WO2014132689A1 - Dispositif à semi-conducteur en carbure de silicium - Google Patents

Dispositif à semi-conducteur en carbure de silicium Download PDF

Info

Publication number
WO2014132689A1
WO2014132689A1 PCT/JP2014/050625 JP2014050625W WO2014132689A1 WO 2014132689 A1 WO2014132689 A1 WO 2014132689A1 JP 2014050625 W JP2014050625 W JP 2014050625W WO 2014132689 A1 WO2014132689 A1 WO 2014132689A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon carbide
region
semiconductor device
interface
main surface
Prior art date
Application number
PCT/JP2014/050625
Other languages
English (en)
Japanese (ja)
Inventor
増田　健良
和田　圭司
健二 平塚
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Publication of WO2014132689A1 publication Critical patent/WO2014132689A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0495—Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • the present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device provided with a transistor element and a Schottky barrier diode element.
  • the main determinant of the withstand voltage is the upper limit of the electric field strength that the drift layer forming the withstand voltage holding region can withstand.
  • a drift layer made of Si can be broken at a place where an electric field of about 0.3 MV / cm or more is applied. For this reason, it is necessary to suppress the electric field strength to less than a predetermined value in the entire drift layer of the MOSFET.
  • the simplest method is to reduce the impurity concentration of the drift layer.
  • this method has a disadvantage that the on-resistance of the MOSFET is increased. That is, there is a trade-off relationship between on-resistance and breakdown voltage.
  • a trade-off relationship between on-resistance and breakdown voltage is described for a typical Si MOSFET in consideration of theoretical limits obtained from Si physical property values.
  • a lower p-type buried layer and an upper p-type buried layer may be added in the n-type base layer on the n-type substrate on the drain electrode. It is disclosed.
  • the lower p-type buried layer and the upper buried layer divide the n-type base layer into a lower stage, an intermediate stage, and an upper stage each having the same thickness. According to this publication, an equal voltage is shared by each of the three stages, and the maximum electric field of each stage is kept below the limit electric field strength.
  • a termination structure having a guard ring also referred to as “Field Limiting Ring”.
  • a guard ring is provided at a depth position corresponding to each of the three steps described above. More specifically, a buried guard ring is provided at each of two different depth positions in the n-type base layer at the terminal portion, and a guard ring is also provided on the surface of the n-type base layer. With these three types of guard rings, the maximum electric field at each stage is kept below the limit strength even in the termination structure.
  • SiC is a material that can sufficiently withstand an electric field strength of 0.4 MV / cm or more. That is, under such electric field strength, the Si layer is easily destroyed, but the SiC layer is not destroyed.
  • a high electric field can be applied in this way, breakdown due to electric field concentration at a specific position in the MOSFET structure becomes a problem.
  • the breakdown phenomenon of the gate insulating film due to the electric field concentration in the gate insulating film, not in the SiC layer is the main determinant of the breakdown voltage.
  • the determination factor of the breakdown voltage differs between the Si semiconductor device and the SiC semiconductor device. For this reason, it is not the best measure to simply apply the technique of the above publication, which is considered to be based on the use of Si, in order to improve the breakdown voltage of the SiC semiconductor device. Therefore, it is preferable to use an optimum structure for the SiC semiconductor device for the structure for maintaining the breakdown voltage.
  • the area of the termination structure in the planar layout directly increases the area of the semiconductor device.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device having a high breakdown voltage and a small size.
  • the silicon carbide semiconductor device of the present invention includes an electrode layer, a silicon carbide film, a first semiconductor element, and a second semiconductor element.
  • the silicon carbide film has a first main surface facing the electrode layer and a second main surface opposite to the first main surface.
  • the silicon carbide film includes a drift layer that forms the first main surface and has the first conductivity type.
  • the drift layer has a first region forming a first main surface and a second region provided on the first region via an interface.
  • the interface has a central surface and an outer edge surface surrounding the central surface on the interface.
  • the silicon carbide film includes a buried region partially provided at the interface and having the second conductivity type.
  • the buried region has an electric field relaxation region partially provided on the central surface and a guard ring region provided on the outer edge surface so as to surround the central surface at the interface.
  • the first semiconductor element is disposed on the center plane of the interface.
  • the second semiconductor element is at least partially disposed on the outer edge surface of the interface.
  • One of the first and second semiconductor elements is a transistor element, and the other of the first and second semiconductor elements is a Schottky barrier diode element.
  • the Schottky barrier diode element has a Schottky electrode provided on the second main surface and at least partially in contact with the drift layer.
  • both the guard ring region for increasing the breakdown voltage and the semiconductor element for the original function of the semiconductor device are arranged on the outer edge surface.
  • region on an outer edge surface is utilized more effectively. That is, the size of the silicon carbide semiconductor device can be reduced while increasing the breakdown voltage of the silicon carbide semiconductor device.
  • the first semiconductor element may be a transistor element.
  • the second semiconductor element may be a Schottky barrier diode element.
  • the transistor element having a high degree of difficulty in suppressing the variation in characteristics is arranged on the central surface where the guard ring region is not provided. Thereby, the influence of the guard ring region on the characteristics of the transistor element can be suppressed. Therefore, it becomes easy to suppress the characteristic variation of the transistor elements.
  • the portion where the Schottky electrode is in contact with the drift layer on the second main surface may be parallel to the first main surface.
  • the portion where the Schottky electrode is in contact with the drift layer on the second main surface may have a portion inclined from the first main surface.
  • the direction of the portion where the Schottky electrode is in contact with the drift layer can be adjusted so that the physical properties of the interface between the Schottky electrode and the drift layer are optimized. Therefore, the characteristics of the Schottky barrier diode can be further improved.
  • a recess may be provided on the second main surface of the silicon carbide film.
  • the recess may have a sidewall made of a drift layer and in contact with the Schottky electrode.
  • the plane orientation of the side wall may be inclined from 50 degrees to 80 degrees from the (000-1) plane.
  • the plane orientation of the side wall in contact with the Schottky electrode is inclined by 50 degrees or more from the (000-1) plane, that is, the carbon plane of silicon carbide.
  • the forward voltage of the Schottky barrier diode can be reduced.
  • the inclination is 80 degrees or less, a highly flat side wall can be easily formed.
  • the portion of the interface that faces the contact surface between the Schottky electrode and the drift layer in the thickness direction may be a buried region.
  • the leakage current path along the thickness direction of the Schottky barrier diode can be blocked by the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
  • the silicon carbide film may partially have a junction region having the second conductivity type on the second main surface.
  • the junction region may be in contact with the Schottky electrode.
  • the Schottky barrier diode can have a junction barrier Schottky (JBS) structure. Therefore, the breakdown voltage of the Schottky barrier diode can be increased.
  • JBS junction barrier Schottky
  • the portion of the interface that faces the junction region in the thickness direction may be at least partially composed of a buried region.
  • the leakage current path of the Schottky barrier diode can be narrowed by the depletion layer extending in the thickness direction from the junction region toward the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
  • the Schottky electrode may be made of a metal having a work function smaller than 4.33 eV.
  • the forward voltage of the Schottky barrier diode can be further reduced as compared with the case where a general Ti electrode is used as the Schottky electrode.
  • the metal may contain at least one atom of Hf, Zr, Ta, Mn, Nb and V.
  • the Schottky electrode includes metal atoms having electronegativity smaller than that of each of silicon carbide atoms Si and C. Therefore, the forward voltage of the Schottky barrier diode can be further reduced.
  • the silicon carbide semiconductor device can be reduced in size while increasing the breakdown voltage of the silicon carbide semiconductor device.
  • FIG. 3 is a partial cross sectional view along a line II in FIG. 2 schematically showing a configuration of the silicon carbide semiconductor device in the first embodiment of the present invention.
  • FIG. 2 is a schematic plan view of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 3 is a schematic partial cross-sectional perspective view of a silicon carbide film included in the silicon carbide semiconductor device in part III of FIG. 2.
  • FIG. 3 is a partial cross sectional view schematically showing a leakage current path of a Schottky barrier diode element in the silicon carbide semiconductor device of FIG. 2.
  • FIG. 8 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 1 is a schematic plan view of the silicon carbide semiconductor device of FIG. 1.
  • FIG. 3 is a schematic partial cross-sectional perspective view of a silicon carbide film included in the silicon carbide semiconductor device in part III of FIG. 2.
  • FIG. 3 is a partial cross sectional
  • FIG. 8 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention.
  • FIG. 11 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 10.
  • FIG. 11 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 10.
  • It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view showing roughly the example of the fine structure of the side wall provided in the silicon carbide film which a silicon carbide semiconductor device has.
  • FIG. 3 is a diagram showing a crystal structure of a (000-1) plane in polytype 4H hexagonal crystal.
  • FIG. 16 is a diagram showing a crystal structure of a (11-20) plane along line XVI-XVI in FIG.
  • FIG. 21 is a diagram showing a crystal structure in the vicinity of the surface of the composite surface in FIG. 14 in the (11-20) plane.
  • FIG. 15 is a diagram when the composite surface of FIG. 14 is viewed from the (01-10) plane. It is a figure which shows the modification of FIG.
  • a semiconductor device 201 (silicon carbide semiconductor device) of the present embodiment includes a single crystal substrate 80, a gate oxide film 91 (gate insulating film), a gate electrode 92, an interlayer insulating film 93, The source electrode 94, the wiring layer 97, the drain electrode layer 98 (electrode layer), the epitaxial film 90 (silicon carbide film), the transistor element ET as the first semiconductor element, and the second semiconductor element And a Schottky barrier diode element ED1.
  • the Schottky barrier diode element ED1 can have a function as a free-wheeling diode electrically connected to the transistor element ET.
  • Single crystal substrate 80 is made of n-type (first conductivity type) silicon carbide.
  • Single crystal substrate 80 preferably has a hexagonal crystal structure, and more preferably has polytype 4H.
  • Epitaxial film 90 (FIGS. 1 and 3) is a silicon carbide film formed epitaxially on single crystal substrate 80.
  • Epitaxial film 90 has lower surface P1 (first main surface) facing drain electrode layer 98 and upper surface P2 (second main surface) opposite to lower surface P1.
  • lower surface P ⁇ b> 1 is arranged on drain electrode layer 98 with single crystal substrate 80 interposed therebetween.
  • Epitaxial film 90 includes drift layer 81 having lower surface P1 and having n-type.
  • Drift layer 81 has lower drift region 81A (first region) forming lower surface P1, and upper drift region 81B (second region) provided on lower drift region 81A via interface IF.
  • Lower drift region 81A preferably has an impurity concentration lower than that of single crystal substrate 80.
  • the impurity concentration of lower drift region 81A is preferably 1 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less, for example, 8 ⁇ 10 15 cm ⁇ 3 .
  • the impurity concentration of upper drift region 81B may be the same as the impurity concentration of lower drift region 81A.
  • the interface IF has a center surface FC and an outer edge surface FT surrounding the center surface FC on the interface IF.
  • a portion of the interface IF located on the inner side of the guard ring 73J (described in detail later) is the center plane FC, and a portion located on the guard ring 73J and on the outer side thereof is the outer edge surface FT. It is.
  • Epitaxial film 90 may be divided into a lower range RA and an upper range RB that are separated from each other by an interface IF.
  • Upper range RB includes upper drift region 81B, base layer 82, source region 83, and contact region 84.
  • Base layer 82 is provided on upper drift region 81B.
  • Base layer 82 has a p-type.
  • the impurity concentration of base layer 82 is, for example, 1 ⁇ 10 18 cm ⁇ 3 .
  • the source region 83 is provided on the base layer 82 and is separated from the upper drift region 81B by the base layer 82.
  • Source region 83 has n-type.
  • Contact region 84 is connected to base layer 82.
  • Contact region 84 has a p-type.
  • a trench TR is provided on the upper surface P2 of the upper side range RB of the epitaxial film 90 on the center surface FC.
  • Trench TR has side wall surface SW and bottom surface BT.
  • Sidewall surface SW passes through source region 83 and base layer 82 and reaches upper drift region 81B. Therefore, the side wall surface SW includes a portion constituted by the base layer 82.
  • the gate oxide film 91 covers each of the sidewall surface SW and the bottom surface BT of the trench TR.
  • Gate oxide film 91 has a portion that connects upper drift region 81 ⁇ / b> B and source region 83 on base layer 82.
  • the gate electrode 92 is provided on the gate oxide film 91.
  • Gate electrode 92 is arranged on sidewall surface SW via gate oxide film 91.
  • the source electrode 94 is in contact with each of the source region 83 and the contact region 84.
  • the source electrode 94 is an ohmic electrode and is made of, for example, silicide.
  • the interlayer insulating film 93 insulates between the gate electrode 92 and the wiring layer 97.
  • the epitaxial film 90 includes a buried region that is partially provided at the interface IF and has p-type (second conductivity type).
  • the buried region has an electric field relaxation region 71 partially provided on the center surface FC and a guard ring region 73 provided on the outer edge surface FT so as to surround the center surface FC at the interface IF.
  • the portion of the interface IF that faces the contact surface between the Schottky electrode 95 and the drift layer 81 in the thickness direction is preferably formed of an embedded region as shown in FIG.
  • the electric field relaxation region 71 has an electric field relaxation region 71T in which the transistor element ET is disposed above and an electric field relaxation region 71D in which the Schottky barrier diode element ED1 is disposed above.
  • the electric field relaxation region 71 preferably has an impurity concentration of about 2.5 ⁇ 10 13 cm ⁇ 3 or more.
  • the guard ring region 73 has a guard ring 73J located on the innermost periphery.
  • Guard ring 73J is preferably in contact with electric field relaxation region 71, and in FIG. 1, is in contact with electric field relaxation region 71D.
  • the guard ring region 73 may further include a guard ring 73I arranged so as to surround the guard ring 73J on the interface IF.
  • Guard ring 73J preferably has an impurity concentration lower than that of electric field relaxation region 71.
  • the epitaxial film 90 may have a field stop region 69 surrounding the guard ring region 73 on the interface IF.
  • Field stop region 69 has n type and has an impurity concentration higher than that of drift layer 81.
  • the transistor element ET as the first semiconductor element is disposed on the center plane FC of the interface IF.
  • the Schottky barrier diode element ED1 as the second semiconductor element is at least partially disposed on the outer edge surface FT of the interface IF. It is preferable that a plurality of semiconductor elements are arranged on the central plane FC, and it is more preferable that the plurality of semiconductor elements do not include the Schottky barrier diode element ED1. A plurality of semiconductor elements may be arranged on the outer edge surface FT. In this case, it is more preferable that the plurality of semiconductor elements do not include the transistor element ET.
  • Schottky barrier diode element ED1 includes Schottky electrode 95 and junction region 85 having a p-type.
  • the Schottky electrode 95 is provided on the upper surface P ⁇ b> 2 and at least partially in contact with the drift layer 81.
  • the Schottky electrode 95 is preferably made of a metal having a work function smaller than 4.33 eV which is the work function of Ti. Schottky electrode 95 is preferably made of a metal having a work function larger than 3.7 eV corresponding to the electric affinity of silicon carbide.
  • the Schottky electrode 95 preferably has a melting point of 1000 ° C. or higher from the viewpoint of stability at high temperatures.
  • the electronegativity of atoms contained in Schottky electrode 95 is preferably smaller than the electronegativity of atoms contained in silicon carbide, that is, the electronegativity of each of Si and C. Examples of the metal that satisfies the above conditions include Hf, Zr, Ta, Mn, Nb, and V.
  • Schottky electrode 95 may be made of any one of these metal elements, or may be made of an alloy containing two or more of these metal elements.
  • junction region 85 is included in the epitaxial film 90 and is partially provided on the upper surface P2. Junction region 85 is in contact with Schottky electrode 95. In the present embodiment, the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 is parallel to lower surface P1. The portion of the interface IF that faces the junction region 85 in the thickness direction is preferably at least partially made of a buried region.
  • the wiring layer 97 is provided in contact with each of the source electrode 94 and the Schottky electrode 95.
  • the wiring layer 97 is made of a conductor. Thereby, the source electrode 94 and the Schottky electrode 95 are electrically connected.
  • the wiring layer 97 is made of, for example, aluminum or an aluminum alloy. Note that in the case where electrical connection between the source electrode 94 and the Schottky electrode 95 is unnecessary, the wiring layer 97 may be formed so as to be in contact with the source electrode 94 and not in contact with the Schottky electrode 95.
  • the maximum electric field strength in RB is preferably configured to be less than 2/3 of the maximum electric field strength in lower range RA, and more preferably configured to be less than half. Such a configuration can be obtained if the impurity concentration of the electric field relaxation region 71 and the guard ring region 73 is sufficiently increased.
  • the plane orientation of the upper surface P2 where the trench TR is not provided preferably has an off angle of 8 degrees or less from the ⁇ 0001 ⁇ plane, more preferably an off angle of 8 degrees or less from the (000-1) plane.
  • Bottom surface BT of trench TR is separated from lower range RA by upper range RB.
  • bottom surface BT has a flat shape substantially parallel to upper surface P2 of epitaxial film 90. Note that the bottom surface BT does not have to be a flat surface, and may be substantially point-like in the cross-sectional view of FIG. 1. In this case, the trench TR has a V-shape.
  • the side wall surface SW is inclined with respect to the upper surface P2 of the epitaxial film 90, so that the trench TR extends in a tapered shape toward the opening.
  • the plane orientation of the side wall surface SW is preferably inclined at 50 ° or more and 80 ° or less with respect to the ⁇ 000-1 ⁇ plane, and is inclined at 50 ° or more and 80 ° or less with respect to the (000-1) plane. It is more preferable.
  • Side wall surface SW has one of the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ and ⁇ 0-11-1 ⁇ when viewed macroscopically. May be.
  • the plane orientation ⁇ 0-33-8 ⁇ has an off angle of 54.7 degrees from the ⁇ 000-1 ⁇ plane.
  • the plane orientation ⁇ 0-11-1 ⁇ has an off angle of 75.1 degrees from the ⁇ 000-1 ⁇ plane. Accordingly, the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ and ⁇ 0-11-1 ⁇ correspond to off-angles of 54.7 to 75.1 degrees. Considering that a manufacturing error of about 5 degrees is assumed for the off angle, the sidewall surface SW is processed by inclining about 50 degrees or more and 80 degrees or less with respect to the ⁇ 000-1 ⁇ plane. The macroscopic plane orientation of SW is easily set to any one of ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ , and ⁇ 0-11-1 ⁇ . In order to increase the channel mobility of the transistor element ET, it is preferable that the side wall surface SW has a predetermined crystal plane (also referred to as a special plane) particularly in a portion on the base layer 82. Details of the special surface will be described later.
  • a predetermined crystal plane also referred to as a special plane
  • both guard ring region 73 for increasing the breakdown voltage and Schottky barrier diode element ED1 which is one of the semiconductor elements for the original function of semiconductor device 201 are provided on outer edge surface FT. Is placed. Thereby, the area
  • the first semiconductor element is the transistor element ET
  • the second semiconductor element is the Schottky barrier diode element ED1.
  • the transistor element ET having a high degree of difficulty in suppressing the variation in characteristics is arranged on the central plane FC where the guard ring region 73 is not provided.
  • the influence of the guard ring region 73 on the characteristics of the transistor element ET can be suppressed. Therefore, it becomes easy to suppress variation in characteristics of the transistor element ET.
  • the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 is parallel to lower surface P1. Thereby, it is not necessary to incline the direction where the Schottky electrode 95 is in contact with the drift layer 81 from the direction parallel to the lower surface P1. Therefore, the manufacturing method of the Schottky barrier diode element ED1 can be simplified.
  • the portion of the interface IF that faces the contact surface between the Schottky electrode 95 and the drift layer 81 in the thickness direction is preferably composed of a buried region (electric field relaxation region 71, guard ring region 73).
  • a buried region electrical field relaxation region 71, guard ring region 73.
  • the Schottky barrier diode element ED1 can have a junction barrier Schottky (JBS) structure. Therefore, the breakdown voltage of the Schottky barrier diode element ED1 can be increased.
  • JBS junction barrier Schottky
  • the depletion layer extending from the junction region 85 obstructs the leakage current path (solid arrow in FIG. 4) of the Schottky barrier diode, thereby reducing the leakage current.
  • the portion of the interface IF that faces the junction region 85 in the thickness direction is at least partially formed of a buried region (electric field relaxation region 71, guard ring region 73).
  • the leakage current path of the Schottky barrier diode can be narrowed by the depletion layer extending in the thickness direction from the junction region 85 toward the buried region. Therefore, the leakage current of the Schottky barrier diode can be further reduced.
  • the Schottky electrode 95 is preferably made of a metal having a work function smaller than 4.33 eV. Thereby, the forward voltage of the Schottky barrier diode can be further reduced as compared with the case where a general Ti electrode is used as the Schottky electrode 95.
  • the metal preferably contains at least one atom of Hf, Zr, Ta, Mn, Nb and V.
  • Schottky electrode 95 contains metal atoms having electronegativity smaller than that of each of silicon carbide atoms Si and C. Therefore, the forward voltage of the Schottky barrier diode can be further reduced.
  • the semiconductor device 201 can handle such a high voltage that a maximum electric field of 0.4 MV / cm or more is applied in the drift layer 81. Further, by providing the electric field relaxation region 71 and the guard ring region 73, the maximum electric field strength in the upper range RB is less than 2/3 of the maximum electric field strength in the lower range RA under the voltage application as described above.
  • the semiconductor device 201 can be configured to be less than half. Thereby, the electric field strength in the upper range RB in the vicinity of the transistor element ET, which is a determining factor of the breakdown voltage, is further reduced.
  • the electric field strength applied to gate oxide film 91 at the corner formed by sidewall surface SW and bottom surface BT of trench TR is further reduced.
  • the maximum electric field strength in the lower range RA is 1.5 times the maximum electric field strength in the upper range RB in the central portion PC, more preferably more than twice.
  • the maximum electric field strength in the side range RA is made higher. Thereby, a higher voltage can be applied to the semiconductor device 201. That is, the breakdown voltage can be increased.
  • lower drift region 81 ⁇ / b> A is formed by epitaxial growth of silicon carbide on single crystal substrate 80.
  • the plane on which epitaxial growth is performed preferably has an off angle of 8 degrees or less from the ⁇ 000-1 ⁇ plane, and more preferably has an off angle of 8 degrees or less from the (000-1) plane.
  • Epitaxial growth can be performed by a CVD method.
  • the source gas for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) can be used. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.
  • the buried region exposed at this time is formed by impurity ion implantation on the interface IF exposed at this time. That is, the electric field relaxation region 71 and the guard ring region 73 are formed. Further, a field stop region 69 may be formed.
  • the order of forming the impurity regions is arbitrary.
  • the acceptor impurity for example, aluminum can be used.
  • phosphorus may be used as the donor impurity.
  • upper drift region 81B is formed by the same method as lower drift region 81A. Thereby, an epitaxial film 90 having a lower range RA and an upper range RB is obtained.
  • an impurity region is formed by implanting impurity ions onto the upper surface P2 of the epitaxial film 90.
  • base layer 82 is formed on upper drift region 81B.
  • a source region 83 separated from upper drift region 81B by base layer 82 is formed on base layer 82.
  • a contact region 84 extending from the upper surface P2 to the base layer 82 is formed.
  • a junction region 85 is also formed. The order of forming the impurity regions is arbitrary.
  • the temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
  • the heat treatment time is, for example, about 30 minutes.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon atmosphere.
  • mask layer 61 having an opening is formed on upper surface P ⁇ b> 2 of epitaxial film 90.
  • the opening is formed corresponding to the position of trench TR (FIG. 1).
  • Mask layer 61 is preferably made of silicon dioxide, and more preferably formed by thermal oxidation.
  • thermal etching using the mask layer 61 is performed. Details of the thermal etching will be described later.
  • a trench TR is formed in the upper surface P2 of the epitaxial film 90 by this thermal etching. At this time, a special surface is self-formed on the side wall surface SW of the trench TR, particularly on the base layer 82.
  • the mask layer 61 is removed by an arbitrary method such as etching.
  • gate oxide film 91 is formed on sidewall surface SW and bottom surface BT of trench TR.
  • Gate oxide film 91 has a portion that connects upper drift region 81 ⁇ / b> B and source region 83 on base layer 82.
  • the gate oxide film 91 is preferably formed by thermal oxidation.
  • NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed.
  • the temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour.
  • nitrogen atoms are introduced into the interface region between gate oxide film 91 and base layer 82.
  • a gas other than NO gas may be used as the atmospheric gas.
  • Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing.
  • the heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91.
  • the time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and base layer 82 is further suppressed.
  • other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
  • a gate electrode 92 is formed on the gate oxide film 91.
  • gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween.
  • the gate electrode 92 can be formed, for example, by film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).
  • interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of source region 83 and contact region 84 is exposed on upper surface P2. Next, source electrode 94 in contact with each of source region 83 and n contact region 84 is formed on upper surface P2.
  • drain electrode layer 98 is formed on lower drift region 81A via single crystal substrate 80. Further, Schottky electrode 95 is formed so as to be in contact with each of drift layer 81 and junction region 85 on upper surface P2 after interlayer insulating film 93 and gate oxide film 91 are partially removed as necessary. . Next, the wiring layer 97 is formed. Thereby, the semiconductor device 201 is obtained.
  • terrace portion HX (concave portion) in which Schottky barrier diode element ED2 is formed is provided on upper surface P2 of epitaxial film 90. It has been. Specifically, as shown in the upper right part in FIG. 10, a terrace portion HX having a terrace shape is provided at the edge of the upper surface P2.
  • the terrace portion HX has a side wall SX and a bottom surface BX. At least a part of the side wall SX is composed of the drift layer 81, and the Schottky electrode 95 is in contact with the part.
  • the part where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 includes sidewall SX.
  • the portion where Schottky electrode 95 is in contact with drift layer 81 on upper surface P2 has a portion inclined from lower surface P1.
  • the plane orientation of the side wall SX is preferably inclined from 50 ° to 80 ° from the ⁇ 000-1 ⁇ plane, and more preferably from 50 ° to 80 ° from the (000-1) plane.
  • the side wall SX has one of the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ , and ⁇ 0-11-1 ⁇ when viewed macroscopically. Also good.
  • the plane orientation ⁇ 0-33-8 ⁇ has an off angle of 54.7 degrees from the ⁇ 000-1 ⁇ plane.
  • the plane orientation ⁇ 0-11-1 ⁇ has an off angle of 75.1 degrees from the ⁇ 000-1 ⁇ plane.
  • the plane orientations ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ and ⁇ 0-11-1 ⁇ correspond to off-angles of 54.7 to 75.1 degrees.
  • the side wall SX is processed by inclining about 50 degrees or more and 80 degrees or less with respect to the ⁇ 000-1 ⁇ plane.
  • the macroscopic plane orientation is likely to be any one of ⁇ 0-33-8 ⁇ , ⁇ 0-11-2 ⁇ , ⁇ 0-11-4 ⁇ , and ⁇ 0-11-1 ⁇ .
  • Such a side wall SX is likely to have a “special surface”. When the side wall SX has a special surface, the flatness of the side wall SX can be improved. Details of the special surface will be described later.
  • the direction of the portion where the Schottky electrode 95 is in contact with the drift layer 81 is optimized so that the physical properties of the interface between the Schottky electrode 95 and the drift layer 81 are optimized. Can be adjusted. Therefore, the characteristics of the Schottky barrier diode can be further improved.
  • the plane orientation of the side wall SX is inclined by 50 degrees or more and 80 degrees or less from the (000-1) plane
  • the plane orientation of the side wall in contact with the Schottky electrode 95 is from the (000-1) plane, that is, the silicon carbide carbon plane. , Tilt more than 50 degrees.
  • the forward voltage of the Schottky barrier diode can be reduced.
  • the inclination is 80 degrees or less, a highly flat side wall can be easily formed.
  • the configuration shown in FIG. 11 is obtained by a method substantially similar to that of the first embodiment.
  • the trench TR is formed by etching in the first embodiment
  • the terrace portion HX is further formed in the present embodiment.
  • the formation of the terrace portion HX may be performed simultaneously with the formation of the trench TR, or may be performed separately.
  • gate oxide film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, and drain electrode layer 98 are formed in substantially the same manner as in the first embodiment.
  • Schottky electrode 95 is formed after interlayer insulating film 93 and gate oxide film 91 are partially removed as necessary.
  • the wiring layer 97 is formed. Thereby, the semiconductor device 202 is obtained.
  • diode element ED3 is arranged on center surface FC in addition to transistor element ET.
  • the Schottky barrier diode element ED2 (FIG. 10: Embodiment 2) is provided in the terrace portion HX as a recess, but the diode element ED3 is provided in the trench portion HY as a recess.
  • the trench part HY has side walls SX that face each other and a bottom face BY that connects the side walls SX.
  • the bottom surface BY has a flat shape substantially parallel to the top surface P2 of the epitaxial film 90 in the present embodiment.
  • the bottom surface BY may not be a flat surface, and may be substantially point-like in the cross-sectional view of FIG. 13.
  • the trench portion HY has a V shape.
  • Trench portion HY may have the same shape as trench TR or may have a different shape. When a similar shape is used, the manufacturing method can be further simplified.
  • a Schottky diode element can be formed on the center plane FC.
  • a Schottky barrier diode element ED1 (FIG. 1) or ED2 (FIG. 10) may be arranged instead of the diode element ED3 (FIG. 13). Further, a Schottky barrier diode element may be disposed on the center surface FC, and a transistor element may be disposed on the outer edge surface FT (not shown in FIG. 13).
  • the first semiconductor element disposed on the central plane FC is any one of the Schottky barrier diode elements ED1 to ED3, and the second semiconductor element disposed on the outer edge surface FT is It may be a transistor element ET.
  • Thermal etching is performed by exposing an object to be etched to a reactive gas at a high temperature, and has substantially no physical etching action.
  • the reactive gas is capable of reacting with silicon carbide under heating.
  • the reactive film is supplied to the epitaxial film 90 under heating, whereby the epitaxial film 90 is etched.
  • the reactive gas preferably contains a halogen element.
  • the halogen element preferably contains chlorine or fluorine.
  • a process gas containing at least one of Cl 2 , BCl 3, CF 4 , and SF 6 can be used as the reactive gas.
  • Particularly preferred reactive gas is Cl 2.
  • the process gas may further contain oxygen gas.
  • the process gas preferably contains a carrier gas.
  • the carrier gas for example, nitrogen gas, argon gas or helium gas can be used.
  • the lower limit of the heating temperature of the epitaxial film 90 for thermal etching is preferably about 700 ° C., more preferably about 800 ° C., and further preferably about 900 ° C. from the viewpoint of securing the etching rate.
  • the upper limit of the heating temperature is preferably about 1200 ° C., more preferably about 1100 ° C., and further preferably about 1000 ° C. from the viewpoint of suppressing etching damage.
  • the etching rate of silicon carbide in the thermal etching is, for example, about 70 ⁇ m / hour. Compared to this, the etching rate of silicon dioxide is extremely low, and therefore, if the mask layer 61 (FIG. 7) is made of silicon dioxide, its consumption can be remarkably suppressed.
  • the side wall SX provided with the Schottky barrier diode element ED2 or ED3 preferably has a special surface.
  • the side wall SX having a special surface includes a surface S1 (first surface) having a surface orientation ⁇ 0-33-8 ⁇ .
  • the plane S1 preferably has a plane orientation (0-33-8). More preferably, the sidewall SX microscopically includes the surface S1, and the sidewall SX further microscopically includes a surface S2 (second surface) having a surface orientation ⁇ 0-11-1 ⁇ .
  • “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, a TEM (Transmission Electron Microscope) can be used.
  • the plane S2 preferably has a plane orientation (0-11-1).
  • the surface S1 and the surface S2 of the side wall SX constitute a composite surface SR having a surface orientation ⁇ 0-11-2 ⁇ . That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy).
  • the composite surface SR has an off angle of 62 degrees macroscopically with respect to the ⁇ 000-1 ⁇ plane.
  • “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used.
  • composite surface SR has a plane orientation (0-11-2).
  • the composite surface SR has an off angle of 62 degrees macroscopically with respect to the (000-1) plane.
  • the direction CD is along the direction in which the above-described periodic repetition is performed.
  • the direction CD roughly corresponds to the direction in which the thickness direction of the epitaxial film 90 (the vertical direction in FIG. 10 or FIG. 13) is projected onto the side wall SX.
  • Si atoms are atoms of the A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.
  • the atoms in each of the four layers ABCB constituting one period described above are (0-11-2) It is not arranged to be completely along the plane.
  • the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer.
  • the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when ignoring the atomic level structure is limited to (0-11-2), the surface is microscopic. Can take various structures.
  • a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being.
  • the length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface obtained by averaging the surfaces S1 and S2 corresponds to the (0-11-2) surface (FIG. 16).
  • the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially.
  • a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in.
  • polytypes other than 4H may constitute the surface according to S2).
  • the polytype may be 6H or 15R, for example.
  • the side wall SX may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the side wall SX may include a composite surface SQ that is configured by periodically repeating the composite surface SR (shown in a simplified manner as a straight line in FIG. 19) and the surface S3. The periodic structure can be observed, for example, by TEM or AFM.
  • the off angle of the side wall SX with respect to the ⁇ 000-1 ⁇ plane deviates from 62 degrees that is the ideal off angle of the composite surface SR. This deviation is preferably small, and preferably within a range of ⁇ 10 degrees.
  • a surface included in such an angle range for example, there is a surface whose macroscopic plane orientation is a ⁇ 0-33-8 ⁇ plane.
  • the off angle of the side wall SX with respect to the (000-1) plane deviates from the ideal off angle of the composite surface SR of 62 degrees. This deviation is preferably small, and preferably within a range of ⁇ 10 degrees.
  • a surface included in such an angle range for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.
  • the structure of the gate electrode is not limited to the trench type, but may be a planar type. That is, the trench TR (FIG. 1) may not be provided on the upper surface P2 of the epitaxial film 90, and the gate electrode may be provided on the flat upper surface P2.
  • the transistor element may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET.
  • the transistor element may be an IGBT (Insulated Gate Bipolar Transistor) element.
  • each of the source electrode and the drain electrode corresponds to an emitter electrode and a collector electrode.
  • the channel type of the transistor is not limited to the n-channel type, and may be a p-channel type. In this case, a configuration in which the p-type and the n-type are interchanged in the above-described embodiment can be used. Further, the junction region of the Schottky barrier diode may be omitted when the effect is not necessary. Further, when the single crystal substrate is removed during the manufacture of the semiconductor device, a structure in which the epitaxial film and the drain electrode layer are in direct contact with each other can also be obtained.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un film en carbure de silicium (90) contenant une couche de dérivation (81) formant une première surface principale (P1) et présentant un premier type de conductivité. La couche de dérivation (81) présente une première zone (81A) formant la première surface principale (P1) et une seconde zone (81B) présente sur la première zone (81A), une interface (IF) étant située entre elles. L'interface (IF) présente une surface centrale (FC) et une surface périphérique (FT) entourant la surface centrale (FC). Le film en carbure de silicium (90) contient une zone encastrée en partie disposée dans l'interface (IF) et présentant un second type de conductivité. La zone encastrée présente une zone de détente de champ électrique (71) ménagée dans la surface centrale (FC) et une zone de grille de protection (73) ménagée dans la surface périphérique (FT). Un élément transistor et un élément diode à barrière de Schottky sont disposés sur la surface centrale (FC) et la surface périphérique.
PCT/JP2014/050625 2013-03-01 2014-01-16 Dispositif à semi-conducteur en carbure de silicium WO2014132689A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-040542 2013-03-01
JP2013040542A JP6075120B2 (ja) 2013-03-01 2013-03-01 炭化珪素半導体装置

Publications (1)

Publication Number Publication Date
WO2014132689A1 true WO2014132689A1 (fr) 2014-09-04

Family

ID=51427963

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/050625 WO2014132689A1 (fr) 2013-03-01 2014-01-16 Dispositif à semi-conducteur en carbure de silicium

Country Status (2)

Country Link
JP (1) JP6075120B2 (fr)
WO (1) WO2014132689A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016042621A1 (fr) * 2014-09-17 2016-03-24 株式会社日立製作所 Dispositif à semi-conducteur, module d'onduleur, onduleur, véhicule ferroviaire, et procédé de fabrication de dispositif à semi-conducteur

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6478884B2 (ja) * 2015-09-11 2019-03-06 株式会社東芝 半導体装置
JP6870546B2 (ja) * 2017-09-14 2021-05-12 株式会社デンソー 半導体装置およびその製造方法
SE541402C2 (en) * 2017-09-15 2019-09-17 Ascatron Ab Integration of a schottky diode with a mosfet
JP7333509B2 (ja) * 2018-11-05 2023-08-25 国立大学法人 筑波大学 炭化珪素半導体装置
JP7101101B2 (ja) * 2018-11-15 2022-07-14 ルネサスエレクトロニクス株式会社 半導体装置
JPWO2022102262A1 (fr) * 2020-11-10 2022-05-19

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191109A (ja) * 1995-11-06 1997-07-22 Toshiba Corp 半導体装置
JP2000101101A (ja) * 1998-09-21 2000-04-07 Hitachi Ltd ＳｉＣショットキーダイオード
JP2003197921A (ja) * 2001-12-26 2003-07-11 Kansai Electric Power Co Inc:The 高耐電圧半導体装置
JP2004006647A (ja) * 2002-03-26 2004-01-08 Toshiba Corp 半導体装置
JP2004087555A (ja) * 2002-08-23 2004-03-18 Toko Inc ショットキーバリアダイオード
JP2008016461A (ja) * 2006-06-30 2008-01-24 Toshiba Corp 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19843659A1 (de) * 1998-09-23 2000-04-06 Siemens Ag Halbleiterbauelement mit strukturiertem Halbleiterkörper
JP4832731B2 (ja) * 2004-07-07 2011-12-07 株式会社東芝 電力用半導体装置
JP4599379B2 (ja) * 2007-08-31 2010-12-15 株式会社東芝 トレンチゲート型半導体装置
JP5396953B2 (ja) * 2009-03-19 2014-01-22 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5511019B2 (ja) * 2011-11-04 2014-06-04 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191109A (ja) * 1995-11-06 1997-07-22 Toshiba Corp 半導体装置
JP2000101101A (ja) * 1998-09-21 2000-04-07 Hitachi Ltd ＳｉＣショットキーダイオード
JP2003197921A (ja) * 2001-12-26 2003-07-11 Kansai Electric Power Co Inc:The 高耐電圧半導体装置
JP2004006647A (ja) * 2002-03-26 2004-01-08 Toshiba Corp 半導体装置
JP2004087555A (ja) * 2002-08-23 2004-03-18 Toko Inc ショットキーバリアダイオード
JP2008016461A (ja) * 2006-06-30 2008-01-24 Toshiba Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016042621A1 (fr) * 2014-09-17 2016-03-24 株式会社日立製作所 Dispositif à semi-conducteur, module d'onduleur, onduleur, véhicule ferroviaire, et procédé de fabrication de dispositif à semi-conducteur
JPWO2016042621A1 (ja) * 2014-09-17 2017-04-27 株式会社日立製作所 半導体装置、インバータモジュール、インバータ、鉄道車両、および半導体装置の製造方法

Also Published As

Publication number Publication date
JP6075120B2 (ja) 2017-02-08
JP2014170778A (ja) 2014-09-18

Similar Documents

Publication Publication Date Title
JP6075120B2 (ja) 炭化珪素半導体装置
JP6111673B2 (ja) 炭化珪素半導体装置
JP6064614B2 (ja) 炭化珪素半導体装置およびその製造方法
WO2012169224A1 (fr) Dispositif à semi-conducteur
WO2012137526A1 (fr) Dispositif à semi-conducteur au carbure de silicium
JP6587265B2 (ja) 炭化珪素半導体装置およびその製造方法
WO2013058037A1 (fr) Dispositif semi-conducteur de carbure de silicium et procédé de fabrication de celui-ci
WO2015040966A1 (fr) Dispositif à semi-conducteurs au carbure de silicium et procédé de fabrication de dispositif à semi-conducteurs au carbure de silicium
WO2014141754A1 (fr) Dispositif à semi-conducteur à base de carbure de silicium
JP6171678B2 (ja) 炭化珪素半導体装置およびその製造方法
US20170207311A1 (en) Silicon carbide semiconductor device and method for manufacturing same
US10192967B2 (en) Silicon carbide semiconductor with trench gate
JP6135383B2 (ja) 炭化珪素半導体装置
JP5983415B2 (ja) 炭化珪素半導体装置
JP5958352B2 (ja) 炭化珪素半導体装置およびその製造方法
WO2016204035A1 (fr) Dispositif semi-conducteur en carbure de silicium
JP2015220408A (ja) 炭化珪素半導体装置およびその製造方法
WO2014041879A1 (fr) Dispositif à semi-conducteur à carbure de silicium
JP5187118B2 (ja) 炭化ケイ素半導体装置および炭化ケイ素半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14757293

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14757293

Country of ref document: EP

Kind code of ref document: A1