CN217468441U

CN217468441U - Silicon carbide semiconductor device

Info

Publication number: CN217468441U
Application number: CN202220975064.3U
Authority: CN
Inventors: 袁俊
Original assignee: Hubei Jiufengshan Laboratory
Current assignee: Hubei Jiufengshan Laboratory
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2022-09-20
Anticipated expiration: 2032-04-24

Abstract

The application discloses carborundum semiconductor device, carborundum semiconductor device includes: the silicon carbide epitaxial layer is provided with a first surface and a second surface which are opposite, and the first surface comprises a grid region and source regions positioned on two sides of the grid region; the surface of the grid electrode region is provided with a first groove; a first withstand voltage masking structure formed in the silicon carbide epitaxial layer on the basis of the first trench; the grid structure is positioned in the first groove, and a metal grid is arranged on the surface of the grid structure; the surface of the source electrode region is internally provided with a second voltage-resistant masking structure; a metal source electrode is arranged on the surface of the source electrode region; the first surface is provided with a well region which is positioned between the first groove and the second voltage-resistant masking structure. The silicon carbide semiconductor device is provided with a first voltage-resistant masking structure in the silicon carbide epitaxial layer based on the first groove, and a second voltage-resistant masking structure in the surface of the source electrode region, so that the voltage resistance of the corner region at the bottom of the first groove is improved, and the problem that breakdown easily occurs in an electric field concentration region is solved.

Description

Silicon carbide semiconductor device

Technical Field

The present application relates to the field of semiconductor device technology, and more particularly, to a silicon carbide (SiC) semiconductor device.

Background

With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The main structure of an electronic device that realizes various functions is an integrated circuit, and semiconductor devices are important constituent electronic components of the integrated circuit. Silicon carbide semiconductor devices have become a major development in the semiconductor field due to their superior characteristics in high power applications.

However, in the application field of high-power devices, the silicon carbide semiconductor device is easy to have a breakdown problem in an electric field concentration area due to the existence of a higher electric field.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a silicon carbide semiconductor device, which comprises:

a silicon carbide semiconductor device, comprising:

the silicon carbide epitaxial layer is provided with a first surface and a second surface which are opposite, and the first surface comprises a grid region and source regions positioned on two sides of the grid region;

a first groove is formed in the surface of the grid electrode region;

a first voltage-resistant masking structure formed within the silicon carbide epitaxial layer based on the first trench;

a gate structure located in the first trench;

a metal grid is arranged on the surface of the grid structure;

a second voltage-resistant masking structure is arranged in the surface of the source region;

a metal source electrode is arranged on the surface of the source electrode region;

the first surface is provided with a well region which is positioned between the first groove and the second voltage-resistant masking structure.

Preferably, in the silicon carbide semiconductor device, the first withstand voltage masking structure is located on a side of the well region facing the second surface in a depth direction of the first trench, and is not in contact with the well region.

Preferably, in the silicon carbide semiconductor device, the first trench is a first double-step trench;

the grid structure comprises polycrystalline silicon filling the first groove, and a first insulating medium layer is arranged between the first groove and the filled polycrystalline silicon;

the first voltage-resistant masking structure comprises doped regions located in the side walls and the bottom surface of the first-level trench facing the second surface.

Preferably, in the silicon carbide semiconductor device, the depth of the well region relative to the first surface is smaller than the depth of a step between two levels of trenches in the first double-step trench, and the first voltage-resistant masking structure is located on one side, facing the second surface, of the step between two levels of trenches in the first double-step trench.

Preferably, in the silicon carbide semiconductor device, the first trench is a first double-step trench; polycrystalline silicon is filled in the first double-step groove, and a first insulating medium layer is arranged between the first double-step groove and the filled polycrystalline silicon;

the thickness of the insulating medium layer at the bottom of the first double-step groove is larger than that of the insulating medium layer on the side wall of each groove in the first double-step groove and is larger than that of the insulating medium layer on the step between the adjacent two grooves.

Preferably, in the silicon carbide semiconductor device, the source region has a multi-step trench in a surface thereof; polycrystalline silicon is filled in the multi-step groove, and a second insulating medium layer is arranged between the multi-step groove and the filled polycrystalline silicon;

the second voltage-resistant masking structure includes a doped region formed within the silicon carbide epitaxial layer based on the multi-step trench.

Preferably, in the silicon carbide semiconductor device, the first trench is a first double-step trench; the multi-step groove is a second double-step groove, and the depth of the first double-step groove is the same as that of the second double-step groove.

the multistage step groove is a three-stage step groove, and the depth of the three-stage step groove is greater than that of the first double-stage step groove.

Preferably, in the silicon carbide semiconductor device, the second withstand voltage masking structure includes a doped region in the silicon carbide epitaxial layer located around the sidewall, the step, the bottom, and the opening of the multi-step trench.

Preferably, in the silicon carbide semiconductor device, the thickness of the second insulating medium layer at the bottom of the multi-step trench is greater than the thickness of the second insulating medium layer on the side wall of each step of the multi-step trench, and is greater than the thickness of the second insulating medium layer on the step between two adjacent steps of the multi-step trench.

Preferably, in the silicon carbide semiconductor device, the second withstand voltage masking structure is an ion implantation region formed in the source region.

Preferably, in the silicon carbide semiconductor device, the ion implantation region is implanted to a depth not less than the depth of the first trench.

As can be seen from the above description, in the silicon carbide semiconductor device and the manufacturing method thereof provided in the present application, the silicon carbide semiconductor device includes: the silicon carbide epitaxial layer is provided with a first surface and a second surface which are opposite, and the first surface comprises a grid region and source regions positioned on two sides of the grid region; the surface of the grid electrode region is provided with a first groove; a first voltage-resistant masking structure formed within the silicon carbide epitaxial layer based on the first trench; a gate structure located within the first trench; a metal grid is arranged on the surface of the grid structure; a second voltage-resistant masking structure is arranged in the surface of the source region; a metal source electrode is arranged on the surface of the source electrode region; the first surface is provided with a well region which is positioned between the first groove and the second voltage-resistant masking structure. The silicon carbide semiconductor device is provided with a first voltage-resistant masking structure in the silicon carbide epitaxial layer based on the first groove, and a second voltage-resistant masking structure in the surface of the source electrode region, so that the voltage-resistant performance of the corner region at the bottom of the first groove is improved, and the problem that breakdown easily occurs in an electric field concentration region is solved.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.

FIG. 1 is a schematic diagram of a DMOSFET structure;

FIG. 2 is a schematic diagram of a UMOSFET structure;

fig. 3 is a schematic structural diagram of a silicon carbide semiconductor device according to an embodiment of the present application;

fig. 4 is a schematic structural view of another silicon carbide semiconductor device according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another silicon carbide semiconductor device according to an embodiment of the present disclosure;

fig. 6 is a schematic structural view of another silicon carbide semiconductor device according to an embodiment of the present application;

fig. 7 to fig. 29 are schematic flow charts illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Because of its excellent characteristics, SiC materials have a strong attraction in terms of high power, and thus are one of the ideal materials for high-performance power MOSFETs. The SiC vertical power MOSFET device mainly comprises a lateral double-diffused DMOSFET and a vertical gate-trench UMOSFET.

As shown in fig. 1, fig. 1 is a schematic structural diagram of a DMOSFET, which includes: a substrate 2 of n + (heavily n-type doped); an n- (n-type lightly doped) drift region 3 disposed on a surface of the substrate 2; a p-type well region 4 located within the drift region 3; and a source region 5 located within the p-type well region, the source region 5 comprising an n + doped region 51 and a p + (p-type heavily doped) doped region 52. A grid dielectric layer 7 is arranged on the surface of the drift region 3, and a grid 8 is arranged on the surface of the grid dielectric layer 7. The surface of the substrate 2 facing away from the drift region 3 has a drain 1.

The DMOSFET structure adopts a plane diffusion technology, adopts refractory materials such as a polysilicon gate as a mask, and defines a p base region and an n + source region by using the edge of the polysilicon gate. The DMOS name is derived from this double diffusion process. And forming a surface channel region by utilizing the side diffusion difference of the p-type base region and the n + source region.

As shown in fig. 2, fig. 2 is a schematic structural diagram of a UMOSFET, and the difference from the structure shown in fig. 1 is that a U-shaped groove is provided in the UMOSFET, a gate dielectric layer 7 covers the surface of the U-shaped groove, and a gate 8 is filled in the U-shaped groove. UMOSFET with vertical gate trench structure, its name is derived from U-type trench structure. The U-shaped groove structure is formed in the grid region by reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the active region channel width), which results in a significant reduction in the on-state characteristic resistance of the device.

After years of research in the industry, planar SiC MOSFETs have been introduced into commercial products by some manufacturers. For the common lateral DMOSFET structure, the modern technological progress has reached the degree that the reduction of the MOS cell size cannot reduce the on-resistance, mainly because the on-resistance per unit area is difficult to reduce to 2m Ω · cm even with smaller lithographic size due to the limitation of the JFET neck region resistance ² And the trench structure can effectively solve the problem. The U-shaped groove structure is shown in figure 2, and the groove etching technology in each process of manufacturing the memory storage capacitor is adopted, so that the transverse direction of a conductive channel is changed into the longitudinal direction, compared with the common structure, the JFET neck resistance is eliminated, the cell density is greatly increased, and the current processing capacity of the power semiconductor is improved.

However, SiC UMOSFETs still have several problems in practical process fabrication and application:

1) the high electric field in the SiC drift region causes the electric field on the gate dielectric layer to be very high, which is exacerbated at the corners of the trench, thereby causing rapid breakdown of the gate dielectric layer at high drain voltages; the electrostatic effect to harsh environments and the high voltage spikes in the circuit are poorly tolerated.

2) The limited depth of ion implantation makes many targeted trench gate protection structures and anti-surge designs technically difficult to implement.

3) Due to the material characteristics of SiC, the thickness of the bottom of the single rectangular or U-shaped gate trench serving as a silicon dioxide layer is usually thinner in the high-temperature furnace tube oxidation process, so that the pressure resistance of the bottom of the trench and the reliability of a device are reduced.

In order to solve the above problem, the technical scheme of the application provides a silicon carbide semiconductor device based on a first trench, a first voltage-resistant masking structure is formed in a silicon carbide epitaxial layer, a second voltage-resistant masking structure is formed in the surface of a source electrode region, the voltage-resistant performance of a corner region at the bottom of the first trench is improved, the problem that breakdown easily occurs in an electric field concentration region is solved, and the electrostatic bearing capacity of the device to severe environments and the tolerance capacity to high-voltage spikes in a circuit are improved. And the first voltage-resistant masking structure can be formed based on the first groove, so that the ion implantation depth during the formation of the first voltage-resistant masking structure can be increased, and various designs for protecting the groove grid and resisting surge are realized conveniently in the process. Furthermore, an insulating medium layer with larger thickness can be formed at the bottom of the groove, so that the problem that a silicon dioxide layer with larger thickness cannot be formed in the groove in the conventional high-temperature furnace tube oxidation process is solved, and the voltage-resisting capability of the bottom of the groove and the reliability of a device are further improved.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

As shown in fig. 3, fig. 3 is a schematic structural diagram of a silicon carbide semiconductor device according to an embodiment of the present application, where the silicon carbide semiconductor device includes:

the silicon carbide epitaxial layer 11 is provided with a first surface and a second surface which are opposite, wherein the first surface comprises a grid region and source regions positioned on two sides of the grid region;

the surface of the gate region has a first trench 12 therein;

a first withstand voltage mask structure 13 formed in the silicon carbide epitaxial layer 11 on the basis of the first trench 12;

a gate structure g located in the first trench 12;

a metal grid G is arranged on the surface of the grid structure;

a second voltage-resistant masking structure 14 is arranged in the surface of the source region;

a metal source electrode S is arranged on the surface of the source electrode region;

the first surface has a well region W therein, which is located between the first trench 12 and the second voltage-resistant masking structure 14.

The silicon carbide semiconductor device is characterized in that a first voltage-resistant masking structure 13 is formed in the silicon carbide epitaxial layer 11 based on the first groove 12, and a second voltage-resistant masking structure 14 is formed in the surface of the source region, so that the voltage resistance of the corner region at the bottom of the first groove 12 is improved, the problem that breakdown is easy to occur in an electric field concentration region is solved, and the electrostatic bearing capacity of the device to severe environment and the bearing capacity of high-voltage peaks in a circuit are improved. Moreover, the first voltage-resistant masking structure 13 can be formed based on the first trench 12, so that the ion implantation depth during the formation of the first voltage-resistant masking structure 13 can be increased, and various designs for trench gate protection and surge resistance can be realized conveniently in the process.

Furthermore, an insulating medium layer with larger thickness can be formed at the bottom of the groove, so that the problem that a silicon dioxide layer with larger thickness cannot be formed in the groove in the conventional high-temperature furnace tube oxidation process is solved, and the voltage-resisting capability of the bottom of the groove and the reliability of a device are further improved.

Optionally, the silicon carbide epitaxial layer 11 is prepared on the surface of the semiconductor substrate 10, and the second surface faces the semiconductor substrate 10. A metal drain D is provided on a surface of the semiconductor substrate 10 on a side away from the silicon carbide epitaxial layer 11. The metal source S and the metal drain D may be Ti, Al, or the like, and the metal drain D may be one or more of Ni, Ti, Al, or Ag.

The doping types of the silicon carbide epitaxial layer 11 and the semiconductor substrate 10 are the same, and the doping types of the well region W, the first voltage-resistant masking structure 13 and the second voltage-resistant masking structure 14 are the same and opposite to the doping type of the epitaxial layer 11. The P-type doping and the N-type doping are of opposite type. The silicon carbide epitaxial layer 11 of the well region W near the first surface has an ion implantation region 17 with a doping type opposite to that of the well region W, and when the well region W is doped P-type, the ion implantation region 17 may be an N + ion implantation region.

The semiconductor substrate 10 may be an N + (N-type heavily doped) silicon carbide substrate; the epitaxial layer 11 is an N- (N-type lightly doped) silicon carbide epitaxial layer and is used as a drift region of the semiconductor device; the well region W is a P-type well region. The first and second withstand

voltage masking structures

13 and 14 include P + (P type heavy doping) ion implantation regions. It should be noted that, in the embodiments of the present application, the doping type of each region of the device is not limited to the description of the embodiments, and the doping type may be set according to the requirement to form a PMOS or NMOS structure.

In the depth direction of the first trench, the first voltage-resistant masking structure 13 is located on one side of the well region W facing the second surface and is not in contact with the well region W, that is, in the vertical direction of fig. 3, the first voltage-resistant masking structure 13 is located below the well region W and is not in contact with the well region W.

In the manner shown in fig. 3, the first trench 12 is a first double-step trench; the gate structure g comprises polysilicon filling the first trench 12, and a first insulating medium layer 151 is arranged between the first trench 12 and the filled polysilicon; the first voltage-resistant masking structure 13 includes doped regions in sidewall surfaces and in bottom surfaces of the first one-level trenches facing the second surface. The first insulating dielectric layer 151 is a gate oxide layer, which may be silicon dioxide.

The first double-step groove is provided with two-step grooves and a step structure positioned between the two-step grooves, one-step groove of the first double-step groove is close to the first surface, the other step of the first double-step groove is close to the second surface, and the opening of the one-step groove close to the first surface is larger than the opening of the one-step groove close to the second surface. Based on the sacrificial layer of the first-stage groove side wall of the first-stage groove close to the first surface of the first double-stage groove, the first double-stage groove is subjected to ion implantation to form a first voltage-resistant masking structure 13, so that the condition that the first double-stage groove is close to the first surface of the first-stage groove and generates ion implantation due to ion scattering during the ion implantation is avoided, the first voltage-resistant masking structure 13 is located below the well region W, the contact between the first voltage-resistant masking structure and the well region W is avoided, the abnormal problem of channel opening of a semiconductor device caused by the contact between the first voltage-resistant masking structure and the well region W is avoided, and the normal work of the device is ensured.

The first insulating medium layer 151 extends to the outside of the first trench 12, covering the first surface. The first insulating medium layer 151 has an opening on the first surface for disposing the metal ohmic contact layer 18, and the source metal S is connected to the silicon carbide epitaxial layer 11 through the metal ohmic contact layer 18 at the opening.

The depth of the well region W relative to the first surface is smaller than the depth of the step between the two-level trenches in the first double-level stepped trench, and the first voltage-resistant masking structure 13 is located on one side of the step between the two-level trenches in the first double-level stepped trench, which faces the second surface.

In the manner shown in fig. 3, the source region has a multi-step trench 16 in the surface thereof; polycrystalline silicon is filled in the multi-step trench 16, and a second insulating medium layer 152 is arranged between the multi-step trench 16 and the filled polycrystalline silicon; the second voltage-resistant masking structure 14 includes a doped region formed within the silicon carbide epitaxial layer 11 based on the multi-step trench.

Wherein, the first insulating dielectric layer 151 on the surface of the first trench 12 and the second insulating dielectric layer 152 on the surface of the multi-step trench 16 are formed simultaneously with the same material. The filled polysilicon within the first trench 12 is formed simultaneously with the polysilicon filled in the multi-step trench 16.

The second voltage-resistant masking structure 14 includes doped regions in the silicon carbide epitaxial layer 11 around the sidewall, the step, the bottom, and the opening of the multi-step trench 16, that is, the second voltage-resistant masking structure 14 is disposed in the silicon carbide epitaxial layer around the sidewall, the step, the bottom, and the opening of the multi-step trench 16.

In the manner shown in fig. 3, the first trench 12 is a first double-step trench; the multi-step trench 16 is a second two-step trench, and the depth of the first two-step trench is the same as that of the second two-step trench, and both trenches can be prepared by the same process flow.

In the embodiment of the present application, the multi-step trench 16 is not limited to a two-step trench, and may also be a step trench larger than 2 steps. The number of trench step levels of the multi-step trench 16 may be set based on device thickness parameters and ion implantation depth requirements.

In the embodiment of the present application, the silicon carbide semiconductor device may be a silicon carbide MOSFET device. In the embodiment shown in fig. 3, a trench gate is formed in the gate region based on the first trench 12, and a trench source is formed in the source region on both sides of the gate region based on the multi-step trench 16. The first trench 12 and the multi-step trench 16 may be both double-step trenches, and in this case, a silicon carbide MOSFET device having a double-step trench structure is formed.

As shown in fig. 4, fig. 4 is a schematic structural diagram of another silicon carbide semiconductor device according to an embodiment of the present application, and based on the manner shown in fig. 3, in the manner shown in fig. 4, the first trench 12 is a first double-step trench; the multistage step groove 16 is a three-stage step groove, and the depth of the three-stage step groove is greater than that of the first double-stage step groove.

As shown in fig. 5, fig. 5 is a schematic structural diagram of another silicon carbide semiconductor device according to an embodiment of the present application, and in the silicon carbide semiconductor device shown in fig. 5, the first trench 12 is a first double-step trench; the first double-step trench is filled with polysilicon, the gate structure g includes polysilicon filling the first double-step trench, and a first insulating medium layer 151 is provided between the first double-step trench and the filled polysilicon. Based on the manner shown in fig. 3, in the silicon carbide semiconductor device shown in fig. 5, the thickness of the first insulating medium layer 151 at the bottom of the first double-step trench is greater than the thickness of the first insulating medium layer 151 on the sidewall of each level of trench in the first double-step trench, and is greater than the thickness of the first insulating medium layer 151 on the step between two adjacent levels of trenches.

In the manner shown in fig. 5, the thickness of the second insulating medium layer 152 at the bottom 16 of the multi-step trench is greater than the thickness of the second insulating medium layer 152 on the sidewall of each step of the multi-step trench 16, and is greater than the thickness of the second insulating medium layer 152 on the step between two adjacent steps of the multi-step trench. The second insulating dielectric layer 152 and the first insulating dielectric layer 151 are the same insulating dielectric layer 15.

Obviously, on the basis of the method shown in fig. 4, the first insulating dielectric layer 151 and the second insulating dielectric layer 152 may be disposed to have a thickness at the bottom of the trench that is greater than the thickness of the other regions of the trench.

According to the silicon carbide semiconductor device, a trench gate can be formed on the basis of the first trench 12 in the gate region, a trench source can be formed on the basis of the multi-step trenches 16 in the source regions on two sides of the gate region, the first voltage-resistant masking structure 13 is formed at the bottom of the first trench 12 through ion implantation, and the second voltage-resistant masking structure 14 is formed in the silicon carbide epitaxial layer 11 on the bottom, the side wall of the multi-step trench 16 and the step between the two steps of trenches through ion implantation. Both the first and second voltage-

resistant masking structures

13 and 14 may be P + (P-type heavily doped) regions.

Based on the first trench 12 and the multi-step trench 16, a first voltage-resistant masking structure 13 and a second voltage-resistant masking structure 14 are respectively formed in the silicon carbide epitaxial layer 11 through ion implantation, so that the problems that a deeper P + masking layer is difficult to form in a silicon carbide material and the damage caused by high-dose and high-energy P + ion implantation is caused are solved, the reliability of a device is improved, and meanwhile, a grid trench can be better shielded and protected. After the first and second withstand

voltage masking structures

13 and 14 are formed by ion activation, silicon dioxide layers are grown on the surfaces of the first trench 12 and the multi-step trench 16 to serve as a first insulating medium layer 151 and a second insulating medium layer 152, then polysilicon is filled in the first trench 12 and the multi-step trench 16, and then metal electrodes are formed, so that the silicon carbide MOSFET device with the double-step trench structure is completed.

As shown in fig. 6, fig. 6 is a schematic structural diagram of another silicon carbide semiconductor device according to an embodiment of the present application, and the second voltage-resistant masking structure 14 is an ion implantation region formed in the source region. In this way, an ion implantation region with a set depth is directly formed as the second voltage-resistant masking structure 14 through an ion implantation forming process without forming a trench in the source region. In the mode shown in fig. 6, in order to achieve a better withstand voltage masking effect, the implantation depth of the ion implantation region is not less than the depth of the first trench 12.

Based on the foregoing embodiments, another embodiment of the present application further provides a method for manufacturing a silicon carbide semiconductor device, which is used for manufacturing the silicon carbide semiconductor device according to the foregoing embodiments, and the manufacturing method may be as shown in fig. 7 to fig. 29.

Referring to fig. 7 to 29, fig. 7 to 29 are schematic flow charts of a method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present application, where the method includes:

step S11: as shown in fig. 7, an epitaxial wafer is provided, the epitaxial wafer includes a silicon carbide epitaxial layer 11, the silicon carbide epitaxial layer 11 has a first surface and a second surface opposite to each other, and the first surface includes a gate region and source regions located at two sides of the gate region.

The silicon carbide semiconductor device may be fabricated using an N + silicon carbide semiconductor substrate 10 having an N-silicon carbide epitaxial layer 11. Wherein a second surface of the silicon carbide epitaxial layer 11 faces the semiconductor substrate 10.

Step S12: as shown in fig. 8 to 16, a first trench 12 is formed in the gate region.

Before forming the first trenches 12, the well region W, the ion implantation region 17, and the electric field buffer region 19 are formed in the silicon carbide epitaxial layer 11 by ion implantation at the first surface. The ion implantation region 17 and the electric field buffer region 19 are located in the surface of the source region and in the well region W.

The fabrication method is described by taking the source region having the multi-step trench 16 as an example, and the subsequent process forms the second voltage-resistant masking structure 14 based on the multi-step trench 16. The electric field buffer region 19 can solve the problems of leakage and breakdown of the multi-step trench 16 at the opening position due to the thin thickness of the second voltage-resistant masking structure 14, and improves the manufacturability and reliability of the device. The doping type of the electric field buffer region 19 and the second voltage-resistant masking structure 14 are the same, and both may be N + doped, for example. The doping types of the ion implantation region 17 and the second voltage-resistant masking structure 14 are opposite, and the ion implantation region 17 may be an N + doping region.

Taking the first trench 12 as a first double-step trench and the multi-step trench 16 as a second double-step trench as an example, the first double-step trench may be formed simultaneously with the second double-step trench, and the specific processes for forming the first double-step trench and the second double-step trench are as follows:

step S121: as shown in fig. 8, a well region W, and an ion implantation region 17 and an electric field buffer region 19 located in the well region are formed by ion implantation at the first surface.

For silicon carbide materials, ion implantation is generally performed at 500-600 ℃ by high temperature ion implantation equipment to reduce damage to the crystal lattice of the silicon carbide material.

Step S122: as shown in fig. 12, a first level trench etch is performed on the first surface.

The first-level trench may be formed by etching using a plasma dry etching process, such as RIE or ICP etching. The etching principle for silicon carbide material is shown in fig. 9-11. First, as shown in FIG. 9, SiO is deposited on a silicon carbide material by a deposition process such as CVD ₂ As a mask layer, a photoresist PR is spin-coated on the surface of the mask layer, the photoresist PR with a desired pattern is formed by exposure and development, then the mask layer is etched based on the patterned photoresist PR as shown in fig. 10 to form a patterned mask layer, and finally, as shown in fig. 11, the silicon carbide material is etched based on the patterned mask layer to form a trench on the surface thereof. The general processes of photoetching, etching and the like of the semiconductor are not described in detail in the subsequent process.

As shown in FIG. 12, when etching to form the first level trench, a layer of SiO may be deposited by CVD ₂ As the mask layer 21, CF is used ₄ 、SF ₆ The gas containing F radicals, or the gas containing Cl radicals such as chlorine, and the mixed gas of Ar and oxygen, are etched in the gate region and the source regions on both sides by plasma etching equipment ICP or RIE to form first-level trenches in the gate region and the source regions, respectively. The depth of the first-stage groove is 10nm-3 mu m, and further, the depth of the first-stage groove can be set to be 800nm-1 mu m, so that the device has better performance.

Step S123: as shown in fig. 13, the first-level trench is filled with SiO ₂ A dielectric layer 22. SiO can be deposited by CVD process ₂ Dielectric layer 22, SiO ₂ The dielectric layer 22 fills the first level trench and covers the mask layer 21.

Step S124: as shown in fig. 14, the reticles 23 of the second level trenches are aligned.

In SiO ₂ The dielectric layer 22 is spin-coated with a photoresist, which is not shown in fig. 14, and the photoresist is exposed and developed based on a reticle 23 to pattern the photoresist.

The mask 23 has a first hollow area for forming a second-level trench of the trench gate in the gate area and a second hollow area for forming a second-level trench of the trench source in the source area. In the mask 23, the opening of the first hollow area is smaller than the opening of the first-level trench in the gate area, and the opening of the second hollow area is larger than the opening of the first-level trench in the source area.

Step S125: as shown in FIG. 15, based on SiO ₂ And etching the photoresist on the surface of the dielectric layer 22 to form second-level trenches on the basis of the first-level trenches of the gate region and the source region respectively.

With CF ₄ 、SF ₆ The gas containing F radicals, or the gas containing Cl radicals such as chlorine, and the mixed gas of Ar and oxygen, are etched in the gate region and the source regions on both sides by plasma etching equipment ICP or RIE to form second-stage trenches in the gate region and the source regions, respectively. The etching depth of the second-stage groove is 100nm-3 um; furthermore, the etching depth of the second-level trench can be set to be 300-500nm, so that the device has better performance.

The opening of the first hollow-out region is smaller than that of the first-stage groove in the gate region, so that the second-stage groove with larger depth can be formed at the bottom of the first-stage groove in the gate region in an etching mode, and the first double-stage groove is formed. Based on the mode, when the first double-step groove is formed in the gate region, SiO is reserved on the side wall of the first-stage groove, close to the first surface, of the first double-step groove while the first double-step groove is formed ₂ The dielectric layer 22 is used as a sacrificial layer to prevent ions from approaching the first bi-level step trench to the second bi-level step trench when the first voltage-resistant masking structure 13 is formed in the subsequent processThe scattering problem of the side wall of the primary groove on one surface solves the problem of abnormal opening of the groove caused by the scattering problem, ensures the normal work of the device and improves the reliability of the device.

Because the opening of the second hollow area is larger than the opening of the first-stage groove in the source area, when the source area is etched downwards, the size of the upper part of the first-stage groove is increased, the depth of the lower part of the first-stage groove is increased, and therefore the second double-stage step groove is formed. Based on the mode, SiO on the side wall, the step and the bottom surface of the second double-step groove can be removed ₂ And the dielectric layer 22 is subjected to ion implantation after a second double-step trench is formed in the source region, so that the second withstand voltage masking structure 14 is formed by performing ion implantation on the side wall, the step and the silicon carbide epitaxial layer 11 at the bottom of the second double-step trench.

As shown in fig. 16, fig. 16 is an SEM image of forming a double-step trench in the source region and the gate region according to the manufacturing method of the embodiment of the present invention, and it can be seen from the SEM image that the double-step trench having a good shape can be formed in the gate region and the source region respectively by the manufacturing method of the embodiment of the present invention.

Step S13: as shown in fig. 17 to 20, a first withstand voltage masking structure 13 is formed within the silicon carbide epitaxial layer on the basis of the first trench.

A second voltage-resistant masking structure 14 is arranged in the surface of the source region; the first surface has a well region W therein, which is located between the first trench 12 and the second voltage-resistant masking structure 14.

The first trench 12 is a first double-step trench; a multi-step groove 16 is formed in the surface of the source region; the method of preparing the first and second voltage-

resistant masking structures

13 and 14 includes: based on the first double-step trench and the dielectric layer 22 of the first double-step trench close to the side wall of the first surface first-step trench, performing ion implantation on the side wall and the bottom of the first double-step trench close to the side wall of the second surface first-step trench, and forming the first voltage-resistant masking structure 13 in the silicon carbide epitaxial layer of the side wall and the bottom of the first double-step trench close to the side wall and the bottom of the second surface first-step trench; based on the multi-step trench 16, ion implantation is performed on the bottom of the multi-step trench 16, the step of each level of trench, and the sidewall, and the second voltage-resistant masking structure 14 is formed in the silicon carbide epitaxial layer at the bottom of the multi-step trench, the step of each level of trench, and the sidewall.

The multistage-step trench 16 may be provided as a second two-stage-step trench having the same depth as the first two-stage-step trench; in other forms, the multi-step trench 16 may be a three-step trench, and the depth of the three-step trench is greater than the depth of the first double-step trench.

In step S13, first, as shown in fig. 17, ion implantation is performed based on the patterned mask layer 21 and the dielectric layer 22 to form the first and second withstand

voltage masking structures

13 and 14. P + ion implantation may be performed on the trench sidewall and the trench bottom at 500-600 ℃ by using a high temperature ion implantation device to form the first voltage-resistant masking structure 13 and the second voltage-resistant masking structure 14, and then as shown in fig. 18, the masking layer 21 and the dielectric layer 22 may be removed, and the silicon dioxide masking may be removed by using a buffered HF wet method to remove the masking layer 21 and the dielectric layer 22.

For P + ion implantation of silicon carbide devices, the typical implanted ions are Al ions; the ion implantation energy can be from hundreds of KeV to several MeV, and the dosage is 1E12cm ^-2 -1E16cm ^-2 (ii) a The implantation depth is from several hundred nm to several micrometers.

Particularly, in the first double-step trench, since the sidewall of the first-step trench close to the first surface is blocked by the dielectric layer 22 with a thickness of tens to hundreds of nanometers, even a micron-sized thickness, the first double-step trench as the well region W of the channel region is not affected by the P + ion implantation during the ion implantation.

As shown in fig. 19, fig. 19 is an SEM image of the first and second voltage-

resistant masking structures

13 and 14 formed by the manufacturing method of the embodiment of the present application, and based on fig. 19, it can be known that after the P + ion implantation is completed, the well region W as the channel region is not affected by the P + ion implantation, and the reliability and stability of the device are improved.

As shown in fig. 20, fig. 20 is an SEM image of the source region P + ion before and after implantation according to the method of the present embodiment. The left image is the SEM image of the corresponding region P + ion implantation of the second double-step trench. The right image is an SEM image of the P + ion-implanted region corresponding to the second two-step trench, and the lower-grayscale region in the right image is an SEM slice image formed after Al ion implantation.

As can be seen from the above description, the first double-step trench is used for the trench gate, and the dielectric layer 22 is retained on the sidewall of the first-step trench close to the first surface while the first double-step trench is formed according to the method of the present application, so that when the first double-step trench is subjected to ion implantation, P + ion implantation can be performed on the bottom and sidewall of the first-step trench close to the second surface, and meanwhile, the sidewall of the first-step trench close to the first surface is prevented from being doped due to P + ion scattering, so that the problem of abnormal opening of the subsequent trench MOSFET channel caused by the above is solved.

Step S14: as shown in fig. 21-23, a gate structure g is formed in the first trench;

the first trench 12 is a first double-step trench; a multi-step groove 16 is formed in the surface of the source region; polycrystalline silicon is filled in the first double-step groove and the multi-step groove; the gate structure g comprises polycrystalline silicon filled in the first double-stage groove; insulating medium layers 15 are arranged between the first double-step groove and the filled polycrystalline silicon and between the multi-step groove 16 and the filled polycrystalline silicon; the gate structure g comprises polysilicon filled in the first double-step trench. The part of the insulating dielectric layer 15 located in the first trench 12 is a first insulating dielectric layer 151, which is used as a gate dielectric layer of the trench gate, and the part located in the multi-step trench 16 is a second insulating dielectric layer 152.

In step S14, as shown in fig. 21, an insulating dielectric layer 15 is formed to cover the first surface and the surfaces of the first trench 12 and the multi-step trench 16, and the insulating dielectric layer in the first trench 12 is used as a gate dielectric layer of the trench gate. Optionally, the insulating dielectric layer 15 is a SiO2 layer. The insulating dielectric layer 15 may be grown in a high temperature furnace, oxygen may be introduced into the high temperature furnace at 1100 ℃ to 1350 ℃, SiO2 may be grown by oxidation on the first surface, the first trench 12, and the surface of the multi-step trench 16 to form the insulating dielectric layer 15, and the thickness of the insulating dielectric layer 15 may be 40 nm to 70 nm.

Next, as shown in fig. 22, after the insulating dielectric layer 15 is formed, the first trench 12 and the multi-step trench 16 are filled with polysilicon. Introducing silane or DCS gas, Ar and doping gas phosphorane borane containing phosphorus or B and the like into an LPCVD furnace tube at 540-800 ℃; after the chemical cracking reaction, polysilicon is generated, and the thickness of the polysilicon can be 400nm to several um.

As shown in fig. 23, the polysilicon is etched by using a mixed gas of HBr, chlorine, and oxygen to remove the polysilicon on the first surface.

Step S15: as shown in fig. 24 and 25, a metal gate electrode is formed on the surface of the gate structure g, and a metal source electrode is formed on the surface of the source region, thereby forming the silicon carbide semiconductor device shown in fig. 3.

The metal gate G is positioned on the surface of the polycrystalline silicon filled in the first double-step groove; the metal source S is located on the surface of the polysilicon filled in the multi-step trench 16.

In step S15, as shown in fig. 24, the insulating dielectric layer 15 on the first surface is etched to form an opening exposing the first surface. CHF may be used ₃ 、CF ₄ And etching the first insulating medium layer 15 in the preset area on the surface of the source electrode area by using F-based gas or Cl-containing chlorine-based gas and the like to form a required opening.

Then, as shown in fig. 25, a metal ohmic contact layer 18 is formed in the opening region of the first insulating dielectric layer 15 to reduce contact resistance of the metal source S and the first surface. A single layer of Ni or multiple layers of metal such as Ti/Ni/Al may be PVD deposited in the source region and stripped or etched away except the source region, followed by rapid thermal annealing at 900-1100 c for 30 seconds-5 minutes to form the metal ohmic contact layer 18.

Finally, a metal gate G is formed on the surface of the trench gate, a metal source S is formed on the surface of the trench source, and a metal drain D is formed on the surface of the semiconductor substrate 10 away from the silicon carbide epitaxial layer 11, thereby forming the silicon carbide semiconductor device shown in fig. 3. The subsequent metal processes of the gate, the source and the like, the passivation layer, the polyimide PI glue, the back drain and the like are conventional process methods, and are not described again.

In the method shown in fig. 7-25, the silicon carbide semiconductor device shown in fig. 3 can be fabricated by taking as an example that the first trench 12 is a first double-step trench and the source region has a second double-step trench. In the mode, when P + ions are implanted into the bottom of the first double-step groove, the problem that when P + ions are implanted in the conventional single-step groove design, due to the fact that P + ions are also implanted into the side wall of the upper portion of the groove due to the fact that a mask and the side wall of the groove are scattered, a withstand voltage masking structure is connected with a well region W serving as a channel region, and therefore channel opening is abnormal is avoided.

Based on the methods shown in fig. 7-25, a silicon carbide mosfet device with a double step trench structure can be formed, and double step trenches can be formed in the gate region and the source regions on both sides of the gate region. Specifically, the gate region has a first double step trench for forming a trench gate, and the source region has a second double step trench for forming a trench source. A first pressure-resistant masking structure 13 is formed in the bottom of the first-stage groove close to the second surface of the first-stage groove and a silicon carbide epitaxial layer 11 in the side wall of the first-stage groove, and a second pressure-resistant masking structure 14 is formed in the bottom of the second double-stage groove, the side wall of each-stage groove and the silicon carbide epitaxial layer 11 of each stage.

If the high-energy and high-dose ion implantation is adopted for more than 1-2um, the serious ion implantation damage to the silicon carbide material is easily caused, and the reliability problem of long-term working of subsequent devices is caused. In the implementation of the application, the double-stage step trench based on the source electrode region forms a trench source electrode structure, the injection of a P + electric field masking structure with the depth of more than 1-2um can be easily realized in the source electrode region, the side wall and the bottom of a trench gate can be well shielded and protected, and the gate reliability of a silicon carbide MOSFET device is enhanced.

Meanwhile, for the trench gate with the first double-step trench, when P + ions are implanted into the bottom of the first double-step trench, the problem that subsequent trench MOSFET channel opening abnormality is caused due to P + ions implanted into the trench side wall due to scattering of the mask and the trench side wall in the existing scheme for preparing the trench gate by using the single-step trench in the industry is solved.

In the embodiment of the application, the silicon carbide semiconductor device with the double-step groove structure and the manufacturing process can also be extended to the scheme of the multi-step groove structure, so that deeper P + ion implantation distribution depth and better electric field shielding protection for a grid region can be achieved, and a semi-super junction structure can be formed. Therefore, in order to form a new P + ion implantation in the source region to form a deeper second withstand voltage masking structure 14 in the source region, a three-step trench may be formed in the source region and a deeper P + mask protection structure may be formed in the source region to fabricate the silicon carbide semiconductor device shown in fig. 4. As shown in fig. 26, fig. 26 is an SEM image of a three-step trench according to an embodiment of the present disclosure.

In another aspect, a method of forming the second voltage-resistant masking structure 14 includes: forming an ion implantation region in the source region by an ion implantation method as the second withstand voltage masking structure 14; the implantation depth of the ion implantation area is not less than the depth of the first groove. This manner can form a silicon carbide semiconductor device as shown in fig. 6. In this way, a two-step trench structure is formed only in the gate region, and the second voltage-resistant masking structure 14 is formed in the source region by directly implanting high-energy and high-dose P + ions to form electric field shielding and protection for the trench gate, and the process method may refer to the process flow of the device structure shown in fig. 3, which is not described in detail in this embodiment.

In other manners, the thickness of the insulating medium layer 15 at the bottom of the first double-step trench may be set to be greater than the thickness of the insulating medium layer 15 on the sidewall of each level of trench in the first double-step trench, and be greater than the thickness of the insulating medium layer 15 on the step between two adjacent levels of trenches; the thickness of the insulating medium layer 15 at the bottom of the multi-step trench 16 is greater than the thickness of the insulating medium layer 15 on the side wall of each step of the multi-step trench 16 and greater than the thickness of the insulating medium layer 15 on the step between two adjacent steps of the multi-step trench, so that the silicon carbide semiconductor device shown in fig. 5 is formed.

The process and structure that can be further selectively optimized based on the methods shown in fig. 7-25 are to form the first and second voltage-

proof masking structures

13 and 14 after ion implantation and high-temperature activation are completed, and then to form SiO by CVD ₂ Filling the grooves of the gate region and the source region by a process, and then adopting a pair of SiO ₂ : gas ICP or RIE plasma etching process with high SiC selectivity ratio for back-etching the groove and the SiO on the first surface ₂ Etching off SiO in the first surface, the first double-step groove and the first groove close to the first surface ₂ SiO at the bottom of the first double-step trench and the second double-step trench ₂ (ii) a Then, SiO on the side wall of the high-temperature furnace tube is grown ₂ And polysilicon filling. Therefore, thicker insulating medium layers can be formed at the bottoms of the first double-step groove and the second double-step groove, the voltage resistance of the grid medium layer at the bottom of the grid of the groove of the device can be further improved, and the reliability of the device is improved.

This process can be illustrated in fig. 27-29, with the following specific method:

first, as shown in fig. 27, in addition to the structure shown in fig. 18, SiO is filled in the double-step trench of both the gate region and the source region ₂ Layer 31. A denser furnace thermal oxide process, such as TEOS or HTO thermal silica process, can be used to oxidize the silicon dioxide through SiH ₄ Or DCS gas, reacts with NO or O2 to form grooves on the surface of the double-step grooveDepositing a layer of dense SiO ₂ Layer 31.

Then, as shown in FIG. 28, the SiO on the first surface is removed by etching ₂ Layer 31 and SiO in double step trench ₂ Layer 31 of SiO of predetermined thickness remaining in the first-level trench on the side close to the second surface ₂ Layer 31. Can adopt a plasma etching process to select SiO ₂ : gases with SiC having a high etch selectivity, e.g. C ₄ F ₈ And etching back to reserve SiO with preset thickness at the bottom of the first-stage groove close to one side of the second surface ₂ Layer 31.

As shown in FIG. 29, SiO is grown on the first surface and the surfaces of the two double-step trenches ₂ And (3) introducing oxygen into a high-temperature furnace tube at 1100-1350 ℃ to grow SiO2 with the thickness of 40-70 nm. The SiO ₂ SiO remaining in the layer and in the bottom of the previous trench ₂ Layer 31 forms the insulating dielectric layer 15.

By adopting the method shown in fig. 27-29, the insulating dielectric layer 15 with a larger thickness can be formed at the bottom of the trench, so that the voltage resistance at the bottom of the trench gate of the device can be further increased, and the reliability of the device can be further improved.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It is to be understood that in the description of the present application, the drawings and the description of the embodiments are to be regarded as illustrative in nature and not as restrictive. Like numerals refer to like structures throughout the description of the embodiments. Additionally, the figures may exaggerate the thicknesses of some layers, films, panels, regions, etc. for ease of understanding and ease of description. It will also be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In addition, "on …" means that an element is positioned on or under another element, but does not essentially mean that it is positioned on the upper side of another element according to the direction of gravity.

The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship relative to an orientation or positional relationship shown in the drawings for ease of description and simplicity of description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A silicon carbide semiconductor device, characterized by comprising:

a first groove is formed in the surface of the grid electrode region;

a gate structure located within the first trench;

a metal grid is arranged on the surface of the grid structure;

2. The silicon carbide semiconductor device according to claim 1, wherein the first voltage-resistant masking structure is located on a side of the well region facing the second surface in a depth direction of the first trench without contacting the well region.

3. The silicon carbide semiconductor device according to claim 1, wherein the first trench is a first double-step trench;

the first voltage-resistant masking structure comprises doped regions in the sidewall surfaces and the bottom surfaces of the first double-step trench facing the second surface.

4. The silicon carbide semiconductor device according to claim 3, wherein a depth of the well region with respect to the first surface is smaller than a depth of a step between two levels of trenches in the first double-step trench, and the first voltage-resistant masking structure is located on a side of the step between two levels of trenches in the first double-step trench toward the second surface.

5. The silicon carbide semiconductor device according to claim 1, wherein the first trench is a first double-step trench; polycrystalline silicon is filled in the first double-step groove, and a first insulating medium layer is arranged between the first double-step groove and the filled polycrystalline silicon;

6. The silicon carbide semiconductor device according to claim 1, wherein the source region has a multi-step trench in a surface thereof; polycrystalline silicon is filled in the multistage step groove, and a second insulating medium layer is arranged between the multistage step groove and the filled polycrystalline silicon;

7. The silicon carbide semiconductor device according to claim 6, wherein the first trench is a first double-step trench; the multi-step groove is a second double-step groove, and the depth of the first double-step groove is the same as that of the second double-step groove.

8. The silicon carbide semiconductor device according to claim 6, wherein the first trench is a first double-step trench;

9. The silicon carbide semiconductor device of claim 6, wherein the second voltage-resistant masking structure comprises a doped region within the silicon carbide epitaxial layer located around the sidewalls, steps, bottom and openings of the multi-step trench.

10. The silicon carbide semiconductor device according to claim 6, wherein the thickness of the second insulating medium layer at the bottom of the multi-step trench is greater than the thickness of the second insulating medium layer on the sidewall of each of the plurality of steps of trenches and greater than the thickness of the second insulating medium layer on the step between two adjacent steps of trenches.

11. The silicon carbide semiconductor device according to claim 1, wherein the second voltage-resistant masking structure is an ion implantation region formed in the source region.

12. The silicon carbide semiconductor device according to claim 11, wherein an implantation depth of the ion implantation region is not less than a depth of the first trench.