JP4559839B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention creates a space (air, vacuum, etc.) in a dielectric layer in a semiconductor device formed using a laminated structure in which a lower semiconductor layer, a dielectric layer, and an upper semiconductor layer are sequentially laminated. Regarding the method. Note that the dielectric in the present specification is interpreted in the same meaning as an insulator in terms of physical properties.

In the semiconductor layer formed on the buried dielectric layer, an island-shaped region isolated from the remaining semiconductor layer by an insulator-filled trench is formed, and a lateral semiconductor switching element is formed in the island-shaped region The device is known. In this type of semiconductor device, a technique generally referred to as a RESURF effect is used. The RESURF effect is a technique for depleting a wide range of a semiconductor layer when the lateral semiconductor switching element is turned off by optimizing the impurity concentration and thickness of the semiconductor layer. This RESURF effect alleviates electric field concentration on the surface portion of the semiconductor layer, so that it is possible to avoid breakdown in this region. That is, a large potential difference can be maintained in the lateral direction.
Therefore, when the semiconductor layer is adjusted so as to obtain the RESURF effect, the breakdown voltage (BV) of the semiconductor device is determined by a potential difference that can be held in the vertical direction. The larger the potential difference, the higher the breakdown voltage of the semiconductor device. This relationship can be expressed by the following equation.
BV = Ecr · (d / 2) + Ecr · (εsemi · Tins / εins) (1)
Here, Ecr is a critical electric field strength causing avalanche breakdown. εsemi is the relative dielectric constant of the semiconductor layer. εins is the relative dielectric constant of the buried dielectric layer. d is the thickness of the semiconductor layer. Tins is the thickness of the buried dielectric layer. The first term on the right side of the equation (1) indicates the shared voltage that can be held in the thickness direction of the semiconductor layer, and the second term indicates the shared voltage that can be held in the thickness direction of the embedded dielectric layer.

In order to maintain a state where the RESURF effect is obtained, it is not preferable to change the thickness (d) of the semiconductor layer. Therefore, in order to improve the breakdown voltage (BV) of the semiconductor device, measures are taken by changing the thickness (Tins) or the relative dielectric constant (εins) of the embedded dielectric layer in the second term on the right side of the equation (1). Is preferred. However, an extremely long processing time is required to obtain a buried dielectric layer having a large thickness (Tins). Therefore, it is preferable to take measures to change the relative dielectric constant of the portion corresponding to the buried dielectric layer by forming a space in the buried dielectric layer. For example, when a space having a relative dielectric constant of about 1.0 is formed in a buried dielectric layer made of silicon oxide (SiO ₂ ) having a relative dielectric constant of about 3.9, the potential difference that can be maintained is increased 3.9 times. be able to. Techniques for forming a space in the buried dielectric layer are disclosed in Patent Document 1 and Patent Document 2.
JP-A-6-188438 JP 2004-146461 A

Both Patent Document 1 and Patent Document 2 use a bonding technique. For example, in Patent Document 1, in order to form a space in a buried dielectric layer, a semiconductor layer whose surface is covered with an oxide film and a back surface which is covered with an oxide film and a part of the oxide film are recessed. A method is proposed in which a space defined by the recess is manufactured by bonding together semiconductor layers on which are formed.
However, when these bonding manufacturing techniques are employed, it is difficult to specify the position of the formed space due to the presence of the semiconductor layer. For this reason, when forming a semiconductor switching element after forming space, it becomes difficult to form a semiconductor switching element according to the position of space. Patent Document 1 proposes a technique for creating a recess for alignment in another oxide film region in order to specify the position of the space. However, there is a problem in that the number of steps for aligning with this separate recess increases.
The present invention proposes a method capable of easily creating a space at a desired position with respect to a dielectric layer interposed between upper and lower semiconductor layers.

The semiconductor device manufacturing method of the present invention reaches the dielectric layer from the surface of the first semiconductor layer of the laminated structure in which the substrate, the dielectric layer, and the first semiconductor layer are sequentially laminated, and the island shape of the first semiconductor layer Forming an insulator-filled trench that insulates and isolates the region from the surrounding region. Furthermore, a step of polishing the substrate from the back surface of the laminated structure to expose the dielectric layer is provided. In addition, the method includes a step of removing the exposed dielectric layer in at least a part of a region corresponding to the island-shaped region, and a step of fixing the second semiconductor layer to the back surface of the remaining dielectric layer.
Each of the substrate, the dielectric layer, and the first semiconductor layer is not limited to being composed of a single material, and each may be composed of a plurality of members. For example, the first semiconductor layer may be stacked with a plurality of semiconductor layers.
The semiconductor switching element is formed in an island region surrounded by the insulator-filled trench. In order to improve the breakdown voltage of the semiconductor switching element, and hence the breakdown voltage of the semiconductor device, it is necessary to form a space in the dielectric layer corresponding to the island-shaped region.
In the above manufacturing method, the substrate is polished from the back surface to expose the dielectric layer. At this time, if an optical method is used, the position of the insulator-filled trench that makes a round through the dielectric layer can be easily confirmed from the back surface side. Therefore, after removing at least a part of the dielectric layer existing inside the circular insulator-filled trench, the second semiconductor layer is fixed to the back surface of the remaining dielectric layer, thereby corresponding to the island-shaped region. A space can be easily formed in the region. By using a sufficiently sophisticated technique such as an existing polishing technique or a bonding technique, a high breakdown voltage semiconductor device can be obtained with certainty.

It is preferable that the method further includes a step of fixing the support plate to the surface of the first semiconductor layer prior to polishing the laminated structure from the back surface.
Even when the substrate is polished, the mechanical strength of the first semiconductor layer can be increased by the support plate, so that the manufacturing process can be carried out stably.

  It is preferable to fix the second semiconductor layer to the back surface of the dielectric layer through an adhesive layer mainly composed of silicon oxide. The adhesion between the second semiconductor layer and the dielectric layer can be strengthened.

It is preferable to further include a step of forming a lateral semiconductor switching element in the island-shaped region after forming the insulator-filled trench.
The lateral semiconductor switching element may be formed at any timing before forming the space or after forming the closed space as long as the insulating filling trench is formed.

In the step of removing the dielectric layer, it is preferable to remove the dielectric layer in a range extending from the high potential region of the lateral semiconductor switching element beyond the range of 50% of the distance between the high potential region and the low potential region.
When a space extending beyond the above range is formed, the breakdown voltage of the semiconductor device can be effectively improved.

It is preferable that the method further includes a step of removing at least a part of the exposed back surface of the first semiconductor layer after removing the dielectric layer.
By adjusting the amount of removal entering the first semiconductor layer from the back surface of the first semiconductor layer, the thickness of the space required for increasing the breakdown voltage of the semiconductor device can be ensured.

It is preferable to include a step of forming a recess in the surface of the second semiconductor layer. Furthermore, it is preferable that the second semiconductor layer is fixed to the back surface of the dielectric layer with the removed region of the dielectric layer and the recess positioned corresponding to each other.
By adjusting the depth of the recess of the second semiconductor layer, the thickness of the closed space required for increasing the breakdown voltage of the semiconductor device can be ensured.

  According to the method for manufacturing a semiconductor device of the present invention, a space can be easily manufactured at a desired position with respect to a dielectric layer interposed between upper and lower semiconductor layers.

The main features of the examples are listed.
(First Form) The laminated structure is a general-purpose SOI substrate.
(2nd form) The insulator filling trench is formed in the annular | circular shape.
(Third embodiment) The thickness and impurity concentration of the drift region are adjusted so that the RESURF effect is obtained.
(Fourth Mode) The space is formed in a substantially flat shape from the high potential region to the low potential region in a plane parallel to the direction connecting the high potential region (for example, drain region) and the low potential region (for example, source region). Has been.

FIG. 1A is a cross-sectional view of the main part of the semiconductor device of the example. FIG. 1B shows a cross-sectional view of the main part corresponding to the line bb in FIG. In this embodiment, a semiconductor device using a semiconductor material containing silicon as a main component is shown as an example. However, the same effects as described below can be obtained even with other semiconductor materials.
The semiconductor device includes a back electrode 22 made of aluminum, for example, and a p-type semiconductor layer 24 formed on the back electrode 22. A buried dielectric layer 26 made of silicon oxide is formed in a partial region on the p-type semiconductor layer 24 via an adhesive layer 82 containing silicon oxide (SiO ₂ ) as a main component. For the adhesive layer 82, for example, a low melting point glass such as borosilicate glass having a film thickness of about several μm can be suitably used. The buried dielectric layer 26 has a thickness of about 4 μm. In the remaining portion where the buried dielectric layer 26 is not formed, a closed space 72 in which air is confined is formed. When the closed space 72 is viewed in plan, it is circular, and the shape of the space is a substantially cylindrical shape with a low height. As will be described later, the closed space 72 has a substantially flat shape extending from below the drain region 54 toward the periphery in a plane parallel to the buried dielectric layer 26. Here, the lateral width of the closed space 72 is L12.

An n ⁻ type semiconductor layer 28 is formed on the buried dielectric layer 26 and the closed space 72. The n ⁻ type semiconductor layer 28 is formed with an insulator-filled trench 32 that makes a circular ring around the position where the closed space 72 is formed. The insulator-filled trench 32 is made of silicon oxide and extends from the surface of the n ⁻ type semiconductor layer 28 to the buried dielectric layer 26. The buried dielectric layer 26 insulates and isolates the inner island region from the remaining n ⁻ type semiconductor layer 28, and a lateral MOSFET is formed in the island region. Note that the n ⁻ type semiconductor layer 28 in the island-like region can be referred to as a drift region 29 when evaluated from the functional surface of the MOSFET. The thickness of the drift region 29 (the thickness of the n ⁻ -type semiconductor layer 28 and the thickness in the vertical direction on the paper) and the impurity concentration are adjusted so that the RESURF effect is obtained. The RESURF effect can be obtained when the product of the thickness of the drift region 29 and the impurity concentration is about 1.2 × 10 ¹² cm ⁻² . In this embodiment, the thickness of the drift region 29 is 30 μm, and the impurity concentration is adjusted to 4 × 10 ¹⁴ cm ⁻³ .

A p-type body diffusion region 34 is formed along the circumference of the insulator-filled trench 32 on the peripheral side of the surface portion of the island-shaped region. The body diffusion region 34 is fixed to the same potential as the surface of the buried dielectric layer 26 via the p ⁺ type trench side diffusion region 36. The trench-side diffusion region 36 can alleviate an electric field that tends to concentrate at the pn junction between the body diffusion region 34 and the drift region 29, particularly at a portion having a large curvature. An n ⁺ -type source diffusion region 38 is formed on the surface portion in the body diffusion region 34. The source diffusion region 38 is formed in a round along the body diffusion region 34. Source diffusion region 38 is separated from drift region 29 by body diffusion region 34. A gate electrode 44 made of polysilicon is opposed to the surface of the body diffusion region 34 separating the source diffusion region 38 and the drift region 29 through a gate insulating film 46 made of silicon oxide. The source diffusion region 38 and the body diffusion region 34 are in contact with the source electrode 42.
An n ⁺ -type drain diffusion region 54 is formed substantially at the center of the island region. The drain diffusion region 54 is in contact with the drain electrode 52. As shown in FIG. 1A, here, the distance between the drain region 54 and the source diffusion region 38 is L10. In this embodiment, this L10 is formed with a thickness of 200 μm.

Next, the operation when this semiconductor device is on will be described.
When a voltage higher than the threshold voltage is applied to the gate electrode 44 in a state where the back electrode 22 and the source electrode 42 are grounded and a positive voltage is applied to the drain electrode 52, the body diffusion region 34 that the gate electrode 44 faces. An inversion layer is formed therein, and the semiconductor device is turned on. The current flows from the source diffusion region 38 to the drain diffusion region 54 via the inversion layer and the drift region 29.

Next, the operation when the semiconductor device is off will be described.
When a voltage lower than the threshold voltage is applied to the gate electrode 44 in a state where the back electrode 22 and the source electrode 42 are grounded and a positive voltage is applied to the drain electrode 52, the body diffusion region 34 that the gate electrode 44 opposes. The inversion layer inside disappears and the semiconductor device is turned off. At this time, the drift region 29 is depleted in a wide range by a depletion layer extending from the pn junction with the body diffusion region 34 and a depletion layer extending from the interface with the buried dielectric layer 26 or the closed space 72 on the back surface. . In addition, since the semiconductor device of this embodiment has a concentric structure, the region where the depletion layer extends can be formed in a well-balanced manner. Thereby, the electric field of the surface part of the drift region 29 is relaxed, and a RESURF effect can be obtained. In other words, the semiconductor device can withstand up to an extremely large lateral potential difference between the drain electrode 52 and the source electrode 42 without being destroyed.
Therefore, the breakdown voltage of the semiconductor device in which such a RESURF effect is obtained is determined by the potential difference that can be held in the vertical direction between the drain electrode 52 and the back electrode 22. This relationship can be expressed by equation (1) shown in paragraph [0002] of this specification. In the case of the present embodiment, the shared voltage that can be held in the thickness direction of the drift region 29 is about 375V. The shared voltage that can be held in the thickness direction of the closed space 72 is about 1170V. Therefore, the breakdown voltage of the semiconductor device of this embodiment is about 1550V. When the closed space 72 is not formed, that is, when the buried dielectric layer 26 is formed over the entire surface between the p-type semiconductor layer 24 and the n ⁻ -type semiconductor layer 28, the buried dielectric layer The shared voltage that can be held in the thickness direction of 26 is 675V. Therefore, the breakdown voltage of this semiconductor device is about 1050V. From this, it can be seen that the withstand voltage is significantly improved by forming the closed space 72 in the embedded dielectric layer 26.

Next, it will be described with reference to FIG. 2 that the lateral width L12 of the closed space 72 affects the effect of improving the breakdown voltage of the semiconductor device. The results shown in FIG. 2 were examined using a diode structure based on the concentric structure of the semiconductor device of FIG. That is, the region corresponding to the source region 38 is replaced with a high-concentration p-type semiconductor diffusion region (which becomes a cathode diffusion region in the diode structure), the thickness of the drift region 29 is 50 μm, and the thickness of the buried dielectric film 26 is 5 μm. This is the result. The distance (L10) between the drain diffusion region 54 (which becomes an anode diffusion region in the diode structure) and the source diffusion region 38 is 200 μm and does not change. The results shown in FIG. 2 are not limited to the studied diode structure, and similar results can be obtained in the MOSFET of FIG. 1 or other semiconductor devices.
FIG. 2 shows the breakdown voltage of the semiconductor device when the width of the closed space (corresponding to L12 shown in FIG. 1A) is variously changed.
As shown in FIG. 2, it can be seen that the breakdown voltage of the semiconductor device is increased when the width of the closed space is increased. In particular, it can be seen that the semiconductor device has an extremely high breakdown voltage when the closed space is formed to extend over 100 μm corresponding to about half of the distance between the drain diffusion region and the source diffusion region.
This result shows that it is extremely effective to form the closed space formed in the buried dielectric layer by extending more than 50% of the distance between the high potential region and the low potential region from the high potential region. It was.

Next, a method for creating the closed space of the semiconductor device shown in FIG. 1 will be described with reference to FIGS.
First, as shown in FIG. 3, a semiconductor substrate 92 made of silicon single crystal, a buried dielectric layer 26 of silicon oxide, n ^- n consists -type silicon single crystal ^- SOI -type semiconductor layer 28 are stacked Prepare a substrate. Since this SOI substrate can use a general-purpose product, the manufacturing cost can be kept low.

Next, as shown in FIG. 4, a trench reaching the buried dielectric layer 26 from the surface of the n ⁻ type semiconductor layer 28 is formed by, for example, RIE (Reactive Ion Etching). Next, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method is performed to fill the trench with silicon oxide, thereby forming the insulator-filled trench 32. As shown in FIG. 1B, the insulator-filled trench 32 is formed in a circle, and the island-shaped region surrounded by the insulator-filled trench 32 is the remaining n ⁻ type semiconductor layer 28. It is isolated from the insulation.

  Next, as shown in FIG. 5, a MOSFET is formed in the island region. This manufacturing method can be created by using an existing manufacturing method or a manufacturing method easily conceived by those skilled in the art. The step of making the MOSFET can also be performed after creating a closed space described below.

Next, as shown in FIG. 6, a polishing support plate 96 is fixed to the surface of the n ⁻ type semiconductor layer 28 with an adhesive 94. As the adhesive 94, for example, an adhesive tape for a wafer made of, for example, an ultraviolet (UV) irradiation curable adhesive can be suitably used.

Next, as shown in FIG. 7, the semiconductor substrate 92 is chemically or mechanically polished from the back surface to expose the embedded dielectric layer 26. This polishing process is performed in combination with plasma etching using, for example, tetrafluoromethane (CF ₄ ), chemical etching using potassium hydroxide (KOH), or other methods as necessary. May be.

Next, as shown in FIG. 8, a photoresist film 98 is patterned on the back surface of the buried dielectric layer 26 by using a photolithography method. At the time of this patterning, for example, if an optical method such as image recognition using an optical microscope, a CCD, or the like is used, the position of the insulator-filled trenches 32 and the insulator filling through the embedded dielectric layer 26 The alignment mark formed with the trench structure can be easily confirmed from the back side. Due to the presence of the support plate 96 formed on the front surface side, it is often difficult to confirm the position of the island-like region from the front surface side. However, in this manufacturing method, the presence of the insulator-filled trench 32 causes the island from the back surface side. It is possible to easily confirm the position and mark of the area. Therefore, the photoresist film 98 can be patterned by a normal alignment technique. The photoresist film 98 is patterned so that the buried dielectric layer 26 existing inside the insulator-filled trench 32 is exposed. The buried dielectric layer 26 is patterned to be exposed in a range extending from the drain diffusion region 54 to more than 50% of the distance between the drain diffusion region 54 and the source region 38.
Next, the embedded dielectric layer 26 exposed from the photoresist film 98 is wet-etched by immersing it in an etching solution containing hydrofluoric acid. The exposed portion of the buried dielectric layer 26 is removed, and the n ⁻ type semiconductor layer 28 is exposed.

Next, as shown in FIG. 9, a p-type semiconductor layer 24 made of silicon single crystal is prepared and fixed to the back surface of the remaining buried dielectric layer 26 via an adhesive layer 82. For the adhesive layer 82, a material mainly composed of silicon oxide can be preferably used. Typically, low-melting glass such as borosilicate glass can be used as the adhesive layer 82, for example. Thereby, the closed space 72 can be easily formed at a position corresponding to the island-shaped region in which the MOSFET is formed.
Next, by depositing aluminum on the back surface of the p-type semiconductor layer 24 to form a back electrode, the high breakdown voltage semiconductor device shown in FIG. 1 can be obtained. Note that the high breakdown voltage semiconductor device shown in FIG. 1 may be obtained by fixing the p-type semiconductor layer 24 on which the back electrode is formed in advance to the back surface of the buried dielectric layer 26.
Similarly, when the lateral semiconductor switching element is formed after the closed space 72 is formed, the closed space 72 exceeds the distance between the drain diffusion region 54 and the source region 38 and exceeds the source from the drain diffusion region 54. Preferably, a lateral semiconductor switching element is formed so that it exists toward the region 38.

The semiconductor device of the above-described embodiment can be configured as a modified example as shown below.
The first modification shown in FIG. 10 is an example in which the closed space 172 has entered the drift region 129. The closed space 172 can be formed by, for example, plasma-etching the back surface of the exposed drift region 129 using tetrafluoromethane (CF ₄ ) after wet-etching the embedded dielectric layer 126. Instead of tetrafluoromethane (CF ₄ ), plasma etching may be performed using, for example, sulfur hexafluoride (SF ₆ ), a mixed gas of tetrafluoromethane and oxygen, or potassium hydroxide (KOH) or the like. The back surface of the drift region 129 can also be formed with low damage by chemical etching. This modification is particularly effective when it is desired to secure the height of the closed space 172 necessary for increasing the breakdown voltage when the buried dielectric layer 126 is thin. Even in this case, it is preferable that the layer thickness and impurity concentration of the drift region 129 are adjusted so that the RESURF effect can be obtained.
A second modification shown in FIG. 11 is an example in which the closed space 272 enters the p-type semiconductor layer 224. The closed space 272 can be formed, for example, by forming a recess in advance in the prepared p-type semiconductor layer 224 by dry etching, chemical etching, or the like. That is, the p-type semiconductor layer 224 can be fixed to the back surface of the buried dielectric layer 226 with the removal region of the buried dielectric layer 226 and the recess thereof positioned in correspondence. This modification is also effective when it is desired to secure the height of the closed space 272 necessary for increasing the breakdown voltage when the buried dielectric layer 226 is thin. Even in this case, the drift region 229 preferably has its layer thickness and impurity concentration adjusted so that the RESURF effect can be obtained.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In the above embodiment, the example of the MOSFET has been described, but the same operation and effect can be obtained also in other semiconductor switching elements such as a diode and an IGBT.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

(A) The principal part sectional drawing of the semiconductor device of an Example is shown. (B) The principal part sectional view corresponding to the bb line of Drawing 1 (a) is shown. The relationship between the lateral width of the closed space and the breakdown voltage of the semiconductor device is shown. A manufacturing process of a semiconductor device of an example is shown (1). The manufacturing process of the semiconductor device of an Example is shown (2). The manufacturing process of the semiconductor device of an Example is shown (3). The manufacturing process of the semiconductor device of an Example is shown (4). The manufacturing process of the semiconductor device of an Example is shown (5). The manufacturing process of the semiconductor device of an Example is shown (6). The manufacturing process of the semiconductor device of an Example is shown (7). The principal part sectional view of the 1st modification is shown. The principal part sectional view of the 2nd modification is shown.

Explanation of symbols

22: back electrode 24: p-type semiconductor layer 26: buried dielectric layer 28: n ⁻ type semiconductor layer 32: insulator-filled trench 34: body diffusion region 36: trench side diffusion region 38: source diffusion region 42: source electrode 44 : Gate electrode 46: gate insulating film 52: drain electrode 54: drain diffusion region 62: field insulating film 72: closed space 82: adhesive layer 92: semiconductor substrate 94: adhesive 96: support plate

Claims (7)

An insulator that reaches the dielectric layer from the surface of the first semiconductor layer of the laminated structure in which the substrate, the dielectric layer, and the first semiconductor layer are sequentially laminated, and that insulates and isolates the island-shaped region of the first semiconductor layer from the surrounding region Forming a filling trench;
Polishing the substrate from the back surface of the laminated structure to expose the dielectric layer;
Removing the exposed dielectric layer in at least a portion of the region corresponding to the island region;
And a step of fixing the second semiconductor layer to the back surface of the remaining dielectric layer.   2. The method according to claim 1, further comprising a step of fixing a support plate to the surface of the first semiconductor layer prior to polishing the laminated structure from the back surface.   The method according to claim 1 or 2, wherein the second semiconductor layer is fixed to the back surface of the dielectric layer through an adhesive layer mainly composed of silicon oxide.   4. The method according to claim 1, further comprising a step of forming a horizontal semiconductor switching element in the island-shaped region after forming the insulator-filled trench.   In the dielectric layer removing step, the dielectric layer is removed in a range extending from a high potential region of the lateral semiconductor switching element to more than 50% of a distance between the high potential region and the low potential region. Item 4. The manufacturing method according to Item 4.   6. The method according to claim 1, further comprising a step of removing at least a part of the exposed back surface of the first semiconductor layer after removing the dielectric layer. A step of forming a recess in the surface of the second semiconductor layer;
The manufacturing method according to claim 1, wherein the second semiconductor layer is fixed to the back surface of the dielectric layer with the removed region of the dielectric layer and the recess corresponding to each other.

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