CN101969062B - Silicon N-type semiconductor combined device on insulator for improving current density - Google Patents

Silicon N-type semiconductor combined device on insulator for improving current density Download PDF

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CN101969062B
CN101969062B CN2010102657946A CN201010265794A CN101969062B CN 101969062 B CN101969062 B CN 101969062B CN 2010102657946 A CN2010102657946 A CN 2010102657946A CN 201010265794 A CN201010265794 A CN 201010265794A CN 101969062 B CN101969062 B CN 101969062B
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钱钦松
魏守明
孙伟锋
陆生礼
时龙兴
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Southeast University
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Abstract

一种提高电流密度的绝缘体上硅N型半导体组合器件,包括:P型衬底,在P型衬底上设埋氧层,在埋氧层上设P型外延层且P型外延层被分割成区域I和II,其中I区为绝缘栅双极型器件区,包括:N型漂移区、P型深阱、N型缓冲阱、P型漏区、N型源区和P型体接触区,在硅表面相应设有场氧化层和栅氧化层,在栅氧化层上设有多晶硅栅;其中II区为高压三极管区,包括:N型三极管漂移区、N型三极管缓冲阱、P型发射区和N型基区,其特征在于II区中的N型基区包在N型缓冲区内部,且I区中P型漏区上的第一漏极金属与II区中N型基区上的第一基极金属通过第二金属连通。本发明在不增加器件面积基础上显著提升器件的电流密度且器件其他性能参数并不改变。

Figure 201010265794

A silicon-on-insulator N-type semiconductor combination device with improved current density, comprising: a P-type substrate, a buried oxide layer is arranged on the P-type substrate, a P-type epitaxial layer is arranged on the buried oxide layer, and the P-type epitaxial layer is divided into regions I and II, where region I is an insulated gate bipolar device region, including: N-type drift region, P-type deep well, N-type buffer well, P-type drain region, N-type source region and P-type body contact region , a field oxide layer and a gate oxide layer are correspondingly provided on the silicon surface, and a polysilicon gate is provided on the gate oxide layer; where II area is a high-voltage triode area, including: N-type triode drift area, N-type triode buffer well, P-type emitter region and an N-type base region, which is characterized in that the N-type base region in the II region is wrapped inside the N-type buffer zone, and the first drain metal on the P-type drain region in the I region and the N-type base region in the II region The first base metal communicates through the second metal. The invention significantly improves the current density of the device without increasing the area of the device and does not change other performance parameters of the device.

Figure 201010265794

Description

一种提高电流密度的绝缘体上硅N型半导体组合器件A silicon-on-insulator N-type semiconductor composite device with improved current density

技术领域 technical field

本发明涉及高压功率半导体器件领域,是关于一种适用于高压应用的提高电流密度的绝缘体上硅N型半导体组合器件。The invention relates to the field of high-voltage power semiconductor devices, and relates to a silicon-on-insulator N-type semiconductor combination device suitable for high-voltage applications with improved current density.

背景技术 Background technique

随着人们对现代化生活需求的日益增强,功率半导体器件的性能越来越受到关注,其中功率半导体器件的可集成性、高耐压、大电流和与低压电路部分的良好的隔离能力是人们最大的技术要求。决定功率集成电路处理高电压、大电流能力大小的因素除了功率半导体器件的种类以外,功率半导体器件的结构和制造工艺也是重要的影响因素。With the increasing demand for modern life, the performance of power semiconductor devices has attracted more and more attention. Among them, the integration, high withstand voltage, high current and good isolation ability of power semiconductor devices are the most important factors for people. technical requirements. The factors that determine the ability of power integrated circuits to handle high voltage and high current are not only the types of power semiconductor devices, but also the structure and manufacturing process of power semiconductor devices.

长久以来,人们采用的功率半导体器件为高压三级管和高压绝缘栅场效应晶体管。这两种器件在满足人们基本的高耐压和可集成性的需求的同时,也给功率集成电路带来了许多的负面影响。对于高压三级管,它的不足有输入阻抗很低,开关速度不高。尽管高压绝缘栅场效应晶体管的输入阻抗非常高,但是电流驱动能力有限,除此之外,它的高耐压和高的导通阻抗呈现出不可避免的矛盾。For a long time, the power semiconductor devices used by people are high-voltage transistors and high-voltage insulated gate field effect transistors. While these two devices meet people's basic needs of high withstand voltage and integrability, they also bring many negative effects to power integrated circuits. For high-voltage triode tubes, its disadvantages are that the input impedance is very low and the switching speed is not high. Although the input impedance of the high-voltage IGSFET is very high, the current driving capability is limited. In addition, its high withstand voltage and high on-resistance present an inevitable contradiction.

随着科学技术的发展,绝缘栅双极型器件的出现解决了人们对功率半导体器件的大部分需求。绝缘栅双极型器件集合了高压三极管和绝缘栅场效应晶体管的优势,具有高的输入阻抗、高的开关速度、高耐压、大的电流驱动能力和低导通阻抗等性能。但是,绝缘栅双极型器件是纵向器件,可集成性能差。后来出现的横向绝缘栅双极型器件解决了这一问题。With the development of science and technology, the emergence of insulated gate bipolar devices has solved most of people's needs for power semiconductor devices. Insulated gate bipolar devices combine the advantages of high-voltage triodes and insulated gate field effect transistors, with high input impedance, high switching speed, high withstand voltage, large current drive capability and low on-resistance. However, the insulated gate bipolar device is a vertical device and has poor integration performance. The lateral insulated gate bipolar device that appeared later solved this problem.

功率半导体器件的可集成性、高耐压、大电流的需求解决后,它的隔离性成为主要的矛盾。主要是在体硅工艺中,高压电路和低压电路同时集成在一个芯片上,高压电路的漏电流会比较高,因此会通过衬底进入低压电路引发低压电路的闩锁,最终造成芯片烧毁。为了解决这一问题,人们提出了绝缘体上硅工艺。After the integration, high withstand voltage, and high current requirements of power semiconductor devices are resolved, its isolation becomes the main contradiction. Mainly in the bulk silicon process, the high-voltage circuit and the low-voltage circuit are integrated on one chip at the same time, the leakage current of the high-voltage circuit will be relatively high, so it will enter the low-voltage circuit through the substrate to cause the latch of the low-voltage circuit, and eventually cause the chip to burn. In order to solve this problem, silicon-on-insulator technology has been proposed.

绝缘体上硅工艺的出现有效地解决了功率半导体器件的隔离问题。目前绝缘体上横向绝缘栅双极型器件已成为功率半导体器件的主力军,广泛应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。The emergence of silicon-on-insulator technology has effectively solved the isolation problem of power semiconductor devices. At present, lateral insulated gate bipolar devices on insulators have become the main force of power semiconductor devices, and are widely used in conversion systems with a DC voltage of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, traction drives and other fields.

围绕着绝缘体上横向绝缘栅双极型器件的一个较大的问题是,与纵向器件相比电流密度不够高,因此常常以加大器件的面积来获得高的电流驱动能力,因而耗费大量的芯片面积,增加了成本。本文介绍了一种新型的提高电流密度的绝缘体上硅N型半导体组合器件,在不增加版图面积的前提下,与同尺寸的普通绝缘体上N型横向绝缘栅双极型器件相比,电流密度大幅度增加。One of the bigger problems surrounding LIGOBI devices is that the current density is not high enough compared to vertical devices, so high current drive capability is often obtained by enlarging the device area, thus consuming a lot of chips area, which increases the cost. This paper introduces a new silicon-on-insulator N-type semiconductor combined device with improved current density. Under the premise of not increasing the layout area, compared with the common N-type lateral insulated gate bipolar device of the same size, the current density increased badly.

发明内容 Contents of the invention

本发明提供一种能够在不改变器件面积的基础上有效提高器件电流密度的绝缘体上硅N型半导体组合器件。The invention provides a silicon-on-insulator N-type semiconductor combined device capable of effectively increasing the current density of the device without changing the device area.

本发明采用如下技术方案:The present invention adopts following technical scheme:

一种提高电流密度的绝缘体上硅N型半导体组合器件,包括:P型衬底,在P型衬底上设有埋氧层,其特征在于,在埋氧层中央设有P型深阱,在P型深阱上设有P型体接触区和N型源区且在P型体接触区和N型源区上设有连通二者的源极金属,在埋氧层上还设有第一隔离区和第二隔离区,由所述的第一隔离区和第二隔离区向埋氧层中心延伸并由此分割形成绝缘栅双极型器件区和高压三极管区,在绝缘栅双极型器件区内设有绝缘栅双极型器件,所述的绝缘栅双极型器件中的源区采用所述的N型源区且所述的N型源区位于绝缘栅双极型器件区内,在高压三极管区内设有高压三极管,所述的高压三极管中的集电区采用所述的P型体接触区,所述的P型体接触区位于高压三极管区内,所述的绝缘栅双极型器件中的第一漏极金属通过第二金属与所述的高压三极管中的第一基极金属连接。A silicon-on-insulator N-type semiconductor combination device for increasing current density, comprising: a P-type substrate, on which a buried oxide layer is arranged, and is characterized in that a P-type deep well is arranged in the center of the buried oxide layer, A P-type body contact region and an N-type source region are arranged on the P-type deep well, and a source metal connecting them is arranged on the P-type body contact region and the N-type source region, and a second layer is arranged on the buried oxide layer. An isolation region and a second isolation region extend from the first isolation region and the second isolation region to the center of the buried oxide layer and are thus divided to form an insulated gate bipolar device region and a high-voltage triode region. An insulated gate bipolar device is provided in the insulated gate bipolar device region, and the source region in the insulated gate bipolar device adopts the N-type source region and the N-type source region is located in the insulated gate bipolar device region Inside, a high-voltage triode is provided in the high-voltage triode area, and the collector area in the high-voltage triode adopts the P-type body contact area, and the P-type body contact area is located in the high-voltage triode area, and the insulation The first drain metal in the gate bipolar device is connected to the first base metal in the high voltage triode through the second metal.

与现有技术相比,本发明具有如下优点:Compared with prior art, the present invention has following advantage:

(1)本发明的半导体组合半导体器件分为两个部分,其中一个部分用于制作绝缘栅双极型器件,另一部分用于制作高压三极管,并同过第二金属将绝缘栅双极型器件的漏极和高压三极管的基极连接在一起,可以在不改变器件总面积的基础上有效的将前者的漏极电流作为流过高压三极管的基极电流进一步放大,从而提高电流密度。该半导体组合器件的等效电路图参见附图4,图5显示了本发明的半导体组合器件与相同面积的绝缘栅双极型器件的电流密度的比较,可见,本发明的半导体组合器件的电流密度比一般绝缘栅双极型器件的电流密度大大提高了。(1) The semiconductor composite semiconductor device of the present invention is divided into two parts, one of which is used to make an insulated gate bipolar device, and the other part is used to make a high-voltage triode, and the insulated gate bipolar device is made of the second metal The drain and the base of the high-voltage transistor are connected together, and the drain current of the former can be further amplified as the base current flowing through the high-voltage transistor without changing the total area of the device, thereby increasing the current density. The equivalent circuit diagram of this semiconductor composite device is referring to accompanying drawing 4, and Fig. 5 shows the comparison of the current density of the semiconductor composite device of the present invention and the insulated gate bipolar device of the same area, as can be seen, the current density of the semiconductor composite device of the present invention Compared with the general insulated gate bipolar device, the current density is greatly improved.

(2)本发明器件的好处在于可以通过调整第一隔离区101与第二隔离区102的夹角来优化绝缘栅双极型器件和高压三极管的版图面积的比例,以达到整个组合半导体器件的电流密度与其他性能(如散热情况等)折衷的最优效果。(2) The advantage of the device of the present invention is that the ratio of the layout area of the insulated gate bipolar device and the high-voltage triode can be optimized by adjusting the angle between the first isolation region 101 and the second isolation region 102, so as to achieve the ratio of the entire combined semiconductor device. The optimal effect of the compromise between current density and other properties (such as heat dissipation, etc.).

(3)本发明器件的在提高电流密度的同时与传统器件相比,并不改变器件原来的版图面积。(3) Compared with traditional devices, the device of the present invention does not change the original layout area of the device while increasing the current density.

(4)本发明器件的在提高电流密度的同时,并不影响器件的耐压水平,器件的基本性能要求仍能满足。图6所示为本发明的半导体组合器件与相同面积一般绝缘栅双极型器件的关态击穿电压的比较图,可见本发明的半导体组合器件的关态击穿电压可以保持与相同面积的一般绝缘栅双极型器件一致。(4) While the current density of the device of the present invention is increased, the withstand voltage level of the device is not affected, and the basic performance requirements of the device can still be met. Fig. 6 shows the comparison diagram of the off-state breakdown voltage of the semiconductor composite device of the present invention and the general insulated gate bipolar device of the same area, as seen the off-state breakdown voltage of the semiconductor composite device of the present invention can be maintained with the same area Generally insulated gate bipolar devices are the same.

(5)本发明器件的制作并不需要额外工艺步骤,与现有的集成电路制造工艺完全兼容。(5) The manufacture of the device of the present invention does not require additional process steps, and is fully compatible with the existing integrated circuit manufacturing process.

附图说明 Description of drawings

图1(a)是本发明组合半导体器件去除钝化保护氧化层后的俯视图。Fig. 1(a) is a top view of the combined semiconductor device of the present invention after removal of the passivation protective oxide layer.

图1(b)是沿着图1(a)的AA’面的剖面图(含有钝化层)。Fig. 1(b) is a cross-sectional view along the AA' plane of Fig. 1(a) (including a passivation layer).

图1(c)是沿着图1(a)的BB’面的剖面图(含有钝化层)。Fig. 1(c) is a sectional view along the BB' plane of Fig. 1(a) (including a passivation layer).

图2是本发明的组合半导体器件三维立体结构图。(去除钝化保护氧化层和所有金属)。Fig. 2 is a three-dimensional structure diagram of the combined semiconductor device of the present invention. (removes passivating protective oxide and all metal).

图3是本发明的半导体组合器件沿AA’面的三维立体剖面图(去除钝化保护氧化层和所有金属)。Fig. 3 is a three-dimensional cross-sectional view of the semiconductor composite device of the present invention along the plane AA' (removing the passivation protective oxide layer and all metals).

图4是本发明的半导体组合器件的等效电路图。Fig. 4 is an equivalent circuit diagram of the semiconductor composite device of the present invention.

图5是本发明的半导体组合器件和相同面积的一般绝缘栅双极型器件的漏极电流密度比较图。Fig. 5 is a comparison diagram of the drain current density of the semiconductor composite device of the present invention and a general insulated gate bipolar device of the same area.

图6是本发明的半导体组合器件和相同面积的一般绝缘栅双极型器件的关态击穿电压比较图。Fig. 6 is a comparison diagram of the off-state breakdown voltage of the semiconductor composite device of the present invention and a general insulated gate bipolar device with the same area.

图7(a)是形成本发明的半导体组合器件中的P型深阱14工艺示意图。Fig. 7(a) is a schematic diagram of the process of forming the P-type deep well 14 in the semiconductor composite device of the present invention.

图7(b)是形成本发明的半导体组合器件中绝缘栅双极型器件区的N型漂移区4以及高压三极管区的N型三极管漂移区4’的工艺示意图。Fig. 7(b) is a schematic diagram of the process of forming the N-type drift region 4 of the insulated gate bipolar device region and the N-type triode drift region 4' of the high-voltage triode region in the semiconductor composite device of the present invention.

图7(c)是形成本发明的半导体组合器件中N漂移区4上的N型缓冲阱5以及N型三极管漂移区4’上的N型三极管缓冲阱5’的工艺示意图。Fig. 7(c) is a schematic diagram of the process of forming the N-type buffer well 5 on the N-drift region 4 and the N-type transistor buffer well 5' on the N-type transistor drift region 4' in the semiconductor composite device of the present invention.

图7(d)是形成本发明的半导体组合器件中绝缘栅双极型器件区的场氧化层8、栅氧化层9以及多晶硅栅10的工艺示意图。FIG. 7( d ) is a schematic diagram of the process of forming the field oxide layer 8 , the gate oxide layer 9 and the polysilicon gate 10 in the insulated gate bipolar device region of the semiconductor composite device of the present invention.

图7(e)是形成本发明的半导体组合器件中P型漏区6、P型发射区15以及N型基区16的工艺示意图。FIG. 7( e ) is a schematic diagram of the process of forming the P-type drain region 6 , the P-type emitter region 15 and the N-type base region 16 in the semiconductor composite device of the present invention.

图7(f)是完全形成本发明的半导体组合器件后,沿着图1(a)的AA’面的剖面图。Fig. 7(f) is a cross-sectional view along the AA' plane of Fig. 1(a) after the semiconductor composite device of the present invention is completely formed.

具体实施方式 Detailed ways

一种提高电流密度的绝缘体上硅N型半导体组合器件,包括:P型衬底1,在P型衬底1上设有埋氧层2,其特征在于,在埋氧层2中央设有P型深阱14,在P型深阱14上设有P型体接触区12和N型源区11且在P型体接触区12和N型源区11上设有连通二者的源极金属72,在埋氧层2上还设有第一隔离区101和第二隔离区102,由所述的第一隔离区101和第二隔离区102向埋氧层2中心延伸并由此分割形成绝缘栅双极型器件区I和高压三极管区II,在绝缘栅双极型器件区I内设有绝缘栅双极型器件,所述的绝缘栅双极型器件中的源区采用所述的N型源区11且所述的N型源区11位于绝缘栅双极型器件区I内,在高压三极管区II内设有高压三极管,所述的高压三极管中的集电区采用所述的P型体接触区12,所述的P型体接触区12位于高压三极管区II内,所述的绝缘栅双极型器件中的第一漏极金属74通过第二金属75与所述的高压三极管中的第一基极金属71连接。A silicon-on-insulator N-type semiconductor composite device with improved current density, comprising: a P-type substrate 1, on which a buried oxide layer 2 is arranged, and is characterized in that a P Type deep well 14, be provided with P type body contact region 12 and N type source region 11 on P type deep well 14 and be provided with the source metal that connects both on P type body contact region 12 and N type source region 11 72. A first isolation region 101 and a second isolation region 102 are also provided on the buried oxide layer 2, which are formed by extending from the first isolation region 101 and the second isolation region 102 to the center of the buried oxide layer 2 The insulated gate bipolar device region I and the high-voltage triode region II are provided with an insulated gate bipolar device in the insulated gate bipolar device region I, and the source region in the insulated gate bipolar device adopts the described The N-type source region 11 and the N-type source region 11 are located in the insulated gate bipolar device region I, and a high-voltage transistor is provided in the high-voltage transistor region II, and the collector region in the high-voltage transistor adopts the described The P-type body contact region 12, the P-type body contact region 12 is located in the high voltage triode region II, the first drain metal 74 in the insulated gate bipolar device communicates with the high voltage through the second metal 75 The first base metal 71 in the triode is connected.

所述的第一隔离区101和第二隔离区102所形成的夹角可以调整,但是由所述的第一隔离区101和第二隔离区102向埋氧层2中心延伸并由此分割形成的两个区域中,钝角所包围的区域必须为绝缘栅双极型器件区I,而锐角所包围的区域必须为高压三极管区II。The angle formed by the first isolation region 101 and the second isolation region 102 can be adjusted, but the first isolation region 101 and the second isolation region 102 extend to the center of the buried oxide layer 2 and are formed by dividing Among the two regions, the region surrounded by the obtuse angle must be the insulated gate bipolar device region I, and the region surrounded by the acute angle must be the high voltage triode region II.

虽然附图说明中的本半导体组合器件结构是采用圆形版图实现形式,但是其实现方式并不仅限于圆形,也可以是跑道型、矩形等其他形状,只要用两个隔离槽101和102将绝缘栅双极型器件和高压三极管隔开并将绝缘栅双极型器件的漏极与高压三极管的基极用金属连接即可。Although the structure of the semiconductor composite device in the description of the accompanying drawings adopts a circular layout, its implementation is not limited to a circle, and it can also be in other shapes such as racetracks, rectangles, etc., as long as two isolation grooves 101 and 102 are used to separate The insulated gate bipolar device and the high voltage triode are separated and the drain of the insulated gate bipolar device is connected to the base of the high voltage triode with metal.

所述的绝缘体上硅N型半导体组合器件P型发射区15与N型基区16的间距为1μm~2μm;The distance between the P-type emitter region 15 and the N-type base region 16 of the silicon-on-insulator N-type semiconductor composite device is 1 μm to 2 μm;

本发明采用如下方法来制备:The present invention adopts following method to prepare:

第一步,取具有P型外延层的绝缘体上硅圆片,根据所设计的绝缘栅双极型器件和高压三极管的面积比例,刻蚀所需要的隔离槽101和102,从而形成绝缘栅双极型器件区I和高压三极管区II,且P型外延层被分割成在绝缘栅双极型器件区I内的第一P型外延层3和在高压三极管区内的第二P型外延层3’。The first step is to take a silicon-on-insulator wafer with a P-type epitaxial layer, and etch the required isolation grooves 101 and 102 according to the designed area ratio of the IGBD device and the high-voltage triode, thereby forming an IGBT Pole type device region I and high-voltage triode region II, and the P-type epitaxial layer is divided into a first P-type epitaxial layer 3 in the insulated gate bipolar device region I and a second P-type epitaxial layer in the high-voltage triode region 3'.

第二步,通过高能量硼离子注入,并高温退火形成P型深阱14。In the second step, the P-type deep well 14 is formed by high-energy boron ion implantation and high-temperature annealing.

第三步,以高能量的磷离子注入,高温退火后在绝缘栅双极型器件区形成N型漂移区4而在高压三极管区形成N型三极管漂移区4’;The third step is to implant high-energy phosphorus ions, and form an N-type drift region 4 in the insulated gate bipolar device region after high-temperature annealing, and form an N-type triode drift region 4' in the high-voltage triode region;

第四步,以高能量的磷离子注入,高温退火后在N漂移区4上形成N型缓冲阱5而在N型三极管漂移区4’上形成N型三极管缓冲阱5’。The fourth step is to implant high-energy phosphorus ions, form an N-type buffer well 5 on the N-type drift region 4 after high-temperature annealing, and form an N-type triode buffer well 5' on the N-type transistor drift region 4'.

第五步,淀积并刻蚀氮化硅,在高温下生长场氧化层。再生长栅氧化层,并淀积多晶硅,刻蚀出多晶硅栅。In the fifth step, silicon nitride is deposited and etched, and a field oxide layer is grown at high temperature. A gate oxide layer is grown again, polysilicon is deposited, and the polysilicon gate is etched.

第六步,通过高剂量的硼离子和磷离子注入,制作各个电极接触区。In the sixth step, each electrode contact area is made by implanting high-dose boron ions and phosphorus ions.

第七步,淀积二氧化硅,刻蚀电极接触孔后淀积金属引线层并刻蚀掉多余金属。The seventh step is to deposit silicon dioxide, etch the electrode contact hole, deposit the metal wiring layer and etch away the excess metal.

第八步,进行钝化层的制作。The eighth step is to make a passivation layer.

Claims (5)

1. silicon-on-insulator N type semiconductor assembling device that improves current density; Comprise: P type substrate (1); On P type substrate (1), be provided with oxygen buried layer (2); It is characterized in that; Central authorities are provided with P moldeed depth trap (14) at oxygen buried layer (2); Being provided with P type body contact zone (12) and N type source region (11) on the P moldeed depth trap (14) and on P type body contact zone (12) and N type source region (11), being provided with the source metal (72) that is communicated with the two, on oxygen buried layer (2), also be provided with first isolated area (101) and second isolated area (102), also cut apart thus to the extension of oxygen buried layer (2) center with second isolated area (102) by described first isolated area (101) and form insulated gate bipolar device district (I) and high-voltage three-pole area under control (II); In insulated gate bipolar device district (I), be provided with insulated gate bipolar device; Source region in the described insulated gate bipolar device adopts described N type source region (11) and described N type source region (11) to be positioned at insulated gate bipolar device district (I), in high-voltage three-pole area under control (II), is provided with the high-voltage three-pole pipe, and the collector region in the described high-voltage three-pole pipe adopts described P type body contact zone (12); Described P type body contact zone (12) is positioned at high-voltage three-pole area under control (II), and first drain metal (74) in the described insulated gate bipolar device is connected with first base metal (71) in the described high-voltage three-pole pipe through second metal (75).
2. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 1; It is characterized in that; Said insulated gate bipolar device comprises: be located at the P type epitaxial loayer (3) on the oxygen buried layer (2); Be provided with N type drift region (4) in P type epitaxial loayer (a 3) upper right side; Be provided with N type buffering trap (5) in the upper right side of N type drift region (4); Be provided with P type drain region (6) and described first drain metal (74) in the upper right side of N type buffering trap (5) and be located at top, P type drain region (6), the silicon face in N type drift region (4) is provided with field oxide (8) and field oxide (8) joins with P type drain region (6), and the silicon face between N type source region (11) and field oxide (8) is provided with gate oxide (9); Gate oxide (9) is provided with the upper surface that polysilicon gate (10) and polysilicon gate (10) extend to field oxide (8), on polysilicon gate (10), is provided with gate metal (73).
3. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 1 and 2; It is characterized in that; Described high-voltage three-pole pipe comprises: be located at the 2nd P type epitaxial loayer (3 ') on the oxygen buried layer (2); Be provided with N type triode drift region (4 ') on the upper left side of the 2nd P type epitaxial loayer (3 '), be provided with N type triode buffering trap (5 ') on the upper left side of N type triode drift region (4 '), on N type triode buffering trap (5 '), be provided with P type emitter region (15) and N type base (16); On P type emitter region (15), be provided with emitter metal (70), on N type base (16), be provided with described first base metal (71).
4. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 3 is characterized in that, P type emitter region (15) is 1 μ m~2 μ m with the spacing of N type base (16).
5. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 3 is characterized in that, described insulated gate bipolar device district (I) and high-voltage three-pole area under control (II) upper surface non-metallic regions are provided with passivation protection oxide layer (13).
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