CN101969062B - Silicon N-type semiconductor combined device on insulator for improving current density - Google Patents
Silicon N-type semiconductor combined device on insulator for improving current density Download PDFInfo
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- CN101969062B CN101969062B CN2010102657946A CN201010265794A CN101969062B CN 101969062 B CN101969062 B CN 101969062B CN 2010102657946 A CN2010102657946 A CN 2010102657946A CN 201010265794 A CN201010265794 A CN 201010265794A CN 101969062 B CN101969062 B CN 101969062B
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Abstract
The invention relates to a silicon N-type semiconductor combined device on an insulator for improving current density. The silicon N-type semiconductor combined device comprises a P-type substrate, wherein the P-type substrate is provided with a buried oxygen layer; the buried oxygen layer is provided with a P-type epitaxial layer, and the P-type epitaxial layer is divided into a region I and a region II; the region I is an insulated gate bipolar device region and comprises an N-type drift region, a P-type deep trap, a N-type buffer trap, a P-type drain region, an N-type source region and a P-type body contact region; a silicon face is correspondingly provided with a field oxide and a gate oxide, and the gate oxide is provided with a polysilicon gate; and the region II is a high-voltage triode region and comprises an N-type triode drift region, an N-type triode buffer trap, a P-type emitter region and an N-type base region. The silicon N-type semiconductor combined device is characterized in that: the N-type base region in the region II is wrapped inside the N-type buffer region, and a first drain electrode metal on the P-type drain region in the region I is communicated with a first base electrode metal on the N-type base region in the region II through a second metal. In the silicon N-type semiconductor combined device, the current density is obviously improved and other performance parameters are not changed on the basis of not increasing the area of the device.
Description
Technical field
The present invention relates to field of high voltage power semiconductor devices, is the silicon-on-insulator N type semiconductor assembling device that is applicable to the raising current density of high-voltage applications about a kind of.
Background technology
Along with people's is to the enhancing day by day of modernized life requirement; The performance of power semiconductor more and more receives publicity, but wherein the integration of power semiconductor, high withstand voltage, big electric current and with the good isolation ability of low-voltage circuit part be the maximum specification requirements of people.The factor of decision power integrated circuit handle high voltages, big current capacity size is except the kind of power semiconductor, and the structure of power semiconductor and manufacturing process also are the significant effects factors.
For a long time, the power semiconductor of people's employing is high pressure triode and High-Voltage Insulation grid field effect transistor.But these two kinds of devices have also brought many negative effects to power integrated circuit in the demand that satisfies the basic high withstand voltage and integration of people.For the high pressure triode, its deficiency has input impedance very low, and switching speed is not high.Although the input impedance of High-Voltage Insulation grid field effect transistor is very high, current driving ability is limited, and in addition, its high withstand voltage and high conduction impedance demonstrates inevitable contradiction.
Along with science and technology development, the appearance of insulated gate bipolar device has solved the most of demand of people to power semiconductor.Insulated gate bipolar device has been gathered the advantage of high-voltage three-pole pipe and isolated-gate field effect transistor (IGFET), has performances such as high input impedance, high switching speed, high withstand voltage, big current driving ability and low conduction impedance.But insulated gate bipolar device is vertical device, can integrated poor performance.The lateral insulated gate bipolar device that occurred has afterwards solved this problem.
After but the integration of power semiconductor, high demand withstand voltage, big electric current solved, its isolation became main contradiction.Mainly be in bulk silicon technological, high-tension circuit and low-voltage circuit are integrated on the chip simultaneously, and therefore the leakage current of high-tension circuit can get into the breech lock that low-voltage circuit causes low-voltage circuit through substrate than higher, finally causes chip to burn.In order to address this problem, people have proposed silicon-on-insulator process.
The appearance of silicon-on-insulator process has solved the isolating problem of power semiconductor effectively.At present lateral insulated gate bipolar device has become the main force of power semiconductor on the insulator, is widely used in direct voltage and is fields such as 600V and above converter system such as alternating current machine, frequency converter, Switching Power Supply, lighting circuit, traction transmission.
A bigger problem of lateral insulated gate bipolar device is on the insulator; To compare current density not high enough with vertical device; Therefore usually obtain high current driving ability with the area that strengthens device, thereby the chip area of labor, cost increased.This paper has introduced a kind of silicon-on-insulator N type semiconductor assembling device of novel raising current density, under the prerequisite that does not increase chip area, compares with N type lateral insulated gate bipolar device on the unidimensional common insulator, and current density increases considerably.
Summary of the invention
The present invention provides a kind of silicon-on-insulator N type semiconductor assembling device that can on the basis that does not change device area, effectively improve device current density.
The present invention adopts following technical scheme:
A kind of silicon-on-insulator N type semiconductor assembling device that improves current density; Comprise: P type substrate; On P type substrate, be provided with oxygen buried layer; It is characterized in that, be provided with P moldeed depth trap, be provided with P type body contact zone and N type source region on the P moldeed depth trap and on P type body contact zone and N type source region, be provided with the source metal that is communicated with the two in oxygen buried layer central authorities; On oxygen buried layer, also be provided with first isolated area and second isolated area; Extended and cut apart thus to the oxygen buried layer center by described first isolated area and second isolated area and form insulated gate bipolar device district and high-voltage three-pole area under control, in the insulated gate bipolar device district, be provided with insulated gate bipolar device, the source region in the described insulated gate bipolar device adopts described N type source region and described N type source region to be positioned at the insulated gate bipolar device district; In the high-voltage three-pole area under control, be provided with the high-voltage three-pole pipe; Collector region in the described high-voltage three-pole pipe adopts described P type body contact zone, and described P type body contact zone is positioned at the high-voltage three-pole area under control, and first drain metal in the described insulated gate bipolar device is connected with first base metal in the described high-voltage three-pole pipe through second metal.
Compared with prior art, the present invention has following advantage:
(1) semiconductor combinations semiconductor device of the present invention is divided into two parts; One of them part is used to make insulated gate bipolar device; Another part is used to make the high-voltage three-pole pipe; And with crossing second metal drain electrode of insulated gate bipolar device and the base stage of high-voltage three-pole pipe are linked together, can be on the basis that does not change the device gross area effectively the former drain current be further amplified as the base current that flows through the high-voltage three-pole pipe, thus the raising current density.The equivalent circuit diagram of this semiconductor combinations device is referring to accompanying drawing 4; Fig. 5 has shown the comparison of the current density of semiconductor combinations device of the present invention and insulated gate bipolar device of the same area; It is thus clear that the current density of the general insulated gate bipolar device of current density ratio of semiconductor combinations device of the present invention has improved greatly.
(2) benefit of device of the present invention is to optimize through the angle of adjusting first isolated area 101 and second isolated area 102 ratio of the chip area of insulated gate bipolar device and high-voltage three-pole pipe, with the compromise optimal effectiveness of the current density that reaches whole combined semiconductor device and other performances (like the heat radiation situation etc.).
(3) when improving current density, comparing with traditional devices of device of the present invention do not change the original chip area of device.
(4) device of the present invention when improving current density, do not influence the withstand voltage level of device, the Essential Performance Requirements of device still can satisfy.Shown in Figure 6 is the comparison diagram of the OFF state puncture voltage of semiconductor combinations device of the present invention and the general insulated gate bipolar device of equal area, and the OFF state puncture voltage of visible semiconductor combinations device of the present invention can keep consistent with general insulated gate bipolar device of the same area.
(5) making of device of the present invention does not need additional technical steps, and is compatible fully with the existing integrated circuits manufacturing process.
Description of drawings
Fig. 1 (a) is the vertical view after combined semiconductor device of the present invention is removed the passivation protection oxide layer.
Fig. 1 (b) is the profile (containing passivation layer) along the AA ' face of Fig. 1 (a).
Fig. 1 (c) is the profile (containing passivation layer) along the BB ' face of Fig. 1 (a).
Fig. 2 is a combined semiconductor device three-dimensional three-dimensional structure diagram of the present invention.(removing passivation protection oxide layer and all metals).
Fig. 3 is the 3 D stereo profile (remove passivation protection oxide layer and all metals) of semiconductor combinations device of the present invention along AA ' face.
Fig. 4 is the equivalent circuit diagram of semiconductor combinations device of the present invention.
Fig. 5 is the drain current densities comparison diagram of semiconductor combinations device of the present invention and general insulated gate bipolar device of the same area.
Fig. 6 is the OFF state puncture voltage comparison diagram of semiconductor combinations device of the present invention and general insulated gate bipolar device of the same area.
Fig. 7 (a) is P moldeed depth trap 14 process schematic representations that form in the semiconductor combinations device of the present invention.
Fig. 7 (b) is the process schematic representation of N type triode drift region 4 ' that forms N type drift region 4 and the high-voltage three-pole area under control in insulated gate bipolar device district in the semiconductor combinations device of the present invention.
Fig. 7 (c) is the process schematic representation that N type on the N drift region 4 cushions the N type triode buffering trap 5 ' on trap 5 and the N type triode drift region 4 ' in the formation semiconductor combinations device of the present invention.
Fig. 7 (d) is the process schematic representation that forms field oxide 8, gate oxide 9 and the polysilicon gate 10 in insulated gate bipolar device district in the semiconductor combinations device of the present invention.
Fig. 7 (e) is the process schematic representation that forms P type drain region 6, P type emitter region 15 and N type base 16 in the semiconductor combinations device of the present invention.
Fig. 7 (f) is after being completed into semiconductor combinations device of the present invention, along the profile of the AA ' face of Fig. 1 (a).
Embodiment
A kind of silicon-on-insulator N type semiconductor assembling device that improves current density; Comprise: P type substrate 1; On P type substrate 1, be provided with oxygen buried layer 2; It is characterized in that; Be provided with P moldeed depth trap 14 in oxygen buried layer 2 central authorities; Being provided with P type body contact zone 12 and N type source region 11 on the P moldeed depth trap 14 and on P type body contact zone 12 and N type source region 11, being provided with the source metal 72 that is communicated with the two, on oxygen buried layer 2, also be provided with first isolated area 101 and second isolated area 102, also cut apart thus to the extension of oxygen buried layer 2 centers with second isolated area 102 by described first isolated area 101 and form insulated gate bipolar device district I and high-voltage three-pole area under control II; In insulated gate bipolar device district I, be provided with insulated gate bipolar device; Source region in the described insulated gate bipolar device adopts described N type source region 11 and described N type source region 11 to be positioned at insulated gate bipolar device district I, in the II of high-voltage three-pole area under control, is provided with the high-voltage three-pole pipe, and the collector region in the described high-voltage three-pole pipe adopts described P type body contact zone 12; Described P type body contact zone 12 is positioned at high-voltage three-pole area under control II, and first drain metal 74 in the described insulated gate bipolar device is connected with first base metal 71 in the described high-voltage three-pole pipe through second metal 75.
Described first isolated area 101 and second isolated area, 102 formed angles can be adjusted; But extend and cut apart thus in two zones that form to oxygen buried layer 2 centers by described first isolated area 101 and second isolated area 102; Obtuse angle institute area surrounded is necessary for insulated gate bipolar device district I, and acute angle institute area surrounded is necessary for high-voltage three-pole area under control II.
Though the device architecture of this semiconductor combinations in the description of drawings is to adopt circular domain way of realization; But its implementation is not limited in circle; Also can be other shapes such as racetrack, rectangle, as long as with 102 insulated gate bipolar device is separated with the high-voltage three-pole pipe and the drain electrode of insulated gate bipolar device is connected with metal with the base stage of high-voltage three-pole pipe with two isolation channels 101.
Described silicon-on-insulator N type semiconductor assembling device P type emitter region 15 is 1 μ m～2 μ m with the spacing of N type base 16;
The present invention adopts following method to prepare:
The first step; Get silicon-on-insulator disk with P type epitaxial loayer; Area ratio according to insulated gate bipolar device that is designed and high-voltage three-pole pipe; The needed isolation channel 101 of etching and 102, thus insulated gate bipolar device district I and high-voltage three-pole area under control II formed, and P type epitaxial loayer is dividing in interior P type epitaxial loayer 3 of insulated gate bipolar device district I and the 2nd P type epitaxial loayer 3 ' in the high-voltage three-pole area under control.
In second step, inject through high-energy boron ion, and high annealing forms P moldeed depth trap 14.
The 3rd step, inject with high-octane phosphonium ion, form N type drift region 4 in the insulated gate bipolar device district behind the high annealing and form N type triode drift region 4 ' in the high-voltage three-pole area under control;
The 4th step, inject with high-octane phosphonium ion, on N drift region 4, form N type buffering trap 5 behind the high annealing and 4 ' go up and form N type triode buffering trap 5 ' in N type triode drift region.
The 5th step, deposit and etch silicon nitride, the field oxide of at high temperature growing.Regrowth gate oxide, and deposit polysilicon etch polysilicon gate.
In the 6th step,, make each electrode contact zone through the boron ion and the phosphonium ion injection of high dose.
The 7th step, deposit silicon dioxide, depositing metal trace layer and etch away excess metal behind the etching electrode contact hole.
In the 8th step, carry out the making of passivation layer.
Claims (5)
1. silicon-on-insulator N type semiconductor assembling device that improves current density; Comprise: P type substrate (1); On P type substrate (1), be provided with oxygen buried layer (2); It is characterized in that; Central authorities are provided with P moldeed depth trap (14) at oxygen buried layer (2); Being provided with P type body contact zone (12) and N type source region (11) on the P moldeed depth trap (14) and on P type body contact zone (12) and N type source region (11), being provided with the source metal (72) that is communicated with the two, on oxygen buried layer (2), also be provided with first isolated area (101) and second isolated area (102), also cut apart thus to the extension of oxygen buried layer (2) center with second isolated area (102) by described first isolated area (101) and form insulated gate bipolar device district (I) and high-voltage three-pole area under control (II); In insulated gate bipolar device district (I), be provided with insulated gate bipolar device; Source region in the described insulated gate bipolar device adopts described N type source region (11) and described N type source region (11) to be positioned at insulated gate bipolar device district (I), in high-voltage three-pole area under control (II), is provided with the high-voltage three-pole pipe, and the collector region in the described high-voltage three-pole pipe adopts described P type body contact zone (12); Described P type body contact zone (12) is positioned at high-voltage three-pole area under control (II), and first drain metal (74) in the described insulated gate bipolar device is connected with first base metal (71) in the described high-voltage three-pole pipe through second metal (75).
2. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 1; It is characterized in that; Said insulated gate bipolar device comprises: be located at the P type epitaxial loayer (3) on the oxygen buried layer (2); Be provided with N type drift region (4) in P type epitaxial loayer (a 3) upper right side; Be provided with N type buffering trap (5) in the upper right side of N type drift region (4); Be provided with P type drain region (6) and described first drain metal (74) in the upper right side of N type buffering trap (5) and be located at top, P type drain region (6), the silicon face in N type drift region (4) is provided with field oxide (8) and field oxide (8) joins with P type drain region (6), and the silicon face between N type source region (11) and field oxide (8) is provided with gate oxide (9); Gate oxide (9) is provided with the upper surface that polysilicon gate (10) and polysilicon gate (10) extend to field oxide (8), on polysilicon gate (10), is provided with gate metal (73).
3. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 1 and 2; It is characterized in that; Described high-voltage three-pole pipe comprises: be located at the 2nd P type epitaxial loayer (3 ') on the oxygen buried layer (2); Be provided with N type triode drift region (4 ') on the upper left side of the 2nd P type epitaxial loayer (3 '), be provided with N type triode buffering trap (5 ') on the upper left side of N type triode drift region (4 '), on N type triode buffering trap (5 '), be provided with P type emitter region (15) and N type base (16); On P type emitter region (15), be provided with emitter metal (70), on N type base (16), be provided with described first base metal (71).
4. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 3 is characterized in that, P type emitter region (15) is 1 μ m～2 μ m with the spacing of N type base (16).
5. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 3 is characterized in that, described insulated gate bipolar device district (I) and high-voltage three-pole area under control (II) upper surface non-metallic regions are provided with passivation protection oxide layer (13).
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| CN102437181A (en) * | 2011-12-08 | 2012-05-02 | 东南大学 | N type silicon on insulator transverse insulated gate bipolar device |
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| CN101594131A (en) * | 2008-05-30 | 2009-12-02 | 三菱电机株式会社 | Semiconductor device |
| CN201853707U (en) * | 2010-08-27 | 2011-06-01 | 东南大学 | Silicon-on-insulator N-type semiconductor combined device capable of increasing current density |
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| CN101594131A (en) * | 2008-05-30 | 2009-12-02 | 三菱电机株式会社 | Semiconductor device |
| CN201853707U (en) * | 2010-08-27 | 2011-06-01 | 东南大学 | Silicon-on-insulator N-type semiconductor combined device capable of increasing current density |
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