CN101969062B - Silicon N-type semiconductor combined device on insulator for improving current density - Google Patents

Abstract

A silicon-on-insulator N-type semiconductor combination device with improved current density, comprising: a P-type substrate, a buried oxide layer is arranged on the P-type substrate, a P-type epitaxial layer is arranged on the buried oxide layer, and the P-type epitaxial layer is divided into regions I and II, where region I is an insulated gate bipolar device region, including: N-type drift region, P-type deep well, N-type buffer well, P-type drain region, N-type source region and P-type body contact region , a field oxide layer and a gate oxide layer are correspondingly provided on the silicon surface, and a polysilicon gate is provided on the gate oxide layer; where II area is a high-voltage triode area, including: N-type triode drift area, N-type triode buffer well, P-type emitter region and an N-type base region, which is characterized in that the N-type base region in the II region is wrapped inside the N-type buffer zone, and the first drain metal on the P-type drain region in the I region and the N-type base region in the II region The first base metal communicates through the second metal. The invention significantly improves the current density of the device without increasing the area of the device and does not change other performance parameters of the device.

Description

A silicon-on-insulator N-type semiconductor composite device with improved current density

technical field

The invention relates to the field of high-voltage power semiconductor devices, and relates to a silicon-on-insulator N-type semiconductor combination device suitable for high-voltage applications with improved current density.

Background technique

With the increasing demand for modern life, the performance of power semiconductor devices has attracted more and more attention. Among them, the integration, high withstand voltage, high current and good isolation ability of power semiconductor devices are the most important factors for people. technical requirements. The factors that determine the ability of power integrated circuits to handle high voltage and high current are not only the types of power semiconductor devices, but also the structure and manufacturing process of power semiconductor devices.

For a long time, the power semiconductor devices used by people are high-voltage transistors and high-voltage insulated gate field effect transistors. While these two devices meet people's basic needs of high withstand voltage and integrability, they also bring many negative effects to power integrated circuits. For high-voltage triode tubes, its disadvantages are that the input impedance is very low and the switching speed is not high. Although the input impedance of the high-voltage IGSFET is very high, the current driving capability is limited. In addition, its high withstand voltage and high on-resistance present an inevitable contradiction.

With the development of science and technology, the emergence of insulated gate bipolar devices has solved most of people's needs for power semiconductor devices. Insulated gate bipolar devices combine the advantages of high-voltage triodes and insulated gate field effect transistors, with high input impedance, high switching speed, high withstand voltage, large current drive capability and low on-resistance. However, the insulated gate bipolar device is a vertical device and has poor integration performance. The lateral insulated gate bipolar device that appeared later solved this problem.

After the integration, high withstand voltage, and high current requirements of power semiconductor devices are resolved, its isolation becomes the main contradiction. Mainly in the bulk silicon process, the high-voltage circuit and the low-voltage circuit are integrated on one chip at the same time, the leakage current of the high-voltage circuit will be relatively high, so it will enter the low-voltage circuit through the substrate to cause the latch of the low-voltage circuit, and eventually cause the chip to burn. In order to solve this problem, silicon-on-insulator technology has been proposed.

The emergence of silicon-on-insulator technology has effectively solved the isolation problem of power semiconductor devices. At present, lateral insulated gate bipolar devices on insulators have become the main force of power semiconductor devices, and are widely used in conversion systems with a DC voltage of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, traction drives and other fields.

One of the bigger problems surrounding LIGOBI devices is that the current density is not high enough compared to vertical devices, so high current drive capability is often obtained by enlarging the device area, thus consuming a lot of chips area, which increases the cost. This paper introduces a new silicon-on-insulator N-type semiconductor combined device with improved current density. Under the premise of not increasing the layout area, compared with the common N-type lateral insulated gate bipolar device of the same size, the current density increased badly.

Contents of the invention

The invention provides a silicon-on-insulator N-type semiconductor combined device capable of effectively increasing the current density of the device without changing the device area.

The present invention adopts following technical scheme:

A silicon-on-insulator N-type semiconductor combination device for increasing current density, comprising: a P-type substrate, on which a buried oxide layer is arranged, and is characterized in that a P-type deep well is arranged in the center of the buried oxide layer, A P-type body contact region and an N-type source region are arranged on the P-type deep well, and a source metal connecting them is arranged on the P-type body contact region and the N-type source region, and a second layer is arranged on the buried oxide layer. An isolation region and a second isolation region extend from the first isolation region and the second isolation region to the center of the buried oxide layer and are thus divided to form an insulated gate bipolar device region and a high-voltage triode region. An insulated gate bipolar device is provided in the insulated gate bipolar device region, and the source region in the insulated gate bipolar device adopts the N-type source region and the N-type source region is located in the insulated gate bipolar device region Inside, a high-voltage triode is provided in the high-voltage triode area, and the collector area in the high-voltage triode adopts the P-type body contact area, and the P-type body contact area is located in the high-voltage triode area, and the insulation The first drain metal in the gate bipolar device is connected to the first base metal in the high voltage triode through the second metal.

Compared with prior art, the present invention has following advantage:

(1) The semiconductor composite semiconductor device of the present invention is divided into two parts, one of which is used to make an insulated gate bipolar device, and the other part is used to make a high-voltage triode, and the insulated gate bipolar device is made of the second metal The drain and the base of the high-voltage transistor are connected together, and the drain current of the former can be further amplified as the base current flowing through the high-voltage transistor without changing the total area of the device, thereby increasing the current density. The equivalent circuit diagram of this semiconductor composite device is referring to accompanying drawing 4, and Fig. 5 shows the comparison of the current density of the semiconductor composite device of the present invention and the insulated gate bipolar device of the same area, as can be seen, the current density of the semiconductor composite device of the present invention Compared with the general insulated gate bipolar device, the current density is greatly improved.

(2) The advantage of the device of the present invention is that the ratio of the layout area of the insulated gate bipolar device and the high-voltage triode can be optimized by adjusting the angle between the first isolation region 101 and the second isolation region 102, so as to achieve the ratio of the entire combined semiconductor device. The optimal effect of the compromise between current density and other properties (such as heat dissipation, etc.).

(3) Compared with traditional devices, the device of the present invention does not change the original layout area of the device while increasing the current density.

(4) While the current density of the device of the present invention is increased, the withstand voltage level of the device is not affected, and the basic performance requirements of the device can still be met. Fig. 6 shows the comparison diagram of the off-state breakdown voltage of the semiconductor composite device of the present invention and the general insulated gate bipolar device of the same area, as seen the off-state breakdown voltage of the semiconductor composite device of the present invention can be maintained with the same area Generally insulated gate bipolar devices are the same.

(5) The manufacture of the device of the present invention does not require additional process steps, and is fully compatible with the existing integrated circuit manufacturing process.

Description of drawings

Fig. 1(a) is a top view of the combined semiconductor device of the present invention after removal of the passivation protective oxide layer.

Fig. 1(b) is a cross-sectional view along the AA' plane of Fig. 1(a) (including a passivation layer).

Fig. 1(c) is a sectional view along the BB' plane of Fig. 1(a) (including a passivation layer).

Fig. 2 is a three-dimensional structure diagram of the combined semiconductor device of the present invention. (removes passivating protective oxide and all metal).

Fig. 3 is a three-dimensional cross-sectional view of the semiconductor composite device of the present invention along the plane AA' (removing the passivation protective oxide layer and all metals).

Fig. 4 is an equivalent circuit diagram of the semiconductor composite device of the present invention.

Fig. 5 is a comparison diagram of the drain current density of the semiconductor composite device of the present invention and a general insulated gate bipolar device of the same area.

Fig. 6 is a comparison diagram of the off-state breakdown voltage of the semiconductor composite device of the present invention and a general insulated gate bipolar device with the same area.

Fig. 7(a) is a schematic diagram of the process of forming the P-type deep well 14 in the semiconductor composite device of the present invention.

Fig. 7(b) is a schematic diagram of the process of forming the N-type drift region 4 of the insulated gate bipolar device region and the N-type triode drift region 4' of the high-voltage triode region in the semiconductor composite device of the present invention.

Fig. 7(c) is a schematic diagram of the process of forming the N-type buffer well 5 on the N-drift region 4 and the N-type transistor buffer well 5' on the N-type transistor drift region 4' in the semiconductor composite device of the present invention.

FIG. 7( d ) is a schematic diagram of the process of forming the field oxide layer 8 , the gate oxide layer 9 and the polysilicon gate 10 in the insulated gate bipolar device region of the semiconductor composite device of the present invention.

FIG. 7( e ) is a schematic diagram of the process of forming the P-type drain region 6 , the P-type emitter region 15 and the N-type base region 16 in the semiconductor composite device of the present invention.

Fig. 7(f) is a cross-sectional view along the AA' plane of Fig. 1(a) after the semiconductor composite device of the present invention is completely formed.

Detailed ways

A silicon-on-insulator N-type semiconductor composite device with improved current density, comprising: a P-type substrate 1, on which a buried oxide layer 2 is arranged, and is characterized in that a P Type deep well 14, be provided with P type body contact region 12 and N type source region 11 on P type deep well 14 and be provided with the source metal that connects both on P type body contact region 12 and N type source region 11 72. A first isolation region 101 and a second isolation region 102 are also provided on the buried oxide layer 2, which are formed by extending from the first isolation region 101 and the second isolation region 102 to the center of the buried oxide layer 2 The insulated gate bipolar device region I and the high-voltage triode region II are provided with an insulated gate bipolar device in the insulated gate bipolar device region I, and the source region in the insulated gate bipolar device adopts the described The N-type source region 11 and the N-type source region 11 are located in the insulated gate bipolar device region I, and a high-voltage transistor is provided in the high-voltage transistor region II, and the collector region in the high-voltage transistor adopts the described The P-type body contact region 12, the P-type body contact region 12 is located in the high voltage triode region II, the first drain metal 74 in the insulated gate bipolar device communicates with the high voltage through the second metal 75 The first base metal 71 in the triode is connected.

The angle formed by the first isolation region 101 and the second isolation region 102 can be adjusted, but the first isolation region 101 and the second isolation region 102 extend to the center of the buried oxide layer 2 and are formed by dividing Among the two regions, the region surrounded by the obtuse angle must be the insulated gate bipolar device region I, and the region surrounded by the acute angle must be the high voltage triode region II.

Although the structure of the semiconductor composite device in the description of the accompanying drawings adopts a circular layout, its implementation is not limited to a circle, and it can also be in other shapes such as racetracks, rectangles, etc., as long as two isolation grooves 101 and 102 are used to separate The insulated gate bipolar device and the high voltage triode are separated and the drain of the insulated gate bipolar device is connected to the base of the high voltage triode with metal.

The distance between the P-type emitter region 15 and the N-type base region 16 of the silicon-on-insulator N-type semiconductor composite device is 1 μm to 2 μm;

The present invention adopts following method to prepare:

The first step is to take a silicon-on-insulator wafer with a P-type epitaxial layer, and etch the required isolation grooves 101 and 102 according to the designed area ratio of the IGBD device and the high-voltage triode, thereby forming an IGBT Pole type device region I and high-voltage triode region II, and the P-type epitaxial layer is divided into a first P-type epitaxial layer 3 in the insulated gate bipolar device region I and a second P-type epitaxial layer in the high-voltage triode region 3'.

In the second step, the P-type deep well 14 is formed by high-energy boron ion implantation and high-temperature annealing.

The third step is to implant high-energy phosphorus ions, and form an N-type drift region 4 in the insulated gate bipolar device region after high-temperature annealing, and form an N-type triode drift region 4' in the high-voltage triode region;

The fourth step is to implant high-energy phosphorus ions, form an N-type buffer well 5 on the N-type drift region 4 after high-temperature annealing, and form an N-type triode buffer well 5' on the N-type transistor drift region 4'.

In the fifth step, silicon nitride is deposited and etched, and a field oxide layer is grown at high temperature. A gate oxide layer is grown again, polysilicon is deposited, and the polysilicon gate is etched.

In the sixth step, each electrode contact area is made by implanting high-dose boron ions and phosphorus ions.

The seventh step is to deposit silicon dioxide, etch the electrode contact hole, deposit the metal wiring layer and etch away the excess metal.

The eighth step is to make a passivation layer.

Claims (5)

1. silicon-on-insulator N type semiconductor assembling device that improves current density; Comprise: P type substrate (1); On P type substrate (1), be provided with oxygen buried layer (2); It is characterized in that; Central authorities are provided with P moldeed depth trap (14) at oxygen buried layer (2); Being provided with P type body contact zone (12) and N type source region (11) on the P moldeed depth trap (14) and on P type body contact zone (12) and N type source region (11), being provided with the source metal (72) that is communicated with the two, on oxygen buried layer (2), also be provided with first isolated area (101) and second isolated area (102), also cut apart thus to the extension of oxygen buried layer (2) center with second isolated area (102) by described first isolated area (101) and form insulated gate bipolar device district (I) and high-voltage three-pole area under control (II); In insulated gate bipolar device district (I), be provided with insulated gate bipolar device; Source region in the described insulated gate bipolar device adopts described N type source region (11) and described N type source region (11) to be positioned at insulated gate bipolar device district (I), in high-voltage three-pole area under control (II), is provided with the high-voltage three-pole pipe, and the collector region in the described high-voltage three-pole pipe adopts described P type body contact zone (12); Described P type body contact zone (12) is positioned at high-voltage three-pole area under control (II), and first drain metal (74) in the described insulated gate bipolar device is connected with first base metal (71) in the described high-voltage three-pole pipe through second metal (75).

2. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 1; It is characterized in that; Said insulated gate bipolar device comprises: be located at the P type epitaxial loayer (3) on the oxygen buried layer (2); Be provided with N type drift region (4) in P type epitaxial loayer (a 3) upper right side; Be provided with N type buffering trap (5) in the upper right side of N type drift region (4); Be provided with P type drain region (6) and described first drain metal (74) in the upper right side of N type buffering trap (5) and be located at top, P type drain region (6), the silicon face in N type drift region (4) is provided with field oxide (8) and field oxide (8) joins with P type drain region (6), and the silicon face between N type source region (11) and field oxide (8) is provided with gate oxide (9); Gate oxide (9) is provided with the upper surface that polysilicon gate (10) and polysilicon gate (10) extend to field oxide (8), on polysilicon gate (10), is provided with gate metal (73).

3. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 1 and 2; It is characterized in that; Described high-voltage three-pole pipe comprises: be located at the 2nd P type epitaxial loayer (3 ') on the oxygen buried layer (2); Be provided with N type triode drift region (4 ') on the upper left side of the 2nd P type epitaxial loayer (3 '), be provided with N type triode buffering trap (5 ') on the upper left side of N type triode drift region (4 '), on N type triode buffering trap (5 '), be provided with P type emitter region (15) and N type base (16); On P type emitter region (15), be provided with emitter metal (70), on N type base (16), be provided with described first base metal (71).

4. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 3 is characterized in that, P type emitter region (15) is 1 μ m～2 μ m with the spacing of N type base (16).

5. the silicon-on-insulator N type semiconductor assembling device of raising current density according to claim 3 is characterized in that, described insulated gate bipolar device district (I) and high-voltage three-pole area under control (II) upper surface non-metallic regions are provided with passivation protection oxide layer (13).

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