CN103094350A - High voltage lateral double diffused MOSFET (LDMOS) device - Google Patents
High voltage lateral double diffused MOSFET (LDMOS) device Download PDFInfo
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Abstract
The invention provides a high voltage lateral double diffused MOSFET (LDMOS) device. A semiconductor heavily doped region which is connected with or coincides with reduced-field layers and shares the same conduction type with the reduced-field layers is introduced at the position close to a source region of each reduced-field layer, and thus the device can generate a high electric field peak value in the middle part of a drift region, a high electric field peak value of a main junction is lowered, the surface electric field distribution of the drift region is optimized, and reverse breakdown voltages of the device can be improved. The device can further improve the doping density of the reduced-field layers of the LDMOS device of a conventional reduced-field layer structure, so that the optimal drift region density of the device is improved, and namely forward direction turn-on resistance of the device can be reduced. The semiconductor heavily doped region which is introduced by the high voltage LDMOS device and a semiconductor contact region of the same conduction type are completed at the same time in technique and preparation, a mask plate and additional processing steps do not need to be added, and therefore the high voltage LDMOS device is simple in technique and low in cost.
Description
Technical field
The invention belongs to the semiconductor power device technology field, particularly a kind of high-voltage LDMOS device.
Background technology
High-voltage LDMOS (Laterally Double-diffused MOSFET, the horizontal dual pervasion field effect pipe) device is due to its good processing compatibility, be easy to be distributed in surperficial source electrode, grid and drain electrode and low voltage logic circuit monolithic by interconnector integrated, be used in high-voltage power integrated circuit widely.but the contradiction between puncture voltage and conducting resistance is one of topmost contradiction of design power LDMOS device, in order to overcome this contradictory relation, the people such as J.A.APPLES have proposed RESURF (Reduced SURface Field, reduce surface field) technology, Fig. 1 has provided a typical conventional SOI RESURF LDMOS device architecture schematic diagram, it is by Semiconductor substrate 1, oxygen buried layer 4, drift semiconductor district 2, semiconductor drain region 10, semiconductor body 6, wherein have semiconductor source region 11 and semiconductor bulk contact zone 12 in semiconductor body 6, and drain metal 15, source metal 14, gate oxide 8, grid 9, field oxide 7 forms.This technology just has been widely used in since proposing among the high tension apparatus design, but this technology can only reduce conducting resistance to a certain extent, still can not meet the power integrated circuit of high speed development to the specification requirement of high-voltage LDMOS device.
In order to improve the on state characteristic of RESURF structure, document: Zingg R P, Weijland I, Zwol H V, et al. 850V DMOS-switch in silicon-on-insulator with specific Ron of 13 Ω mm2. Proceeding of International SOI Conference, 2000, pp.62-63 has proposed a kind of new high pressure low on-resistance designing technique---D-RESURF technology.Fig. 2 has provided the existing high-voltage LDMOS device structural representation that falls the field layer that has.its first conductive type semiconductor falls layer 3 and is arranged in the second conductive type semiconductor drift region 2, the conducting resistance that a layer 3 can reduce the LDMOS device to a certain extent falls in this first conductive type semiconductor, but by its surface electric field distribution as can be known, an electric field low ebb will appear in its PN junction place in positively biased, thereby affect the device surface Electric Field Distribution, and according to the RESURF principle, the RESURF requirement on devices has strict electric charge to control, have the LDMOS device that falls layer fall a layer to its electric charge control require stricter, this invisible complexity that increases the designs preparation.
in order to improve breakdown characteristics with the high-voltage LDMOS device that falls layer and puncture voltage thereof to falling a sensitiveness of layer doping content, document: Souza M D, Narayanan E M S. Double RESURF technology for HVIC. Electron Lett, 1996, 32 (12): 1092, document: Hardikar S, de Souza M M, Xu Y Z, et al. A novel double RESURF LDMOS for HVIC ' s. J Microelectron, 2004, 35 (3): 305, propose to have linear varying doping (LVD) surface and fallen a layer LDMOS device architecture, as shown in Figure 3, it is by Semiconductor substrate 1, drift semiconductor district 2, semiconductor drain region 10, semiconductor body 6, wherein have semiconductor source region 11 and semiconductor bulk contact zone 12 in semiconductor body 6, and drain metal 15, source metal 14, gate oxide 8, grid 9, field oxide 7 and semiconductor fall a layer 3 and form.Described the first conductive type semiconductor falls a doping content of layer 3 from channel region one side direction drain region one side line reduction.By optimizing slope and the initial concentration of linear distributed function, can greatly optimize the surface electric field distribution of drift region, thereby increase substantially the puncture voltage of device.
But, in order to obtain a layer concentration of falling of linear change, must stria mask lithography of increase and high temperature long term annealing.The complexity that this has increased technique has improved manufacturing cost.document: Zhu Kuiying, Deng. the optimal design of Double RESURF nLDMOS power device, solid electronics research and progress, 2010, vol.30, No.2, pp.256-271, propose to have multi-region and fallen a layer LDMOS device architecture, as shown in Figure 4, have a plurality of the first conductive type semiconductors and fall a layer 3 in the second conductive type semiconductor drift region 2, its comparable single plot structure obtains higher puncture voltage, and after falling a layer employing multi-region varying doping, the puncture voltage of device diminishes with the sensitiveness of falling field layer dopant dose, during the multi-region varying doping, the puncture voltage of device still can remain unchanged in wider falling under a layer implantation dosage.The Qu Yueduo that hence one can see that divides, near desirable puncture voltage, meanwhile, and reticle, the technique manufacturing also increases thereupon.
Summary of the invention
The present invention is directed to the technical problem that exists in the above-mentioned background technology, propose a kind of high-voltage LDMOS device.
The present invention adopts following technical scheme for solving the problems of the technologies described above:
A kind of high-voltage LDMOS device, the high-voltage LDMOS device superficial layer that comprises the first conductive type semiconductor substrate, is positioned at the second conductive type semiconductor drift region of the first conductive type semiconductor substrate top and is positioned at the second top, conductive type semiconductor drift region; Wherein, has the second conductive type semiconductor drain region in the second top, conductive type semiconductor drift region one side, have the first conductive type semiconductor tagma at the second top, conductive type semiconductor drift region opposite side, have the second conductive type semiconductor source region and the first conductive type semiconductor body contact zone in the first conductive type semiconductor tagma;
described high-voltage LDMOS device superficial layer is by field oxide, gate oxide, source metal, drain metal forms, wherein, drain metal contacts with the second conductive type semiconductor drain region, source metal contacts with the first conductive type semiconductor body contact zone with the second conductive type semiconductor source region respectively, the first conductive type semiconductor tagma contacts with gate oxide, the gate oxide surface is grid, the second conductive type semiconductor drift region respectively with field oxide, the gate oxide contact, the second inside, conductive type semiconductor drift region also has n and falls a layer with contacted the first conductive type semiconductor of field oxide, falling layer at each first conductive type semiconductor has near the second conductive type semiconductor source region one side and falls first a conductive type semiconductor heavily doped region that layer is connected or overlaps, n is the natural number greater than 0.
Described the second conductive type semiconductor drift region is directly to form in the upper surface extension of Semiconductor substrate, perhaps first makes oxygen buried layer on Semiconductor substrate, and then extension forms on oxygen buried layer.
It is evenly to distribute or horizontal linear dopant profiles that a CONCENTRATION DISTRIBUTION of layer falls in described the first conductive type semiconductor; When CONCENTRATION DISTRIBUTION was horizontal linear dopant profiles, doping content reduced gradually from the second conductive type semiconductor source region one side to the second conductive type semiconductor drain region one side.
The material of described the second conductive type semiconductor drift region is silicon, carborundum, GaAs or germanium silicon.
Beneficial effect: the present invention proposes a kind of high-voltage LDMOS device, described device by fall at each layer near a source region introduce one with an identical conduction type semiconductor heavily doped region that layer is connected or overlaps falls; So just can produce a high peak electric field at the middle part, drift region, reduce the high peak electric field in main knot place, optimize the surface electric field distribution of drift region, thereby can improve the reverse breakdown voltage of device; Can also improve routine and fall the LDMOS device of layer structure and fall a doping content of layer, thereby improve the optimum drift region concentration of device, forward conduction resistance that namely can the lowering device part.Simultaneously, the semiconductor heavily doped region that the present invention introduces is completed in the technique preparation simultaneously with identical conduction type semiconductor body contact zone, need not the processing step that increases mask plate and add, and technique is simple, and is with low cost.
Description of drawings
Fig. 1 is conventional RESURF LDMOS structural representation.
Fig. 2 is that a LDMOS structural representation of layer falls in conventional having.
Fig. 3 is that a LDMOS structural representation of layer falls in linear doping.
Fig. 4 has multi-region to fall a LDMOS structural representation of layer.
Fig. 5 is the embodiment 1 of a kind of high-voltage LDMOS device of the present invention.
Fig. 6 is the embodiment 2 of a kind of high-voltage LDMOS device of the present invention.
Fig. 7 is the embodiment 3 of a kind of high-voltage LDMOS device of the present invention.
Fig. 8 is the embodiment 4 of a kind of high-voltage LDMOS device of the present invention.
Fig. 9 is that the routine of same structure parameter has the LDMOS device architecture that falls layer and the surface electric field distribution schematic diagram of LDMOS device architecture provided by the invention.
Figure 10 is that the LDMOS device architecture of field layer falls in conventional having and the I/V characteristic of LDMOS device architecture provided by the invention compares.
In description of reference numerals: Fig. 1 to Fig. 8,1 is the first conductive type semiconductor substrate, 2 is second conductive type semiconductor drift regions, 3 is that a layer falls in the first conductive type semiconductor, the 4th, oxygen buried layer, 6 is first conductive type semiconductor tagmas, the 7th, field oxide, the 8th, gate oxide, the 9th, grid, 10 is second conductive type semiconductor drain regions, 11 is second conductive type semiconductor source regions, and 12 is first conductive type semiconductor body contact zones, the 13rd, and first kind conductive type semiconductor heavily doped region, the 14th, source metal, the 15th, drain metal.
Embodiment
The illustrative embodiments of a kind of high-voltage LDMOS device of the present invention is described below with reference to accompanying drawings in more detail.Yet, can implement the present invention and should not be understood as to be confined to execution mode described in this paper with different forms.On the contrary, provide these execution modes be for present disclosure with thorough and complete, and will pass on scope of the present invention to those skilled in the art all sidedly.In whole disclosure, in various figure of the present invention and execution mode, identical Reference numeral is censured identical part.Accompanying drawing and in some cases, may enlarge ratio in order to be clearly shown that the feature of execution mode not necessarily in proportion.The first conduction type of the present invention is P type and the second conduction type is N type or the first conduction type is N type and the second conduction type is the P type.
a kind of high-voltage LDMOS device of the present invention, as shown in Figure 5, a kind of embodiment of high-voltage LDMOS device structure provided by the invention, it comprises the first conductive type semiconductor substrate 1, be positioned at the second conductive type semiconductor drift region 2 on the first conductive type semiconductor substrate 1 surface, be positioned at the second conductive type semiconductor drain region 10 of the second conductive type semiconductor drift region 2 top one sides, be positioned at the first conductive type semiconductor tagma 6 of the second conductive type semiconductor drift region 2 top opposite sides, have the second conductive type semiconductor source region 11 and the first conductive type semiconductor body contact zone 12 in the first conductive type semiconductor tagma 6, what device surface contacted with the second conductive type semiconductor drain region 10 is drain metal 15, what contact with the first conductive type semiconductor body contact zone 12 with the second conductive type semiconductor source region 11 is source metal 14, the first conductive type semiconductor tagma 6 and 2 surfaces, part the second conductive type semiconductor drift region are that gate oxide 8, gate oxide 8 surfaces are grids 9, and all the other 2 surfaces, drift semiconductor district are field oxides 7.2 inside, described the second conductive type semiconductor drift region also have the first conductive type semiconductor and fall a layer 3.A layer 3 falls in described the first conductive type semiconductor to have near source region one side and falls layer 3 first a conductive type semiconductor heavily doped region 13 that is connected.
Fig. 6 is the embodiment 2 of high-voltage LDMOS device structure provided by the invention, has first kind conductive type semiconductor heavily doped region 13, and itself and semiconductor fall a layer 3 and overlap.
Fig. 7 is the embodiment 3 of high-voltage LDMOS device structure provided by the invention, have the first conductive type semiconductor and fall layer 3 first conductive type semiconductor by the piecewise linearity varying doping and form, doping content reduces gradually from the second conductive type semiconductor source region 11 1 side to the second conductive type semiconductor drain region 10 1 sides.
Fig. 8 is the embodiment 4 of high-voltage LDMOS device structure provided by the invention, have multi-region the first conductive type semiconductor and fall layer 3, each fall a layer 3 near source region one sides all introduce one with layer 3 first a conductive type semiconductor heavily doped region 13 that is connected falls.
Fig. 9 is that the routine of same structure parameter has the LDMOS device architecture that falls layer and the surface electric field distribution schematic diagram of LDMOS device architecture provided by the invention.
Figure 10 is that the LDMOS device architecture of field layer falls in conventional having and the I/V characteristic of LDMOS device architecture provided by the invention compares.
In a kind of high-voltage LDMOS device provided by the invention, first kind conductive type semiconductor heavily doped region 13 and the first conductive type semiconductor body contact zone 12 are completed in the technique preparation simultaneously, need not to increase mask plate and additional processing step, technique is simple, workable, reduced manufacturing cost.
Operation principle of the present invention:
The below describes working mechanism of the present invention take SOI LDMOS device as example.
Fig. 9 has compared the surface electric field distribution that a layer LDMOS device architecture and LDMOS device architecture provided by the invention fall in having of routine.Two kinds of structures have identical physical dimension, and the drift region CONCENTRATION DISTRIBUTION is optimized.Wherein dotted line is that routine has and falls a layer LDMOS device surface Electric Field Distribution curve, and solid line is LDMOS device surface Electric Field Distribution curve provided by the invention.As seen from the figure, have for routine and fall a LDMOS device architecture of layer, its both sides in the drift region produce two high peak electric field, and the place produces lower electric field valley at the positively biased PN junction, has a strong impact on the surface electric field distribution of drift region, reduces puncture voltage.And for high-voltage LDMOS device structure provided by the invention, its middle part in the drift region produces a high peak electric field, has optimized the surface electric field distribution of drift region, thereby can improve the puncture voltage of device.
Figure 10 compared conventional have a LDMOS device architecture of layer and the I/V characteristic curve of LDMOS device architecture provided by the invention fall.Wherein dotted line is that routine has and falls layer LDMOS device drain-source current and a drain-source voltage relation curve, and solid line is LDMOS device drain-source current provided by the invention and drain-source voltage relation curve.As seen from the figure, at V
DSDuring=10V, it is 12 μ A/ μ m that routine has an electric current that falls field layer LDMOS device; LDMOS device current provided by the invention is 20 μ A/ μ m, and current capacity has improved 40% than conventional structure.
In sum, the present invention by fall layer near source region one side introduce one with a first kind conductive type semiconductor heavily doped region 13 that layer is connected falls.It can produce a high peak electric field at the middle part, drift region on the one hand, has reduced the high peak electric field at main knot place, has optimized the surface electric field distribution of drift region, thereby can improve the reverse breakdown voltage of device; On the other hand, according to the RESURF principle, it can improve routine and falls the LDMOS device of layer structure and fall a doping content of layer, thereby has improved the optimum drift region concentration of device, forward conduction resistance that namely can the lowering device part.Simultaneously, the first kind conductive type semiconductor heavily doped region 13 that the present invention introduces is completed in the technique preparation simultaneously with the first conductive type semiconductor body contact zone 12, need not the processing step that increases mask plate and add, and technique is simple, and is with low cost.
Claims (4)
1. high-voltage LDMOS device comprises the first conductive type semiconductor substrate (1), is positioned at the second conductive type semiconductor drift region (2) of the first conductive type semiconductor substrate (1) top and the high-voltage LDMOS device superficial layer that is positioned at the second top, conductive type semiconductor drift region (2); Wherein, has the second conductive type semiconductor drain region (10) in the second top, conductive type semiconductor drift region (2) one side, have the first conductive type semiconductor tagma (6) at the second top, conductive type semiconductor drift region (2) opposite side, have the second conductive type semiconductor source region (11) and the first conductive type semiconductor body contact zone (12) in the first conductive type semiconductor tagma (6);
described high-voltage LDMOS device superficial layer is by field oxide (7), gate oxide (8), source metal (14), drain metal (15) forms, wherein, drain metal (15) contacts with the second conductive type semiconductor drain region (10), source metal (14) contacts with the first conductive type semiconductor body contact zone (12) with the second conductive type semiconductor source region (11) respectively, the first conductive type semiconductor tagma (6) contacts with gate oxide (8), gate oxide (8) surface is grid (9), the second conductive type semiconductor drift region (2) respectively with field oxide (7), gate oxide (8) contact, it is characterized in that, the second inside, conductive type semiconductor drift region (2) also has n and falls a layer (3) with contacted the first conductive type semiconductor of field oxide (7), falling layer (3) at each first conductive type semiconductor has near the second conductive type semiconductor source region (11) one sides and falls first a conductive type semiconductor heavily doped region (13) that layer (3) is connected or overlaps, n is the natural number greater than 0.
2. a kind of high-voltage LDMOS device according to claim 1, it is characterized in that, described the second conductive type semiconductor drift region (2) is directly to form in the upper surface extension of Semiconductor substrate (1), perhaps first make oxygen buried layer (4) on Semiconductor substrate (1), then extension forms on oxygen buried layer (4).
3. a kind of high-voltage LDMOS device according to claim 1 and 2, is characterized in that, it is evenly to distribute or horizontal linear dopant profiles that a CONCENTRATION DISTRIBUTION of layer (3) falls in described the first conductive type semiconductor; When CONCENTRATION DISTRIBUTION was horizontal linear dopant profiles, doping content reduced gradually from the second conductive type semiconductor source region (11) one side to the second conductive type semiconductor drain region (10) one sides.
4. a kind of high-voltage LDMOS device according to claim 3, is characterized in that, the material of described the second conductive type semiconductor drift region (2) is silicon, carborundum, GaAs or germanium silicon.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057904A (en) * | 2016-07-29 | 2016-10-26 | 东莞华南设计创新院 | Germanium-based silicon germanium reduced-field layer LDMOS device structure |
| CN108269841A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | Transverse diffusion metal oxide semiconductor field effect pipe |
| CN108807525A (en) * | 2017-10-23 | 2018-11-13 | 苏州捷芯威半导体有限公司 | Semiconductor devices and preparation method thereof |
| CN109411527A (en) * | 2018-09-22 | 2019-03-01 | 天津大学 | A kind of N-type LDMOS using reduction surface field technology |
| CN110518070A (en) * | 2019-09-03 | 2019-11-29 | 深圳第三代半导体研究院 | One kind being suitable for single chip integrated silicon carbide LDMOS device and its manufacturing method |
| CN110518060A (en) * | 2019-09-07 | 2019-11-29 | 电子科技大学 | Variety lateral doping junction termination structures |
| CN112071896A (en) * | 2020-07-30 | 2020-12-11 | 浙江大学 | Transverse 4H-SiC MOSFET power device |
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| CN1937257A (en) * | 2006-09-14 | 2007-03-28 | 电子科技大学 | High-voltage SensorFET device |
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| CN1937257A (en) * | 2006-09-14 | 2007-03-28 | 电子科技大学 | High-voltage SensorFET device |
Non-Patent Citations (1)
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| S.HARDIKAR，ETC: "A novel double RESURF LDMOS for HVIC"s", 《MICROELECTRONICS JOURNAL》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057904A (en) * | 2016-07-29 | 2016-10-26 | 东莞华南设计创新院 | Germanium-based silicon germanium reduced-field layer LDMOS device structure |
| CN106057904B (en) * | 2016-07-29 | 2018-11-30 | 东莞华南设计创新院 | A kind of germanium base SiGe drop field layer LDMOS device structure |
| CN108269841A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | Transverse diffusion metal oxide semiconductor field effect pipe |
| CN108807525A (en) * | 2017-10-23 | 2018-11-13 | 苏州捷芯威半导体有限公司 | Semiconductor devices and preparation method thereof |
| CN109411527A (en) * | 2018-09-22 | 2019-03-01 | 天津大学 | A kind of N-type LDMOS using reduction surface field technology |
| CN110518070A (en) * | 2019-09-03 | 2019-11-29 | 深圳第三代半导体研究院 | One kind being suitable for single chip integrated silicon carbide LDMOS device and its manufacturing method |
| CN110518060A (en) * | 2019-09-07 | 2019-11-29 | 电子科技大学 | Variety lateral doping junction termination structures |
| CN110518060B (en) * | 2019-09-07 | 2021-03-16 | 电子科技大学 | Lateral variable doped junction termination structure |
| CN112071896A (en) * | 2020-07-30 | 2020-12-11 | 浙江大学 | Transverse 4H-SiC MOSFET power device |
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