CN104201207A - High-voltage MOS (metal oxide semiconductor) device with adaptive bias field plates - Google Patents
High-voltage MOS (metal oxide semiconductor) device with adaptive bias field plates Download PDFInfo
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- CN104201207A CN104201207A CN201410472165.9A CN201410472165A CN104201207A CN 104201207 A CN104201207 A CN 104201207A CN 201410472165 A CN201410472165 A CN 201410472165A CN 104201207 A CN104201207 A CN 104201207A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 230000003044 adaptive effect Effects 0.000 title abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 239000004020 conductor Substances 0.000 claims description 13
- 238000007667 floating Methods 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 230000005684 electric field Effects 0.000 abstract description 19
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 9
- 238000005513 bias potential Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000011982 device technology Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000010534 mechanism of action Effects 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a high-voltage MOS (metal oxide semiconductor) device with adaptive bias field plates. Compared with conventional metal field plates (such as gate field plates, drain field plates and source field plates) connected with constant potential, the adaptive bias field plates have the advantages that on one hand, the adaptive bias field plates can weaken electric field peaks at the tail ends of the conventional metal field plates, and distribution of electric fields on the surface of the device is further optimized; more importantly, bias potential of the adaptive bias field plates can be set as required, thus, effect of improving voltage resistance of the device is more obvious; on the other hand, by the adaptive bias field plates, assistant exhausting effect on a drift region can be enhanced, and doping density of the drift region is high so as to lower specific on-resistance of the device. The adaptive bias field plates can be applied to various power devices and are particularly applicable to high-voltage MOS devices.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of high-pressure MOS component with adaptive-biased field plate.
Background technology
The key of power semiconductor is to realize high-breakdown-voltage and low on-resistance.For conventional LDMOS device, drift region length is monotone increasing with the rising of device electric breakdown strength, and drift region concentration reduces simultaneously; This not only can increase chip area and the cost of device (or circuit), and is unfavorable for chip miniaturization.More seriously, the conducting resistance of device increases with the increase of drift region length (or device withstand voltage), wherein puncture voltage (BV, Breakdown Voltage) and conduction resistance (R
on, sp, Specific on-Resistance) between relation can be expressed as R
on, sp∝ BV
2.5, and the increase of conducting resistance causes device power consumption sharply to increase, and devices switch speed also lowers thereupon.
For improving the puncture voltage of device, researcher has proposed all multi-methods, wherein ties terminal technology and is widely used.Document (Chen Xingbi, [p-n
+the simple expression of surface electric field distribution while having field plate] electronic letters, vol, Vol.14,36 (1986)) in, point out that Metal field plate (as shown in Figure 1) can effectively reduce curvature and the peak surface electric field of the main knot of device and improve the distribution of device surface electric field, thereby improve device electric breakdown strength; But Metal field plate technical deficiency part is the end of Metal field plate and can introduces a new electric field spike and affect the breakdown characteristics of device.
Further, there is researcher to propose slope Metal field plate technology as shown in Figure 2, thereby can reduce Metal field plate end additional electric field kurtosis, improve breakdown characteristic of device; But this technology is applied greatly limited because non-homogeneous oxide layer technique realizes difficulty.
In order to reach the effect similar to non homogen field plate technique and to reduce technology difficulty, there is researcher to propose ladder field plate techniques (Zhang Bo as shown in Figure 3, [improving the non-homogeneous oxide layer field plate techniques of device withstand voltage], semiconductor technology, No.4,19 (1998)), this field plate techniques can be alleviated equally the additional electric field spike of Metal field plate end and improve device electric breakdown strength, and technique is relatively simple; But the realization of ladder field plate technique need to increase the number of mask, so cost can increase to some extent.
Except Metal field plate technology, also there is researcher to propose the resistive field plate techniques of SIPOS (Semi-Insulating Poly-crystalline Silicon) (L.E.Clark and D.S.Zoroglu, [Enhancement of breakdown properties of overlay annular diodes by field shaping resistive films], Solid-State Electronics, vol.15, pp.653-657,1972), as shown in Figure 4.The resistive field plate of this SIPOS is to have introduced polycrystalline resistor layer on the field medium (as field oxide) of device, and the two ends of polycrystalline resistor layer are connected with negative electrode with the anode of device respectively.Owing to having uniform current to flow through on SIPOS resistance, so SIPOS upper from anode to negative electrode between pressure drop even, its coupling makes device drift region Electric Field Distribution even, effectively reduces device surface peak electric field, thereby avoided device surface to puncture in advance, improves device electric breakdown strength; Yet it is larger to flow to the Leakage Current of source electrode by drain electrode in SIPOS, can increase the power consumption of device.
For improving field plate effect, there is researcher to propose to refer to grid field plate (Dawei Xu as Fig. 5 more, Xinhong Cheng and Yuehui Yu, et.al, [Improved LDMOS performance with buried multi-finger gates], Microelectronic Engineering, vol.122 (2014), pp.29-32) and as shown in Figure 6 floating empty becket structure (Jinping Zhang, Yi Ye and Chunhua Zhou, et.al, [High breakdown voltage 4H-SiC MESFETs with floating metal strips], Microelectronic Engineering, vol.85 (2008), pp.89-92) structure, optimizing surface Electric Field Distribution is to improve device electric breakdown strength.
In above field plate techniques, the current potential of field plate is always connected with source electrode or gate electrode, field plate connects a fixed potential, or in floating dummy status, its current potential all can not adaptively be followed the variation of device withstand voltage, makes field plate limited to the optimization function of device surface electric field.
RESURF technology is the common technology of alleviating device electric breakdown strength and conducting resistance contradiction in power semiconductor, and Fig. 7, Fig. 8 and Fig. 9 have provided respectively single-, double-and triple-RESURF technology schematic cross-section.This technology can reduce device peak surface electric field and avoid puncturing in advance, and the while also can be improved the doping content of drift region and be reduced conducting resistance.Document (Y.Koishikawa, M.Takahashi, H.Yangigawa, and T.Kunyama, [Double RESURF device technology for power ICs], NEC RES Dev., 1994,359 (4), Mohamed Imam, Zia Hossain, Mohammed Quddus, Jim Adams, Charles Hoggatt, Takeshi Ishiguro, and Rajesh Nair, [Design and Optimization of Double-RESURF High-VoltageLateral Devices for a Manufacturable Process], IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.50, NO.7, JULY2003) in, provided RESURF technology to improving device electric breakdown strength and the effect that reduces conducting resistance, therefrom can find out that RESURF technology effectively alleviated the contradictory relation of 2.5 powers between device electric breakdown strength and conduction resistance.But the P type layer in RESURF technology need to take the part current channel in N-type drift region and be unfavorable for further reducing conducting resistance.
Summary of the invention
Object of the present invention, is exactly for the problems referred to above, proposes a kind of high-pressure MOS component with adaptive-biased field plate.
Technical scheme of the present invention: a kind of high-pressure MOS component with adaptive-biased field plate, comprise the first conductive type semiconductor substrate 1, be positioned at the first conductive type semiconductor substrate 1 upper strata the second conductive type semiconductor drift region 2 and the first conductive type semiconductor tagma 3, be positioned at the second conductive type semiconductor drift region 2 and 3 upper stratas, the first conductive type semiconductor tagma field dielectric layer 7; 3 upper stratas, described the first conductive type semiconductor tagma are provided with separate the first conductive type semiconductor body contact zone 5 and the second conductive type semiconductor source region 4; The first conductive type semiconductor body contact zone 5 and the second conductive type semiconductor source region 4 upper surfaces arrange active electrode 8; The second 2 upper stratas, conductive type semiconductor drift region is provided with the second conductive type semiconductor drain region 6 away from the one end in the first conductive type semiconductor tagma 3; The second conductive type semiconductor drain region 6 upper surfaces are provided with drain electrode 10; Between described source electrode 8 and drain electrode 10, be provided with gate electrode 9; Described gate electrode 9 contacts with the second conductive type semiconductor source region 4 with the first conductive type semiconductor tagma 3; It is characterized in that, also comprise adaptive-biased field plate, described adaptive-biased field plate consists of field plate 11 and film resistor 13; Wherein, described field plate 11 and film resistor 13 electrical connections; Described field plate 11 arranges the upper surface of dielectric layer 7 on the scene; One end of described film resistor 13 and 8 electrical connections of source electrode, its other end and drain electrode 10 electrical connections.
The technical scheme that the present invention is total, the Metal field plate being connected with fixed potential with tradition (as grid field plate, leakage field plate and source field plate) is compared, on the one hand, automatic biasing field plate can weaken the electric field spike of common metal field plate termination, further the distribution of optimised devices surface field; The more important thing is, the bias potential of automatic biasing field plate can be set as required; Thereby its effect that improves device withstand voltage is more obvious.On the other hand, automatic biasing field plate can strengthen the assisted depletion effect to drift region, and high drift region doping content is to reduce device conduction resistance; And this device and stand CMOS flow process can be good compatible.This automatic biasing field plate can be applied in multiple power device.
Concrete, between described field plate 11 and film resistor 13, be provided with passivation layer 12; Between described field plate 11 and film resistor 13, for passing through electric conducting material (144), set up electrical connection; One end of described film resistor 13 and source electrode 8 are for setting up electrical connection by electric conducting material (141), and its other end and drain electrode 10 are for setting up electrical connection by electric conducting material (143).
Concrete, described field plate (11) consists of m separate subfield plate, and each subfield plate is set up electrical connection by electric conducting material (145) and film resistor (13); Wherein, m is positive integer.
Concrete, in described m sub-field plate, there is n sub-field plate to be connected with source electrode 8, there is k sub-field plate to be connected with drain electrode 10, there is j sub-field plate to be connected with gate electrode 9, there is h sub-field plate in floating dummy status; Wherein n, k, j, h are natural number and n+k+j+h < m, n >=0, k >=0, j >=0, h >=0.
Concrete, described the second conductive type semiconductor drift region 2 is super-junction structure.
Between substrate and active layer, also can introduce buried regions medium 20, form the high pressure SOI LDMOS formation soi structure with automatic biasing field plate; The substrate layer 1 of described soi structure is the first conduction type or the second conductive type semiconductor; Described buried regions medium 20 is low-K dielectrics that silicon dioxide or dielectric coefficient are less than dioxide dielectric coefficient; The drift region of power MOS (Metal Oxide Semiconductor) device can increase by the first conductive type semiconductor layer 18, or the surface of described drift region forms the first conductive type semiconductor layer 17; The formation material of the film resistor 13 forming on passivation layer 12 is polysilicons, or nichrome, tantalum nitride, tin oxide etc.; Described dielectric layer 7, dielectric 91 are materials such as high K that silicon dioxide or dielectric coefficient are larger than dioxide dielectric coefficient; The domain with the high-voltage power MOS device of automatic biasing field plate is that interdigitated distribution, ring-type or symmetrical polygon distribute; In power device district, the drift region of the second conduction type adopts Uniform Doped, or adopts horizontal varying doping technology
Beneficial effect of the present invention is, by automatic biasing field plate, the field plate on power device surface introduced to adaptive bias voltage, makes device surface Electric Field Distribution more evenly improve device electric breakdown strength; Automatic biasing field plate can assisted depletion drift region and improve doped level, reduces device conducting resistance; Automatic biasing field plate is not introduced additional parasitic capacitance, does not affect devices switch and frequency characteristic; This device and stand CMOS flow process can be good compatible.
Accompanying drawing explanation
Fig. 1 is the structural representation of common metal field plate;
Fig. 2 is the structural representation of slope oxide layer Metal field plate;
Fig. 3 is the structural representation of ladder oxide layer Metal field plate;
Fig. 4 is the structural representation of the resistive field plate of conventional SIPOS;
Fig. 5 is the LDMOS device architecture schematic diagram with a plurality of grid field plates;
Fig. 6 has the LDMOS device architecture schematic diagram of floating empty becket;
Fig. 7 is the schematic cross-section of conventional single-RESURF structure;
Fig. 8 is the schematic cross-section of conventional double-RESURF structure;
Fig. 9 is the schematic cross-section of conventional triple-RESURF structure;
Figure 10 is the high-voltage LDMOS device strip domain distribution vertical view with automatic biasing field plate that the present invention proposes;
Figure 11 is the circular domain distribution of the high-voltage LDMOS device with the automatic biasing field plate vertical view that the present invention proposes;
Figure 12 is along dotted line M in Figure 10 and Figure 11
1m
2generalized section;
Figure 13 is along dotted line N in Figure 10 and Figure 11
1n
2generalized section;
Figure 14 is the high-voltage LDMOS device strip domain distribution schematic diagram with a plurality of automatic biasing field plates that the present invention proposes;
Figure 15 is the circular domain distribution schematic diagram of the high-voltage LDMOS device with a plurality of automatic biasing field plates that the present invention proposes;
Figure 16 is along dotted line M in Figure 14 and Figure 15
1m
2generalized section;
Figure 17 is along dotted line N in Figure 14 and Figure 15
1n
2generalized section;
Figure 18 is the strip domain distribution schematic diagram of the high-voltage LDMOS device dielectric layer on the scene with automatic biasing field plate that proposes of the present invention;
Figure 19 is that the high-voltage LDMOS device with automatic biasing field plate and source field plate that proposes of the present invention is at the strip domain distribution schematic diagram of passivation layer;
Figure 20 is along dotted line M in Figure 19
1m
2generalized section;
Figure 21 is along dotted line L in Figure 19
1l
2generalized section;
Figure 22 be the present invention propose there is automatic biasing field plate and leak the high-voltage LDMOS device of field plate at the strip domain distribution schematic diagram of passivation layer;
Figure 23 is along dotted line M in Figure 22
1m
2generalized section;
Figure 24 is along dotted line L in Figure 22
1l
2generalized section;
Figure 25 is that the high-voltage LDMOS device with automatic biasing field plate and grid field plate that proposes of the present invention is at the strip domain distribution schematic diagram of passivation layer;
Figure 26 is along dotted line M in Figure 25
1m
2generalized section;
Figure 27 is along dotted line N in Figure 25
1n
2generalized section;
Figure 28 is that the high-voltage LDMOS device with automatic biasing field plate and floating empty becket that proposes of the present invention is at the strip domain distribution schematic diagram of passivation layer;
Figure 29 is along dotted line M in Figure 28
1m
2generalized section;
Figure 30 is along dotted line N in Figure 28
1n
2generalized section;
Figure 31 is the high-voltage LDMOS device structural profile schematic diagram with automatic biasing field plate of the double-RESURF that proposes of the present invention;
Figure 32 is the high-voltage LDMOS device structural profile schematic diagram with automatic biasing field plate of the triple-RESURF form that proposes of the present invention;
Figure 33 is the planar gate type high pressure SOILDMOS device architecture generalized section with automatic biasing field plate that the present invention proposes;
Figure 34 is the groove gate type high pressure SOILDMOS device architecture generalized section with automatic biasing field plate that the present invention proposes;
Figure 35 is the super junction type LDMOS of the high pressure with the automatic biasing field plate device architecture schematic diagram that the present invention proposes;
Figure 36 is the circular domain distribution schematic diagram of the high-voltage LDMOS device dielectric layer on the scene with automatic biasing field plate that proposes of the present invention;
Figure 37 is that the high-voltage LDMOS device with automatic biasing field plate that proposes of the present invention is at the circular domain distribution schematic diagram of passivation layer;
Embodiment
Below in conjunction with accompanying drawing with the high-voltage LDMOS embodiment that N raceway groove has an automatic biasing field plate, the present invention is described in detail
Embodiment 1:
As shown in figure 10, this example is for having the high-voltage LDMOS device list structure domain distribution schematic diagram of automatic biasing field plate, and Figure 12 is along dotted line M in Figure 10
1m
2generalized section, Figure 13 is along dotted line N in Figure 10
1n
2generalized section, comprise substrate layer 1 from top to down, active layer 2 and a dielectric layer 7.High-voltage LDMOS device also comprises P type tagma 3, source region 4, body contact zone 5, drain region 6, dielectric 91, electric conducting material 92 and field plate 11, and wherein the active layer 2 between tagma 3 and drain region 6 is called drift region, and dielectric 91 forms insulated gate with electric conducting material 92.The common exit of source region 4 and body contact zone 5 is source electrode 8, and the exit in drain region 6 is drain electrode 10.Field plate 11 is positioned at the upper surface of a dielectric layer 7.
Film resistor 13 is positioned at a dielectric layer 7 upper surfaces, the two ends of film resistor 13 respectively with source electrode 8 and drain electrode 10 electrical contacts, field plate 11 contact with film resistor 13, thus formation automatic biasing field plate.
This routine operation principle is:
Theoretical based on electric resistance partial pressure, because field plate 11 contacts with film resistor 13, the bias voltage on field plate 11 picks up from film resistor 13.By changing the contact position of field plate 11 and film resistor 13, can realize the bias voltage modulation to field plate 11; Meanwhile, the biased electrical pressure energy self adaptation on field plate 11 is followed the variation of the added voltage of MOS device drain and MOS device withstand voltage and is changed, and realizes the optimal modulation effect to device surface electric field, improves device electric breakdown strength.Meanwhile, this automatic biasing field plate energy assisted depletion drift region, improves drift region doping content and reduces device conduction resistance
Field medium 7 is silicon dioxide or the dielectric coefficient dielectric material higher than silicon dioxide; When medium 7 is high-k material, can strengthen the assisted depletion effect of automatic biasing field plate to drift region then and there, favourable reduction device conducting resistance.
This example is also applicable to circulus, and as shown in figure 11, its principle is identical with list structure, does not repeat them here for its domain.
Figure 14 and Figure 15 are the high-voltage LDMOS device strip with a plurality of automatic biasing field plates and the ring-type domain structure schematic diagrames that the present invention proposes, and Figure 16 is along dotted line M in Figure 14 and Figure 15
1m
2generalized section, Figure 17 is along dotted line N in Figure 14 and Figure 15
1n
2generalized section.Compare with structure shown in Figure 11 with Figure 10, structure shown in Figure 14 and Figure 15 has a plurality of (n >=1) automatic biasing field plate.A plurality of automatic biasing field plates can better optimised devices surface electric field distribution, favourable raising device electric breakdown strength.
Figure 36 and Figure 37 are high-voltage LDMOS domain and the generalized sections with automatic biasing field plate that the present invention proposes.That now film resistor 13 is positioned at passivation layer 12 upper surfaces with the difference of Figure 11, Figure 12.The two ends of film resistor 13 contact with drain electrode 10 with the source electrode 8 of MOS device with 143 by electric conducting material 142 respectively, field plate 11 contacts with film resistor 13 by electric conducting material 144, thereby form automatic biasing field plate, by changing the contact position of electric conducting material 144 and film resistor 13, can realize the bias voltage modulation to field plate 11.
In the present invention, for realizing the film resistor 13 of adaptive-biased voltage on field plate, be positioned at device field dielectric layer 7 or passivation layer 12, effectively reduce device parasitic capacitance, affect hardly switching characteristic and the frequency characteristic of device.
Figure 19-Figure 21, Figure 22-Figure 24, Figure 25-Figure 27, Figure 28-Figure 30 are respectively the high-voltage LDMOS device vertical view and the profiles that have automatic biasing field plate and source field plate, have automatic biasing field plate and grid field plate, have automatic biasing field plate structure and leak field plate, have automatic biasing field plate and floating empty becket that the present invention proposes; Wherein in Figure 19-Figure 21, field plate 111 is connected with source electrode potential, and in Figure 22-Figure 24, field plate 113 is connected with drain electrode current potential, and in Figure 25-Figure 27, field plate 111 is connected with gate electrode potential, and in Figure 28-Figure 30, field plate 112 is in floating dummy status.The terminal technology combinations such as automatic biasing field plate and conventional source field plate, grid field plate, leakage field plate or floating empty becket are used, and have improved the flexibility of device design, and effective optimised devices surface electric field distribution is to improve device electric breakdown strength.These applied in any combination can not increase device technology and realize difficulty.
Adaptive-biased field plate operation principle in said structure is identical with embodiment 1.
Embodiment 2:
As shown in figure 31, this example has the high-voltage LDMOS device generalized section of automatic biasing field plate for double-RESURF type.Compare structure shown in Figure 16, this example is in surface, drift region and body, to introduce p-type buried regions to form double-RESURF mechanism of action.By optimizing the position of automatic biasing field plate 11 or 111,112,113 and p-type buried regions, the common modulation device surface electric field distribution of RESURF and automatic biasing field plate also improves drift region doping content, thereby improves device electric breakdown strength and reduce device conduction resistance.
The adaptive-biased field plate operation principle of this example is identical with embodiment 1.
, also applicable to triple-RESURF type structure, shown in figure 32, be in like manner the high-voltage LDMOS device structural profile schematic diagram with automatic biasing field plate of triple-RESURF form, its principle is identical with embodiment 2, does not repeat them here.
Embodiment 3:
Shown in Figure 33, for this routine planar gate type has the high pressure SOI LDMOS device architecture generalized section of automatic biasing field plate.Wherein substrate layer 1 is P type.Such device also has the plurality of advantages that SOI device has.
The adaptive-biased field plate operation principle of this example is identical with embodiment 1.
In like manner also be applicable to groove gate type structure, as shown in figure 34, for having the groove gate type high pressure SOILDMOS device architecture generalized section of automatic biasing field plate, its principle is identical with embodiment 3.
Embodiment 4:
The automatic biasing field plate that the present invention proposes is also applicable to super junction device.
As shown in figure 25, in order to have the super junction type LDMOS device architecture schematic diagram of automatic biasing field plate, (the bias potential connected mode in figure on field plate 111,112,113 can be connected with source electrode, drain electrode or gate electrode this example, or in floating dummy status, in this figure, do not mark out).The distribution of automatic biasing field plate energy modulation device surface field is to improve device electric breakdown strength, and super junction device has lower conduction resistance, and the two combination is boost device overall performance effectively.
The adaptive-biased field plate operation principle of this example is identical with embodiment 1.
The high-voltage power MOS device with automatic biasing field plate that the present invention proposes, its domain can also be that the interdigitated as shown in Figure 14, Figure 18, Figure 19, Figure 22, Figure 25, Figure 28 distributes, or the annulus as shown in Figure 15 and Figure 37 is symmetrical; Wherein Figure 14 and Figure 15 have described and on the high-voltage power MOS device dielectric layer 7 on the scene with automatic biasing field plate, have formed field plate 11 and film resistor 13, and Figure 19, Figure 22, Figure 25, Figure 28 and Figure 37 have described the high-voltage power MOS device with automatic biasing field plate and on passivation layer 12, formed film resistor 13.
The high-voltage power MOS device with automatic biasing field plate that the present invention proposes, its domain also symmetrical polygon distributes, as regular hexagon and octagon distribution etc.
In above case study on implementation, automatic biasing field plate is also applicable to IGBT, thyristor and diode constant power device.
Claims (5)
1. a high-pressure MOS component with adaptive-biased field plate, comprise the first conductive type semiconductor substrate (1), be positioned at the first conductive type semiconductor substrate (1) upper strata the second conductive type semiconductor drift region (2) and the first conductive type semiconductor tagma (3), be positioned at the second conductive type semiconductor drift region (2) and the first upper strata, conductive type semiconductor tagma (3) field dielectric layer (7); Described the first upper strata, conductive type semiconductor tagma (3) is provided with the first separate conductive type semiconductor body contact zone (5) and the second conductive type semiconductor source region (4); The first conductive type semiconductor body contact zone (5) and the second conductive type semiconductor source region (4) upper surface arrange active electrode (8); The second upper strata, conductive type semiconductor drift region (2) is provided with the second conductive type semiconductor drain region (6) away from the one end in the first conductive type semiconductor tagma (3); The second conductive type semiconductor drain region (6) upper surface is provided with drain electrode (10); Between described source electrode (8) and drain electrode (10), be provided with gate electrode (9); Described gate electrode (9) contacts with the second conductive type semiconductor source region (4) with the first conductive type semiconductor tagma (3); It is characterized in that, also comprise adaptive-biased field plate, described adaptive-biased field plate consists of field plate (11) and film resistor (13); Wherein, described field plate (11) and film resistor (13) electrical connection; Described field plate (11) arranges the upper surface of dielectric layer on the scene (7); One end of described film resistor (13) and source electrode (8) electrical connection, its other end and drain electrode (10) electrical connection.
2. a kind of high-pressure MOS component with adaptive-biased field plate according to claim 1, is characterized in that, between described field plate (11) and film resistor (13), is provided with passivation layer (12); Between described field plate (11) and film resistor (13), for passing through electric conducting material (145), set up electrical connection; One end of described film resistor (13) and source electrode (8) are for setting up electrical connection by electric conducting material (141), and its other end and drain electrode (10) are for setting up electrical connection by electric conducting material (143).
3. a kind of high-pressure MOS component with adaptive-biased field plate according to claim 2, it is characterized in that, described field plate (11) consists of m separate subfield plate, and each subfield plate is set up electrical connection by electric conducting material (145) and film resistor (13); Wherein, m is positive integer.
4. a kind of high-pressure MOS component with adaptive-biased field plate according to claim 3, it is characterized in that, in described m sub-field plate, there is n sub-field plate to be connected with source electrode (8), there is k sub-field plate to be connected with drain electrode (10), there is j sub-field plate to be connected with gate electrode (9), have h sub-field plate in floating dummy status; Wherein n, k, j are all, h is natural number and n+k+j+h < m, n >=0, k >=0, j >=0, h >=0.
5. according to a kind of high-pressure MOS component with adaptive-biased field plate described in claim 1-4 any one, it is characterized in that, described the second conductive type semiconductor drift region (2) is super-junction structure.
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| CN104752512A (en) * | 2015-01-09 | 2015-07-01 | 电子科技大学 | Transverse high-voltage device with multi-electrode structure |
| CN113707717A (en) * | 2021-08-31 | 2021-11-26 | 电子科技大学 | Power device with multi-floating field plate and collector PMOS structure |
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Application publication date: 20141210 |