CN108807525A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN108807525A CN108807525A CN201710992137.3A CN201710992137A CN108807525A CN 108807525 A CN108807525 A CN 108807525A CN 201710992137 A CN201710992137 A CN 201710992137A CN 108807525 A CN108807525 A CN 108807525A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 300
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 210000000746 body region Anatomy 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 12
- 230000010287 polarization Effects 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 18
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000006378 damage Effects 0.000 description 5
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004549 pulsed laser deposition Methods 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 238000003877 atomic layer epitaxy Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- 239000012212 insulator Substances 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000004153 renaturation Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
A kind of semiconductor devices of offer of the embodiment of the present invention and preparation method thereof, wherein the semiconductor devices includes substrate；The first semiconductor layer positioned at the one side of substrate；Positioned at second semiconductor layer and third semiconductor layer of first semiconductor layer far from the one side of substrate；The source electrode and grid made based on the third semiconductor layer；Wherein, the third semiconductor layer is n-type doping, and the third semiconductor layer includes p-type doped body region, the p-type doped body region includes N+ types doped body region and P+ type doped body region, the source electrode is contacted with the N+ types doped body region and P+ type doped body region, wherein, second semiconductor layer and first semiconductor layer can form two-dimensional electron gas by polarization.The semiconductor device structure that the present invention provides is simple, easily manufactured, has higher uniformity and stability, and its opening and closing can be controlled by grid, realizes enhanced semiconductor device.
Description
Technical field
The present invention relates to microelectronics technologies, in particular to a kind of semiconductor devices and preparation method thereof.
Background technology
In terms of semi-conductor electronic device, AlGaN/GaN high electron mobility transistor (High Electron
Mobility Transistor, HEMT) be with high concentration two-dimensional electron gas (Two-Dimensional Electron Gas,
Wide band gap semiconductor device 2DEG) has high output power density, high temperature resistant, the spy that stability is strong and breakdown voltage is high
Point has very big application potential in power electronic devices field.
Wherein, since, there are stronger two-dimensional electron gas, generally use AlGaN/GaN is different in AlGaN/GaN heterojunction structures
The high electron mobility transistor that matter knot is formed is depletion device, and enhancement device is then not easy to realize.Depletion device
Application increase the complexity of circuit design, and be easy to cause to open by mistake and open, security of system declines.Enhancement device needs
Grid adds positive pressure that could open, and reduces the complexity of circuit, while also improving safety, real in power electronics applications
Existing gallium nitride enhancement device is an important research direction.
Invention content
In view of this, the present invention provides a kind of semiconductor devices and preparation method thereof, the above problem can effectively solve the problem that.
Present pre-ferred embodiments provide a kind of semiconductor devices, including：
Substrate；
The first semiconductor layer positioned at the one side of substrate；
Positioned at second semiconductor layer and third semiconductor layer of first semiconductor layer far from the one side of substrate；
The drain electrode to be formed is made based on second semiconductor layer；
The source electrode and grid made based on the third semiconductor layer；Wherein,
The third semiconductor layer is n-type doping, and the third semiconductor layer includes p-type doped body region, the p-type doping
Body area includes N+ types doped body region and P+ type doped body region, and the source electrode connects with the N+ types doped body region and P+ type doped body region
It touches.
In the selection of present pre-ferred embodiments, N+ types doped body region is located in p-type doped body region close to grid
Side, the P+ type doped body region be located in p-type doped body region far from grid side.
In the selection of present pre-ferred embodiments, gate dielectric, the gate dielectric are formed based on the fabrication
It is contacted respectively with N+ types doped body region, the p-type doped body region and the third semiconductor layer.
In the selection of present pre-ferred embodiments, second semiconductor layer and the third semiconductor layer are made in
First semiconductor layer is covered each by first semiconductor layer far from the one side of substrate far from the one side of substrate
Part surface.
In the selection of present pre-ferred embodiments, it is separate that second semiconductor layer is made in first semiconductor layer
One side of substrate, and the part surface of the first semiconductor layer side is covered, the third semiconductor layer is by described first
Semiconductor layer does not carry out ion implanting by the part of the second semiconductor layer covering and is formed.
In the selection of present pre-ferred embodiments, the third semiconductor layer is located at second semiconductor layer far from institute
State the side of the first semiconductor layer.
In the selection of present pre-ferred embodiments, the third semiconductor layer open up it is fluted, the grid be located at should
In groove, gate dielectric is filled between the grid and the groove.
In the selection of present pre-ferred embodiments, the grid is located at the third semiconductor layer far from described the first half
The one side of conductor layer has gate dielectric between the grid and the third semiconductor layer.
In the present invention, the doping concentration of the p-type doped body region is modulated, and the threshold voltage of the semiconductor devices can
Modulation.
In the selection of present pre-ferred embodiments, the p-type doped body region close to the grid side edge with
There are gaps between the edge close to the grid side for the third semiconductor layer.
Present pre-ferred embodiments also provide a kind of production method of semiconductor devices, the method includes：
One substrate is provided；
The first semiconductor layer is formed in the side of the substrate；
The second semiconductor layer and third semiconductor layer are formed in side of first semiconductor layer far from the substrate；
P-type doped body region is made based on the third semiconductor layer, N+ type doping bodies are made based on the p-type doped body region
Area and P+ type doped body region；And
Source electrode and grid are made based on the third semiconductor layer, makes the source electrode and N+ types doped body region and P+ type
Doped body region Ohmic contact makes drain electrode based on second semiconductor layer.
In the selection of present pre-ferred embodiments, the is formed in side of first semiconductor layer far from the substrate
Two semiconductor layers and third semiconductor layer, the step of include：
The second semiconductor layer is formed in side of first semiconductor layer far from substrate；
The subregion for exposing first semiconductor layer is performed etching to second semiconductor layer；
Third semiconductor layer is formed in region of first semiconductor layer not by the covering of the second semiconductor layer.
In the selection of present pre-ferred embodiments, in the area that first semiconductor layer is not covered by the second semiconductor layer
Domain formed third semiconductor layer the step of include：
In first semiconductor layer described the is not formed by the area deposition semi-conducting material that the second semiconductor layer covers
Three semiconductor layers；Or
Part to first semiconductor layer not by the covering of the second semiconductor layer carries out ion implanting, forms the third
Semiconductor layer.
In the selection of present pre-ferred embodiments, the grid makes to be formed by following steps：
The third semiconductor layer is performed etching, groove is formed；
Gate dielectric is filled in the groove；
Grid material is filled in the groove forms grid.
Semiconductor devices provided by the invention and preparation method thereof, wherein by the ingehious design to the semiconductor devices,
The opening and closing of the semiconductor devices can be controlled by grid, realize enhanced semiconductor device.Meanwhile the present invention is implemented
Example can improve the threshold voltage of enhanced semiconductor devices, and the threshold voltage can be in wide range internal modulation.
Further, the semiconductor device structure that the present embodiment provides is simple, easily manufactured, have higher uniformity and
Stability, and the semiconductor devices uses heterojunction structure as drift region, receiver is mainly pressure-resistant.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the structural schematic diagram for the semiconductor devices that the embodiment of the present invention one provides.
Fig. 2 is the structural schematic diagram of semiconductor devices provided by Embodiment 2 of the present invention.
Fig. 3 is the structural schematic diagram for the semiconductor devices that the embodiment of the present invention three provides.
Fig. 4 is the structural schematic diagram for the semiconductor devices that the embodiment of the present invention four provides.
Fig. 5 is the flow diagram of the production method of semiconductor devices provided in an embodiment of the present invention.
Fig. 6 is the sub-process schematic diagram of the production method of semiconductor devices provided in an embodiment of the present invention.
Fig. 7 is another sub-process schematic diagram of the production method of semiconductor devices provided in an embodiment of the present invention.
Fig. 8 (a) to Fig. 8 (d) is the making step status diagram for the semiconductor devices that the embodiment of the present invention provides.
Icon：10- semiconductor devices；11- substrates；The first semiconductor layers of 12-；The second semiconductor layers of 13-；14- thirds half
Conductor layer；140-P types doped body region；141-P+ types doped body region；142-N+ types doped body region；15- source electrodes；16- grids；160-
Gate dielectric；17- drains.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment only
It is a part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings
The component of embodiment can be arranged and be designed with a variety of different configurations.
Therefore, below the detailed description of the embodiment of the present invention to providing in the accompanying drawings be not intended to limit it is claimed
The scope of the present invention, but be merely representative of the present invention selected embodiment.Based on the embodiments of the present invention, this field is common
The every other embodiment that technical staff is obtained without creative efforts belongs to the model that the present invention protects
It encloses.
It should be noted that：Similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined, then it further need not be defined and explained in subsequent attached drawing in a attached drawing.In description of the invention
In, " first, second, third, fourth etc. is only used for distinguishing description term, and should not be understood as only or imply relative importance.
In the description of the present invention unless specifically defined or limited otherwise, term " setting ", " connected ", " connection " are answered
It is interpreted broadly, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；Can be that machinery connects
It connects, can also be electrical connection；It can be directly connected, can also can be indirectly connected through an intermediary in two elements
The connection in portion.For the ordinary skill in the art, the tool of above-mentioned term in the present invention can be understood with concrete condition
Body meaning.
Firstly the need of explanation, in the prior art, mainly enhanced semiconductor device is realized by following methods
Part.
(1) groove technology reduces two-dimensional electron gas density at raceway groove, to make by the barrier layer below etching grid
Device threshold voltage forward direction moves.The enhanced HEMT device formed using this method, on the one hand, the potential barrier thickness below grid
Degree is not easy to be precisely controlled, and the consistency of performance and repeatability of the enhanced GaN HEMT devices of manufacture are difficult to ensure；On the other hand,
It etches deeper slot grid the carrier mobility of raceway groove is caused to damage.
(2) two-dimensional electron gas formation gallium nitride enhancement device at raceway groove is exhausted using to injection fluorine ion below grid,
But fluorine ion is all injected in grid lower barrierlayer, carrier mobility is had an impact；On the other hand, the mistake of fluorine ion is injected
Cheng Rongyi causes to damage to abarrier layer material, to influence the reliability of device.
(3) side introduces the cap layer structure that P-type is adulterated under the gate.Due to the conduction band of P-GaN cap layer structures and AlGaN layer
Difference makes the conduction band of the interfaces AlGaN/GaN be increased to above fermi level, exhausts the 2DEG at raceway groove, realizes enhanced.But
The P-GaN cap layers other than etching removal grid are needed in device fabrication processes, introduce etching injury, current collapse is serious.
From the aforegoing it can be seen that the problem of how alleviating above-mentioned 3 kinds of enhancement devices, realizes a kind of with high uniform
The enhanced semiconductor device of property, stability and resistance to pressure seems very necessary, below will be by four embodiments to the present invention
The semiconductor devices provided is described in detail.
Embodiment one
Referring to Fig. 1, a kind of structural schematic diagram of the semiconductor devices 10 provided for the embodiment of the present invention one, wherein should
Semiconductor devices 10 include substrate 11, the first semiconductor layer 12, the second semiconductor layer 13 and third semiconductor layer 14, source electrode 15,
Grid 16 and drain electrode 17.First semiconductor layer 12 is located at 11 side of the substrate, second semiconductor layer 13 and institute
It states third semiconductor layer 14 and is located at first semiconductor layer 12 far from 11 side of the substrate, the third semiconductor layer 14 exists
Upright projection area coverage on the substrate 11 is less than upright projection covering of first semiconductor layer 12 on the substrate 11
Area.The source electrode 15 and the grid 16 are made based on the third semiconductor layer 14, and the drain electrode 17 is based on described second
Semiconductor layer 13 makes.It should be noted that in embodiment one, second semiconductor layer 13 and the third semiconductor layer 14 are made
Make in first semiconductor layer 12 far from 11 side of substrate, and is covered each by the separate substrate 11 of first semiconductor layer 12
The part surface of side, and second semiconductor layer 13 and first semiconductor layer 12 can form Two-dimensional electron by polarization
Gas.
Wherein, the third semiconductor layer 14 is n-type doping, and the third semiconductor layer 14 includes p-type doped body region
140, the p-type doped body region 140 includes N+ types doped body region 142 and P+ type doped body region 141, N+ types doped body region
142 are located at close to the side of the grid 16, and the P+ type doped body region 141 is located remotely from the side of grid 16, the source electrode
15 contact with the N+ types doped body region 142 and the P+ type doped body region 141.Preferably, the source electrode 15 is adulterated with the N+ types
Body area 142 and P+ type doped body region 141 form Ohmic contact.
In addition, the source electrode 15 is contacted completely or partially with the P+ type doped body region 141 and the source electrode 15 and institute
State the contact of 142 part of N+ types doped body region.140 bottom of p-type doped body region can be in third semiconductor layer 14, can also
It is deep into the first semiconductor layer 12, it is preferable that 140 bottom of p-type doped body region extends to first semiconductor layer 12
In, help to reduce Leakage Current and optimizes the field distribution of the grid 16.
Optionally, N+ types doped body region 142 and P+ type doped body region 141 can contact and can also separate.It is practical real
Depth is injected preferably compared with shallow implant depth in Shi Shi, the P+ type doped body region 141.In addition, the grid 16 is located at the leakage
Far from 17 one end of the drain electrode between pole 17 and the source electrode 15 or positioned at the source electrode 15, the present embodiment is without limitation.
Further, in the third semiconductor layer 14, the p-type doped body region 140 is close to the grid 16
One side edge is misaligned close to 16 one side edge of the grid with the third semiconductor layer 14 and there are gaps.Preferably,
Gap is less than or equal to 0.5um, and can reduce electronics using such setting in the present embodiment enters Two-dimensional electron gas channel from raceway groove
The path of process advantageously reduces the overall electrical resistance of the semiconductor devices 10.
The doping concentration of p-type doped body region 140 is variable in semiconductor device structure of the present invention, by modulating p-type
The doping concentration of doped body region 140 realizes the different threshold voltage of device, for example, the doping concentration range of p-type doped body region 140
105/cm3-1020/cm3, doping concentration is higher, and grid 16 makes the p-type doped body region required voltage of 140 transoid higher,
Threshold voltage is higher.
When actual implementation, sapphire (sapphire), silicon carbide (SiC), silicon (Si), niobic acid may be used in the substrate 11
Lithium, silicon-on-insulator, gallium nitride (GaN), one kind in aluminium nitride (AlN) or well known to those skilled in the art any
Other are suitble to the material for growing group III-nitride to be formed, and the present invention is not particularly limited this.
The material of first semiconductor layer 12 is preferably gallium nitride.The material of second semiconductor layer 13 can be
Two dimension electricity can be formed well known to the semiconductor technologies personnel such as AlGaN, AlN or InAlN with the GaN (the first semiconductor layer 12)
The material of sub- gas, preferably III-nitride semiconductor material.The material of the third semiconductor layer 14 is preferably GaN, and is
N-type doping, and the material of the third semiconductor layer 14 can be with the material or the second semiconductor of first semiconductor layer 12
The material identical of layer 13, specifically, the present embodiment is not limited.
In addition, be formed with gate dielectric 160 based on the making of the grid 16, the gate dielectric 160 respectively with the N+
Type doped body region 142, the p-type doped body region 140 and the third semiconductor layer 14 contact.Optionally, the grid is situated between
The material of matter 160 can be SiO2, AlN or aluminium oxide (Al2O3) etc., in the present embodiment, the gate dielectric 160 can have
Effect reduces the leakage current of the grid 16.
Further, the grid 16 can be planar gate or groove profile grid, for example, in the present embodiment one, the grid
Pole 16 is preferably planar gate, and is located at one side of the third semiconductor layer 14 far from first semiconductor layer 12, described
There is gate dielectric 160, and the gate dielectric 160 is adulterated with the N+ types successively between grid 16 and the third semiconductor layer 14
Body area 142, p-type doped body region 140 and third semiconductor layer 14 contact.When really implementing, the grid 16 and the grid
Medium 160 also may extend to the surface of second semiconductor layer 13, help to reduce the surface Leakage Current and conducting resistance.
Embodiment two
Fig. 2 is the structural schematic diagram of the semiconductor devices 10 provided in the embodiment of the present invention two.As shown in Fig. 2, this implementation
Example two is similar with embodiment one, wherein the two the difference is that, in embodiment two, second semiconductor layer 13 is made
Make in first semiconductor layer 12 far from 11 side of the substrate, and covers the part table of 12 side of the first semiconductor layer
Face, the third semiconductor layer 14 be by part that first semiconductor layer 12 is not covered by the second semiconductor layer 13 into
Row ion implanting and formed.In addition, in the present embodiment two, the grid 16 is preferably planar gate.
Compared with embodiment one, the semiconductor devices 10 provided in embodiment two generates third semiconductor layer without additional
14, reduce process complexity.
Embodiment three
Fig. 3 is the structural schematic diagram of the semiconductor devices 10 provided in the embodiment of the present invention three.As shown in figure 3, this implementation
Example three is similar with embodiment one, the difference is that, in embodiment three, the third semiconductor layer 14 is located at described second
Side of the semiconductor layer 13 far from first semiconductor layer 12.
Wherein, due in embodiment one, forming the first semiconductor layer 12 on the substrate 11 first, then this
Side of the semi-conductor layer 12 far from substrate 11 forms the second semiconductor layer 13, then is carved to second semiconductor layer 13
Erosion so that second semiconductor layer 13 only covers the part surface of 12 side of the first semiconductor layer, finally not described
The region of second semiconductor layer 13 covering forms third semiconductor layer 14, and such implementation need to be by second semiconductor layer 13
The interface for etching into AlGaN (aluminum gallium nitride)/GaN, easily causes to damage to two-dimensional electron gas.And half provided in the present embodiment three
The structure of conductor device 10, it is not necessary that the subregion of second semiconductor layer 13 is etched away by way of etching, to
The destruction to first semiconductor layer 12 (two-dimensional electron gas) is avoided, and then improves the globality of the semiconductor devices 10
Energy.
Example IV
Fig. 4 is the structural schematic diagram of the semiconductor devices 10 provided in the embodiment of the present invention four.As shown in figure 4, this implementation
Example four is similar with embodiment three, the difference is that, in example IV, the third semiconductor layer 14 open up it is fluted,
The grid 16 is located in the groove, gate dielectric 160 is filled between the grid 16 and the groove, and the grid 16 is located at
The source electrode 15 far from 17 one end of the drain electrode, the gate dielectric 160 successively with N+ types doped body region 142, p-type doped body region
140, third semiconductor layer 14 and the contact of the second semiconductor layer 13.When the groove gos deep into second semiconductor layer 13, institute
Gate dielectric 160 is stated also to contact with second semiconductor layer 13, when the groove gos deep into first semiconductor layer 12, institute
Gate dielectric 160 is stated also to contact with first semiconductor layer 12.
Wherein, when grid 16 is located in the groove, it is preferable that the p-type doped body region 140 and the third are partly led
The contact surface of body layer 14, it is misaligned with the surface of side of second semiconductor layer 13 far from first semiconductor layer 12,
And the distance between two faces should be small as far as possible.Preferably, the distance between two faces are less than or equal to 0.5um, to reduce
Electronics enters the path that Two-dimensional electron gas channel passes through from raceway groove.
In the present embodiment four, the source electrode 15 is located between the grid 16 and the drain electrode 17,15 He of the source electrode
The p-type doped body region 140 in the bar state, can play the role of electric field shielding between grid 16 and drain electrode 17,
And field distribution is optimized, the electric field strength at the grid 16 is effectively reduced, the reliability of the semiconductor devices 10 is enhanced.
Meanwhile the third semiconductor layer 14 n-type doping and the P+ type doped body region 141 can be realized during extension.
Based on above-described embodiment one to the semiconductor devices 10 described in example IV, the embodiment of the present invention gives this
The operation principle of semiconductor devices 10, it is specific as follows.
When 16 voltage of grid is zero, it is located at 140 surface of p-type doped body region of 160 lower section of the gate dielectric not transoid, then
10 raceway groove of semiconductor devices is not turned on.In other words, when being not pressurized on the grid 16, which is off shape
State.
When filling up enough positive voltages on grid 16,140 surface of the p-type doped body region hair of 160 lower section of the gate dielectric
Raw transoid, and electron accumulation layer is generated, form conducting channel.It is in the drain electrode 17 plus positive electric when the source electrode 15 is grounded
When pressure, under electric field action, electronics is from source electrode 15s, by conducting channel, the third semiconductor layer 14 of 16 lower section of grid, and
Two-dimensional electron gas along AlGaN/GaN heterojunction boundaries reaches drain electrode 17, specific as shown in Figure 1, wherein solid line table with the arrow
Show that electronics flows through path.
In short, in semiconductor devices 10 provided in an embodiment of the present invention, when 16 voltage of grid is zero, the grid 16 covers
140 surface of cover area p-type doped body region does not form raceway groove, and the semiconductor devices 10 turns off；And outside grid 16 plus enough just
Transoid occurs for pressure, the 16 overlay area doped body regions XiaPXing of grid, 140 surface, forms electron accumulation layer, the semiconductor devices 10
Conducting, thus constituting enhanced semiconductor devices 10 has higher threshold voltage, and can be by adjusting p-type doped body region
140 doping concentration has good consistency, can weigh in the threshold voltage of the wide range internal modulation semiconductor devices 10
Renaturation, thermal stability and high reliability.In addition, the drift region (as shown in phantom in Figure 1) that AlGaN/GaN heterojunction structures are formed can
For providing two-dimensional electron gas conductive path, drift zone resistance is effectively reduced, the main pressure resistance of device is born.
Further, as shown in figure 5, the present embodiment additionally provides a kind of manufacturing method of semiconductor devices 10, the side
Method includes：
Step S100 provides a substrate 11.
Step S200 forms the first semiconductor layer 12 in the side of the substrate 11.
Specifically, Fig. 8 (a) is please referred to, wherein the material of the substrate 11 is as previously mentioned, which is not described herein again.The lining
The forming method at bottom 11 may include CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapour
Phase Epitaxy, vapour phase epitaxy), (Metal-organic Chemical Vapor Deposition, metal have MOCVD
Machine compound chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor Deposition, low-pressure chemistry
Vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical gas
Mutually deposit), PLD (Pulsed Laser Deposition, pulsed laser deposition), atomic layer epitaxy, MBE (Molecular
Beam Epitaxy, molecular beam epitaxy), sputtering, evaporation etc., specifically, the present embodiment is not limited herein.
The method that the first semiconductor layer 12 is formed on the substrate 11 may include, but be not limited to the shape of the substrate 11
At method, in other words, the forming method of first semiconductor layer 12 can be with the forming method of the substrate 11 just as also may be used
It is different.
Step S300, side of first semiconductor layer 12 far from the substrate 11 formed the second semiconductor layer 13 with
And third semiconductor layer 14.Specifically, as shown in fig. 6, in the present embodiment, the step S300 includes following sub-step：
Sub-step S310 forms the second semiconductor layer 13 in side of first semiconductor layer 12 far from substrate 11.
Specifically, in the forming method of second semiconductor layer 13 and first semiconductor layer 12 or the substrate 11
Forming method it is similar, details are not described herein for the present embodiment.
Sub-step S320 performs etching second semiconductor layer 13 part for exposing first semiconductor layer 12
Region.
Wherein, Fig. 8 (b) and 8 (c) are please referred to, in the present embodiment, can be used and led with the substrate 11 or described the first half
The forming method of body layer 12 is similar, and forming described the second half in first semiconductor layer, 12 side far from the substrate 11 leads
Body layer 13, then with first semiconductor layer 12 be stop-layer, local etching is carried out to second semiconductor layer 13, is exposed
The subregion of first semiconductor layer 12.Wherein, etching depth is to cut through second semiconductor layer 13, and is etched to institute
Until stating the first semiconductor layer 12.Optionally, in sub-step S320, etching technics can be used, but be not limited to wet etching
Or dry etching etc..
Sub-step S330 forms third half in the region that first semiconductor layer 12 is not covered by the second semiconductor layer 13
Conductor layer 14.
In the present embodiment, third half is formed in the region that first semiconductor layer 12 is not covered by the second semiconductor layer 13
When conductor layer 14, the ionic type of injection is the ion that can form n-type doping well known to semiconductor technology personnel in GaN,
The present embodiment is not particularly limited herein.
It should be noted that the generation type of the third semiconductor layer 14 provided in this implementation embodiment is only a kind of specific embodiment party
Formula, for example, can be directly in the area deposition semiconductor material not covered by the second semiconductor layer 13 in first semiconductor layer 12
Material forms the third semiconductor layer 14.Alternatively, do not performed etching to second semiconductor layer 13, but directly this second
A side surface deposited semiconductor material of the semiconductor layer 13 far from first semiconductor layer 12 forms the third semiconductor layer
14.Specifically, the present embodiment is not limited.
Step S400 makes p-type doped body region 140 based on the third semiconductor layer 14, is based on the p-type doped body region
140 make N+ types doped body region 142 and P+ type doped body region 141.
Specifically, it as shown in Fig. 8 (d), makes p-type doped body region 140 in the third semiconductor layer 14 and is based on institute
It is real by way of ion implanting to state p-type doped body region 140 and make N+ types doped body region 142 and P+ type doped body region 141
It is existing.Wherein, the ionic type of injection can be that can form p-type doping well known to the semiconductor technologies personnel such as Mg in GaN
The ion of ion, the ion of P+ type doping and the doping of N+ types, to form p-type doped body region 140, N+ types doped body region 142
With P+ type doped body region 141.
Step S500 makes source electrode 15 and grid 16 based on the third semiconductor layer 14, makes the source electrode 15 and the N+
141 Ohmic contact of type doped body region 142 and P+ type doped body region makes drain electrode 17 based on second semiconductor layer 13.
Wherein, it by taking groove profile grid shown in Fig. 4 as an example, is wrapped in the step of third semiconductor layer 14 makes grid 16
It includes：
Sub-step S510 performs etching the third semiconductor layer 14, forms groove.
Sub-step S520 fills gate dielectric 160 in the groove.
Sub-step S530 fills 16 material of grid formation grid 16 in the groove.
It should be understood that the gate dielectric 160 is filled in the inner surface of the groove, the grid 16 can pass through the grid
Medium 160 with it is described successively with N+ types doped body region 142, p-type doped body region 140, third semiconductor layer 14 and the second half
Conductor layer 13 contacts.In addition, the source electrode 15 and 141 Ohmic contact of N+ types doped body region 142 and P+ type doped body region.
In conclusion the present invention provides a kind of semiconductor devices 10 and preparation method thereof, wherein by the semiconductor device
The ingehious design of part 10 can be controlled the opening and closing of the semiconductor devices 10 by grid 16, realize and enhanced partly lead
Body device 10.Meanwhile, it is capable to the threshold voltage of enhanced semiconductor devices 10 is effectively improved, and the threshold voltage can be larger
Range internal modulation.
Further, the semiconductor devices 10 that the present embodiment provides is simple in structure, easily manufactured, has higher uniformity
And stability, and the semiconductor devices 10 uses heterojunction structure as drift region, resistance to pressure is strong.
Obviously, those skilled in the art should be understood that the function of the above-mentioned embodiment of the present invention can use general meter
Device is calculated to realize, they can be concentrated on a single computing device, or be distributed in net constituted by multiple computing devices
On network, optionally, they can be realized with the executable existing program code of computing device or algorithm, it is thus possible to by it
Store and be performed by computing device in the storage device, either they are fabricated to each integrated circuit modules or
By in them multiple modules or step be fabricated to single integrated circuit module and realize.In this way, functions implementing the present invention are not
Any specific hardware and software is limited to combine.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any made by repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (14)
1. a kind of semiconductor devices, which is characterized in that including：
Substrate；
The first semiconductor layer positioned at the one side of substrate；
Positioned at second semiconductor layer and third semiconductor layer of first semiconductor layer far from the one side of substrate；
The drain electrode made based on second semiconductor layer；
The source electrode and grid made based on the third semiconductor layer；Wherein,
The third semiconductor layer is n-type doping, and the third semiconductor layer includes p-type doped body region, the p-type doped body region
Including N+ types doped body region and P+ type doped body region, the source electrode is contacted with the N+ types doped body region and P+ type doped body region.
2. semiconductor devices according to claim 1, which is characterized in that N+ types doped body region is located at the p-type and mixes
Close to the side of the grid in the areas Za Ti, the P+ type doped body region is located in the p-type doped body region far from the grid
Side.
3. semiconductor devices according to claim 1, which is characterized in that gate dielectric is formed based on the fabrication,
The gate dielectric is contacted with N+ types doped body region, the p-type doped body region and the third semiconductor layer respectively.
4. semiconductor devices according to claim 1, which is characterized in that second semiconductor layer and the third are partly led
Body layer is made in first semiconductor layer far from the one side of substrate, and is covered each by first semiconductor layer far from institute
State the part surface of one side of substrate.
5. semiconductor devices according to claim 1, which is characterized in that second semiconductor layer is made in described first
Semiconductor layer covers the part surface of the first semiconductor layer side far from one side of substrate, and the third semiconductor layer is logical
It crosses and ion implanting is not carried out by the part that the second semiconductor layer covers to first semiconductor layer and is formed.
6. semiconductor devices according to claim 1, which is characterized in that the third semiconductor layer is located at described the second half
Side of the conductor layer far from first semiconductor layer.
7. according to the semiconductor devices described in claim 1-6 any one, which is characterized in that the third semiconductor layer opens up
Fluted, the grid is located in the groove, and gate dielectric is filled between the grid and the groove.
8. according to the semiconductor devices described in claim 1-6 any one, which is characterized in that the grid is located at the third
One side of the semiconductor layer far from first semiconductor layer between the grid and the third semiconductor layer there is grid to be situated between
Matter.
9. according to the semiconductor devices described in claim 1-6 any one, which is characterized in that mix the p-type doped body region
Miscellaneous concentration is modulated, and the threshold voltage of the semiconductor devices is modulated.
10. semiconductor devices according to claim 8, which is characterized in that the p-type doped body region is close to the grid
There are gaps between the edge close to the grid side for the edge of side and the third semiconductor layer.
11. a kind of production method of semiconductor devices, which is characterized in that the method includes：
One substrate is provided；
The first semiconductor layer is formed in the side of the substrate；
The second semiconductor layer and third semiconductor layer are formed in side of first semiconductor layer far from the substrate；
Make p-type doped body region based on the third semiconductor layer, based on the p-type doped body region make N+ types doped body region and
P+ type doped body region；And
Source electrode and grid are made based on the third semiconductor layer, the source electrode is made to be adulterated with N+ types doped body region and P+ type
Body area Ohmic contact makes drain electrode based on second semiconductor layer.
12. the production method of semiconductor devices according to claim 11, which is characterized in that in first semiconductor layer
Side far from the substrate forms the second semiconductor layer and third semiconductor layer, the step of include：
The second semiconductor layer is formed in side of first semiconductor layer far from substrate；
The subregion for exposing first semiconductor layer is performed etching to second semiconductor layer；
Third semiconductor layer is formed in region of first semiconductor layer not by the covering of the second semiconductor layer.
13. the production method of semiconductor devices according to claim 11, which is characterized in that in first semiconductor layer
Do not include by the step of region formation third semiconductor layer of the second semiconductor layer covering：
The third half is not formed by the area deposition semi-conducting material that the second semiconductor layer covers in first semiconductor layer
Conductor layer；Or
Part to first semiconductor layer not by the covering of the second semiconductor layer carries out ion implanting, forms the third and partly leads
Body layer.
14. the production method of the semiconductor devices according to claim 11-13 any one, which is characterized in that the grid
Pole makes to be formed by following steps：
The third semiconductor layer is performed etching, groove is formed；
Gate dielectric is filled in the groove；
Grid material is filled in the groove forms grid.
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