CN1937257A - High-voltage SensorFET device - Google Patents

Abstract

A high-voltage SensorFET device belongs to the fields of semiconductor power device technology, power device sensing technology and power integrated circuit technology. Including high voltage SensorFET devices with lateral JFET structure and vertical JFET structure. A power SensorFET device with a lateral JFET structure forms a JFET channel by sandwiching an n (or p) well (or epitaxial layer) 8 between a p (or n) gate region 2 and a p (or n) substrate 6, and utilizes RESURF The principle is to increase the breakdown voltage of the device. A power SensorFET device with a vertical JFET structure is implemented by sandwiching n (or p) wells (or epitaxial layers) 8 between different p (or n) gate regions 2 and p (or n) gate regions 2 and p (or n) The n (or p) well (or epitaxial layer) 8 is sandwiched between the substrates 6 to form a JFET channel, and the RESURF principle is used to increase the breakdown voltage of the device. The invention has good IV characteristics of JFET while satisfying high withstand voltage, has the functions of current sampling and providing charging current for low-voltage integrated circuits, and is easy to integrate. It can be applied in fields such as power management, motor drive and power control.

Description

High Voltage SensorFET Devices

technical field

The invention belongs to the field of semiconductor power device technology, power device sensing technology and power integrated circuit technology.

Background technique

In recent years, with the development of power electronics technology, smart power integrated circuits (SPICs) have been more and more widely used. SPIC is the integration of logic control circuits and power devices up to modulation mode. One of its benefits is that it is designed with a protection circuit for high-voltage circuits and power devices, which significantly improves the circuit and devices under high voltage or/and high current conditions. reliability. The realization of the protection circuit of the high-voltage circuit and the power device involves the sampling problem of the signal. At present, in the power integrated circuit, there are mainly two ways to sample the signal of the high-voltage circuit, namely, voltage sampling and current sampling.

In power integrated circuits, a commonly used voltage sampling method is to connect a series resistance loop on a high-voltage circuit bus. The upper resistor connected to the high voltage has a larger resistance value, and the lower resistor connected to the ground has a smaller resistance value, so that sampling can obtain signals that can be processed by the low-voltage control circuit from the high-voltage bus. However, the cost of this voltage sampling method is relatively high, and there is a withstand voltage limit especially when a resistor with high precision is used. For this reason, scholars have proposed measures of various voltage sampling methods. Literature (1), T.Terashima, M.Yoshizawa, M.Fukunaga, et.al, Structure of 600V IC and A new voltage sensing device (structure of 600V IC and new voltage sensing device), ISPSD, 1993: 224-229, The structure is shown in Figure 1. The structural device adopts RESURF technology to optimize the electric field in the drift region, and the detection voltage area is at the inner edge of the depletion layer of the lateral device, and the connection of the constant current source is used to avoid the breakdown of the voltage circuit. However, the constant current source will inject carriers in the depletion region, which affects the electric field distribution of the device, thus directly affecting many characteristics of the device; secondly, the position of the voltage sensor is extremely sensitive to the main junction voltage. Since an N ⁺ detection ring or P ⁺ detection ring is introduced at the inner edge of the depletion layer, it is easy to destroy the RESURF condition satisfied by its drift region, which will reduce the breakdown voltage of the device. Document (2), HAN Lei, YE Xing-ning, CHEN Xing-bi, A Novel High-Voltage Detector Integrated into SPIC by Using FFLR Voltage detector), CHINESE JOURNAL OFSEMICONDUCTORS, 2001, 22(10): 1250-1254, using the voltage division principle of the field limiting ring to realize the voltage sampling of the high voltage circuit, the structure is shown in Figure 2. The voltage between adjacent rings of the structure does not change with the voltage of the main junction, and there is a one-to-one correspondence between the voltage on the field limiting ring and the voltage on the main junction. Therefore, the high voltage of the main junction can be gradually divided by multiple field-limiting rings, and one of the outermost rings is designed as a high-voltage voltage detector to sample a voltage signal that can be processed by the low-voltage control circuit. However, when the main junction voltage increases, this structure needs to increase the number of field-limiting rings and the spacing of the adjustment rings, resulting in an increase in layout area. In addition, in the silicon oxidation process of the planar process, there will inevitably exist a certain amount of mobile charges and fixed charges at the interface between the oxide layer and the silicon, and these interface charges will obviously affect the electric field distribution of the field-limiting ring system, thus Good voltage sampling performance cannot be achieved. Document (3), J.Petruzzello, T.Letavic, B.Dufort, SOI HighVoltage Power FET with an Internal Voltage (Current) Sensing Terminal (SOI High Voltage Power FET with an Internal Voltage (Current) Sampling Terminal), ISPSD, 2003: 224-227, the structure is shown in Figure 3. In this structure, the field plate on the field oxygen (FOX) is used to sample the drain terminal voltage, and the field plate voltage and the drain terminal voltage are realized through the field oxygen capacitor (C _FP ) and an external capacitor C _EXT (connected between the field plate and the ground). One-to-one correspondence, the partial pressure formula is as follows: $\frac{V_{\mathrm{FP}}}{V_{\mathrm{DS}}}=\frac{C_{\mathrm{FP}}\left(V_{\mathrm{DS}}\right)}{C_{\mathrm{FP}}\left(V_{\mathrm{DS}}\right)+C_{\mathrm{EXT}}},$ Among them, V _FP is the field plate voltage, V _DS is the drain terminal voltage, and C _FP (V _DS ) indicates that the field oxygen capacitance is a function of the drain terminal voltage. However, this structure has two disadvantages: one is that the field oxygen capacitance is a function of the drain voltage, which decreases with the increase of the drain voltage, so it cannot reflect the drain voltage well; the other is the gap between the oxide layer and the silicon interface. The movable charges and fixed charges between them make this structure unable to achieve good voltage sampling performance. To sum up, the voltage sampling method either cannot accurately reflect the drain terminal voltage, or the breakdown voltage of the device structure is low.

The current sampling method of power devices often uses small resistors or ammeters in series directly, but this will cause certain losses and other unfavorable factors, or use the method of coupling small inductance during AC. The above methods either have large losses or are only for AC conditions. And need external components. In power devices, the parallel structure of primary cells is mostly used, and for lateral devices, multiple units are also connected in parallel. Therefore, only one or a smaller unit is selected, and its current has a relatively strict proportional relationship with the total current, so as to realize the current sampling of the power device. Literature (4), Chong-Man Yun, Doo-Young Kim, Yeam-Ik Choi, et.al, AMonolithic Current Limiting Power MOSFET (Monolithic Current Limiting Power MOSFET), IEEE, 1995: 71-74, Structure As shown in Figure 4. This structure uses VDMOS to be composed of many original cells, and the source of some of the original cells is drawn separately, and the current flowing on it can reflect the total current. Since the current is distributed completely according to the number of primitive cells, the sampling current is obtained by setting the ratio of the number of primitive cells. However, the sensor device in this current sampling mode requires an external resistor for current sampling, and the external resistor will have a bad influence on the characteristics of the entire power device (such as reduced withstand voltage, uneven current distribution, etc.).

Contents of the invention

The object of the present invention is to provide a high-voltage SensorFET device with a JFET structure, which has good IV characteristics of JFET while meeting high withstand voltage. The device has the function of current sampling and charging current for low-voltage integrated circuits, and is easy to integrate.

The present invention proposes a high-voltage SensorFET device in the current sampling mode shown in Figure 5. This structural device can avoid voltage sampling and the shortcomings of the previous current mode. At the same time, the device with this sampling structure can not only realize current sampling and control well. function, and self-supply of working energy for power integrated circuits can also be performed through the sampling device. As shown in Figure 6. When the switching power supply is working normally, A4=1, the power tube is turned on, the drain voltage of the power tube is lower than ten volts, and the SensorFET works in the linear region with a small DC resistance. At the same time, the MN19 tube is turned on, and the sampling power tube Conduct current into the low-voltage circuit and compare it with the current limit to control the conduction duty cycle of the power transistor. At this time, the role of the SensorFET is to sample the conduction current of the power tube into the low-voltage circuit for sampling and control.

When A4=0, the power tube is turned off, and the drain end of the power tube usually rises to a voltage value of several hundred volts at this time. At this time, it does not need too much current to flow through the SensorFET device, only a small current is needed to provide current to the internal circuit of the chip and charge the bypass capacitor C (SensorFET controls the internal circuit of the power supply by charging the bypass capacitor C provide a stable low voltage power supply). The high drain voltage of hundreds of volts but only a small charging current is realized by the SensorFET. At this time, the SensorFET works in the saturation region and has a large DC on-resistance, so a small charging current will be generated for the RC loop.

This structure is implemented in the form of a normally-on high-voltage JFET, and its specific structure is shown in Figure 7 (Figure 7 is the specific form of the structure included in the dotted box in Figure 5). In addition, for the SensorFET device, the present invention also provides a structure as shown in FIG. 8 . As shown in FIG. 5 , this structure uses lateral devices to connect one or more units in parallel, and one or more units are used for current sampling. In the structure of the present invention, when the main power tube is working normally, its drain terminal voltage is relatively low, and the JFET channel of the SensorFET is not pinched, so the SensorFET can sample the current in the main power tube; when the power tube is turned off, At this time, the drain terminal voltage of the device is relatively high (usually about 600V), and the SensorFET can directly charge the external capacitor serving as the power supply of the low-voltage control circuit, so that the external capacitor can provide power for the low-voltage control circuit after the power tube is turned on; at the same time, the SensorFET The JFET channel has been pinched off, that is, it is equivalent to a resistor with a high resistance value. Through the voltage division function of the SensorFET, it can ensure a good connection between the low-voltage circuit and the high-voltage circuit (wherein, the sampling function of the SensorFET works when the power tube is working. , at this time its charging function stops; when the power tube is turned off, the charging function of the SensorFET works, and the sampling function stops). In terms of withstand voltage, RESURF technology is used to realize the high withstand voltage characteristics of the SensorFET to ensure that the SensorFET can work normally when the power tube is turned off and the drain terminal voltage is high.

Detailed technical scheme of the present invention is as follows:

1. High-voltage SensorFET device with lateral JFET structure

The present invention provides a high-voltage SensorFET device with a lateral JFET structure, as shown in FIG. 7 , including an n ⁺ (or p ⁺ ) source region 5, an n ⁺ (or p ⁺ ) drain region 7, and a p (or n) gate region 2 , n (or p) well 8 and p (or n) substrate 6; characterized in that, p (or n) gate region 2 is located in n ⁺ (or p ⁺ ) source region 5 and n ⁺ (or P ⁺ ) drain In the n (or p) well 8 between the regions 7; the JFET channel is formed by sandwiching the n (or p) well 8 between the p (or n) gate region 2 and the p (or n) substrate 6, so as to The IV characteristics of JFET are provided; a lateral diode is formed by p (or n) gate region 2 and n (or p) well 8, and a vertical diode is formed by p (or n) substrate 6 and n (or p) well 8, The horizontal diode and the vertical diode form a RESURF structure, so as to improve the breakdown voltage of the device.

In the above-mentioned high-voltage SensorFET device with a lateral JFET structure, the n (or p) well (8) can also be replaced by an n (or p) epitaxial layer.

It should be noted:

In order to obtain a high breakdown voltage in the RESURF structure, it is required that the n (or p) well (or epitaxial layer) 8 be completely depleted. Full depletion should occur before the avalanche breakdown of the lateral p (or n) gate region 2/n (or p) well (or epitaxial layer) 8 junction.

2. High-voltage SensorFET device with vertical JFET structure

The present invention also provides ^{a high} -voltage SensorFET ^device with a vertical JFET ^structure , as shown in FIG. or n) gate region 2, an n (or p) well 8 and a p (or n) substrate 6; it is characterized in that two p (or n) gate regions 2 are parallel to each other, and a p (or n) gate The region 2 is located in the n ⁽ or p) well 8 between the n + (or p ⁺ ) source region 5 and an n ⁺ (or p ⁺ ) drain region 7, and the other p (or n) gate region 2 is located in the n ⁺ (or p ⁺ ) in the n (or p) well 8 between the source region 5 and another n ⁺ (or p ⁺ ) drain region 7; The n (or p) well 8 is sandwiched between the p) well 8 and two p (or n) gate regions 2 and the p (or n) substrate 6 to form a JFET channel, thereby providing the IV characteristics of the JFET; by Two p (or n) gate regions 2 form two lateral diodes with n (or p) well 8 respectively, and a vertical diode is formed by p (or n) substrate 6 and n (or p) well 8, and the two A horizontal diode and a vertical diode form a RESURF structure to increase the breakdown voltage of the device. It is characterized in that the drain, gate and source are all on the surface of the device, which is easy to integrate with other devices.

In the above-mentioned high-voltage SensorFET device with a vertical JFET structure, the n (or p) well (8) can also be replaced by an n (or p) epitaxial layer.

It should be noted:

In order to obtain a high breakdown voltage in the RESURF structure, it is required that the n (or p) well (or epitaxial layer) 8 be completely depleted. Full depletion should occur before the avalanche breakdown of the lateral p (or n) gate region 2/n (or p) well (or epitaxial layer) 8 junction.

Working principle of the present invention:

1. High-voltage SensorFET device with lateral JFET structure

The high-voltage SensorFET device with a lateral JFET structure provided by the present invention can greatly increase the breakdown voltage of the device (according to the design to meet the required voltage requirement) while maintaining the good IV characteristics of the JFET. Here, a high-voltage SensorFET device with a lateral JFET structure is taken as an example to illustrate the working principle of this structure in the present invention.

As shown in Figure 7, a high-voltage SensorFET device with a lateral JFET structure has an n (or p) well (or epitaxial layer) 8 between its p (or n) gate region 2 and p (or n) substrate 6 to form a JFET Channel, when voltage is applied to the drain, and the gate and source are grounded, an electric field from the drain to the source is formed in the JFET channel, and the many electrons in the semiconductor generate a channel drift current under the action of the electric field. When the drain voltage increases When, due to the p (or n) gate region 2/n (or p) well (or epitaxial layer) 8 junction depletion region widened to n (or p) well (or epitaxial layer) 8 and p (or n) lining The depletion region of the bottom 6/n (or p) well (or epitaxial layer) 8 junction widens to the n (or p) well (or epitaxial layer) 8, and finally these two depletion regions will meet in the channel, making the channel The road is broken. With the increase of the drain voltage, the device will be in the saturated working area. Due to the existence of the channel modulation effect, the drain current in the saturated area will increase slightly with the increase of the drain voltage. In order to better meet the requirements of the SensorFET in the switching power supply Application requirements (that is, when the drain terminal is high voltage, the SensorFET is equivalent to a large resistance resistor), the channel of the JFET should be made as long as possible to reduce the channel modulation effect, but this involves the problem of increased on-resistance. Therefore, the selection of the channel length should be considered according to the situation. When the drain terminal voltage reaches a certain value and exceeds the breakdown voltage of the device, the drain current will increase sharply.

In order to meet the requirements of SensorFET applied under high voltage, RESURF technology is adopted. The RESURF structure consists of a lateral diode p (or n) gate region 2/n (or p) well (or epitaxial layer) 8 and a vertical diode p (or n ) substrate 6/n (or p) well (or epitaxial layer) 8, this vertical diode provides a space charge depletion region that maintains a high withstand voltage. The basic principle of the RESURF structure is determined by three parameters: substrate impurity concentration P _sub , well (assumed to be uniformly doped) impurity average concentration N _well and well drift region junction depth X _jwell . Therefore, the integral charge in the well is Q _n =N _well ×X _jnwell , when Q _n is within a certain range, the depletion region of the vertical diode in the drift region of the n (or p) well (or epitaxial layer) The depletion region of the diode in the drift region of the n (or p) well (or epitaxial layer) 8 is connected such that the lateral diode depletion region width is comparable to that of the lateral diode without the p (or n) substrate 6 than a substantial increase. Therefore, the lateral electric field at the lateral junction of the p (or n) gate region 2/n (or p) well (or epitaxial layer) 8 is significantly lower than that of the one-dimensional diode, thereby increasing the breakdown voltage of the device. It is required that the drift region in the n (or p) well (or epitaxial layer) 8 be completely depleted before the lateral electric field reaches the critical breakdown electric field, at which point the RESURF structure obtains the maximum breakdown voltage. As shown in Figure 7, the vertical depletion region of the drift region in the n (or p) well (or epitaxial layer) 8 is formed by the p (or n) substrate 6/n (or p) well (or epitaxial layer) 8 This is provided by a knot, so it is called the Single RESURF structure.

2. High-voltage SensorFET device with vertical JFET structure

The working principle of the high-voltage SensorFET device with the vertical JFET structure is the same as that of the above-mentioned high-voltage SensorFET device with the lateral JFET structure. Compared with the high-voltage SensorFET device with lateral JFET structure, this structure differs in that the JFET channel is vertical.

In summary, the high-voltage SensorFET device of the lateral JFET structure provided by the present invention greatly improves the breakdown voltage of the device while realizing the IV characteristics of the JFET well; it also provides a vertical JFET structure that is easy to implement and integrate. High voltage SensorFET devices. Taking the P-type substrate as an example, through the simulation of MEDICI and TSUPREM4 simulator, the results are as follows:

① For a high-voltage SensorFET with a lateral JFET structure, when the concentration of the p-substrate 6 is 1.5×10 ¹⁴ /cm ³ , the concentration of the n-well (or epitaxial layer) 8 is 1.25×10 ¹⁵ /cm ³ , and the concentration of the n-well (or epitaxial layer) 8 The junction depth (or thickness) is 8 μm, the concentration of p gate region 2 is 2×10 ¹⁷ /cm ³ , the junction depth of p gate region 2 is 1 μm, and the concentration of n ⁺ drain region 7 and n ⁺ source region 5 is 6×10 ¹⁹ /cm ³ , when the junction depth of n ⁺ drain region 7 and n ⁺ source region 5 is 0.5 μm, its breakdown voltage is 680V; when gate 3 is grounded and source 4 is grounded, its IV characteristics are shown in Figure 9.

②For a high-voltage SensorFET with a vertical JFET structure, when the concentration of the p-substrate 6 is 1.5×10 ¹⁴ /cm ³ , the concentration of the n-well (or epitaxial layer) 8 is 5×10 ¹⁴ /cm ³ , and the concentration of the n-well (or epitaxial layer) 8 The junction depth (or thickness) is 30 μm, the concentration of p gate region 2 is 8×10 ¹⁶ /cm ³ , the junction depth of p gate region 2 is 25 μm, and the concentration of n ⁺ drain region 7 and n ⁺ source region 5 is 6×10 ¹⁹ /cm ³ , when the junction depth of n ⁺ drain region 7 and n ⁺ source region 5 is 0.5 μm, its breakdown voltage is 890V; when gate 3 is grounded and source 4 is grounded, its IV characteristics are shown in Fig. 10 .

It can be seen from Fig. 9 and Fig. 10 that the high-voltage SensorFET with the lateral JFET structure and the high-voltage SensorFET with the vertical JFET structure have good IV characteristics of JFET while satisfying high withstand voltage.

Description of drawings

Figure 1 is a schematic diagram of the structure of the existing 600V IC and the new voltage sensing device.

Fig. 2 is a schematic structural diagram of an existing high-voltage voltage detector that can be integrated in an SPIC realized by using a floating field-limiting loop.

Fig. 3 is a structural schematic diagram of an existing SOI high-voltage power field effect transistor with a voltage (current) sampling terminal inside.

FIG. 4 is a schematic structural diagram of an existing monolithic power MOSFET with a current limiting function.

Fig. 5 is a schematic structural diagram of a power MOSFET with sampling and charging functions according to the present invention.

FIG. 6 is a schematic diagram of an application circuit for current sampling and self-power supply of the high-voltage SensorFET of the present invention.

Fig. 7 is a schematic structural diagram of a high-voltage SensorFET device with a lateral JFET structure of the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, 7 is n ⁺ (or p ⁺ ) drain region, 8 is n (or p) well or n (or p) epitaxial layer.

Fig. 8 is a schematic structural diagram of a high-voltage SensorFET device with a vertical JFET structure of the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, 7 is n ⁺ (or p ⁺ ) drain region, 8 is n (or p) well or n (or p) epitaxial layer.

Fig. 9 is a schematic diagram of the IV characteristic curve of the high-voltage SensorFET device with the lateral JFET structure shown in Fig. 7,

The gate is grounded and the source is grounded.

Fig. 10 is a schematic diagram of the IV characteristic curve of the high-voltage SensorFET device with the vertical JFET structure shown in Fig. 8,

The gate is grounded and the source is grounded.

Fig. 11 is a schematic diagram of the structure of a high-voltage SensorFET device having a lateral JFET structure and a p (or n) field-falling layer of the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, 7 is n ⁺ (or p ⁺ ) drain region, 8 is n (or p) well or n (or p) epitaxial layer, and 10 is p (or n) drop field layer.

12 is a schematic diagram of the structure of a high-voltage SensorFET device having a lateral JFET structure and p (or n) field-falling layers of different doped regions according to the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or P ⁺ ) source area, 6 is the p (or n) substrate, and 7 is the n ⁺ (or p ⁺ ) drain region, 8 is n (or p) well or n (or p) epitaxial layer, 10 is p (or n) field drop layer of two different doping regions.

Fig. 13 is a schematic diagram of the structure of a high-voltage SensorFET device having a lateral JFET structure and a p (or n) type multi-ring drop field layer of the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or P ⁺ ) source area, 6 is the p (or n) substrate, and 7 is the n ⁺ (or p ⁺ ) drain region, 8 is an n (or p) well or n (or p) epitaxial layer, and 10 is a p (or n) type multi-ring drop field layer.

Fig. 14 is a schematic structural view of a high-voltage SensorFET device having a vertical JFET structure and a p (or n) field drop layer of the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, 7 is n ⁺ (or p ⁺ ) drain region, 8 is n (or p) well or n (or p) epitaxial layer, and 10 is p (or n) drop field layer.

15 is a schematic diagram of the structure of a high-voltage SensorFET device having a vertical JFET structure and p (or n) field-falling layers of different doped regions according to the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, 7 is the n ⁺ (or P ⁺ ) drain region, 8 is the n (or p) well or n (or p) epitaxial layer, and 10 is the p (or n) drop field layer of two different doped regions.

Fig. 16 is a schematic diagram of the structure of a high-voltage SensorFET device with a vertical JFET structure and a p (or n) type multi-ring drop field layer of the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, and 7 is the n ⁺ (or p ⁺ ) drain region, 8 is an n (or p) well or n (or p) epitaxial layer, and 10 is a p (or n) type multi-ring drop field layer.

Fig. 17 is a schematic structural diagram of a high-voltage SensorFET device with a vertical JFET structure and multi-point sampling according to the present invention,

Among them, 1 is the drain, 2 is the p (or n) gate area, 3 is the gate, 4 is the source, 5 is the n ⁺ (or p ⁺ ) source area, 6 is the p (or n) substrate, and 7 is the n ⁺ (or P ⁺ ) drain region, 8 is an n (or p) well or an n (or p) epitaxial layer.

Fig. 18 is a schematic diagram of the IV characteristic curve with a lateral JFET structure and a p (or n) type multi-ring drop field layer shown in Fig. 10

The gate is grounded, the source is grounded, and the substrate is P-type. The concentration of p substrate 6 is 1.5×10 ¹⁴ /cm ³ , the concentration of n well (or epitaxial layer) 8 is 2×10 ¹⁵ /cm ³ , the junction depth (or thickness) of n well (or epitaxial layer) 8 is 8 μm, p The concentration of the gate region 2 is 2×10 ¹⁷ /cm ³ , the junction depth of the p gate region 2 is 1 μm, the concentration of the n ⁺ drain region 7 and n ⁺ source region 5 is 6×10 ¹⁹ /cm ³ , and the p drop field layer 10 When the concentration of 2×10 ¹⁷ /cm ³ , the junction depth of p drop field layer 10 is 0.5 μm, and the junction depth of n ⁺ drain region 7 and n ⁺ source region 5 is 0.5 μm, the breakdown voltage is 854V. At the same time, the structure also has good IV characteristics of JFET.

Detailed ways

By adopting the high-voltage SensorFET device structure with a lateral JFET structure and the high-voltage SensorFET device structure with a vertical JFET structure of the present invention, a high-voltage sampling device with good IV characteristics of JFET and high withstand voltage can be obtained. It can be widely used in switching power supplies and motor drives with various current sampling methods. And this type of structure is compatible with power integrated circuits. With the development of semiconductor device technology, more high-voltage JFET devices with high voltage, low on-resistance and good IV characteristics of JFET can be manufactured by adopting the present invention.

In specific implementation, for a high-voltage SensorFET with a lateral JFET structure, the n (or p) layer is first epitaxially grown on the p (or n) substrate or the n (or p) well is implanted and the junction is pushed, and then the p (or p) layer is implanted n) gate region and push the junction, and then implant n ⁺ (or P ⁺ ) drain and source regions.

For a high-voltage SensorFET with a vertical JFET structure, the n (or p) layer is epitaxially grown on the p (or n) substrate or the n (or p) well is implanted and the junction is pushed. There are many ways to realize the gate region, such as Implant the p (or n) gate region directly by photolithography, or form a p (or n) gate region by grooving and filling, and then implant n ⁺ (or P ⁺ ) drain and source regions.

For a high-voltage SensorFET with a lateral JFET structure and a p (or n) field drop layer, the n (or p) layer is epitaxially grown on the p (or n) substrate or the n (or p) well is implanted and the junction is pushed. Then implant the p (or n) gate region and push the junction, then implant the p (or n) drop field layer, and then implant the n ⁺ (or p ⁺ ) drain and source regions. Or the gate region and the falling field layer are formed at the same time.

During the implementation process, according to the specific situation, certain flexible designs can be carried out under the condition that the basic structure remains unchanged, such as:

A uniform p (or n) field drop layer 10 can be injected into the surface of the drift region between the drain region 7 and the gate region 2 in FIG. 7 , as shown in FIG. 11 . The concentration of the above-mentioned p (or n) field-falling layer can be uniform, or the field-falling layer adopts lateral variable doping (LVD) technology, and its concentration gradually decreases from the side of the source end to the side of the drain end. Or divide the P drop field layer into a plurality of differently doped regions, use high doping in the region near the source end, and low doping in the region near the drain end, as shown in Figure 12; the above-mentioned p (or n) drop field layer It can be a single drop field layer structure, or a p (or n) type multi-ring drop field layer structure can be made on the surface at the same time, as shown in FIG. 13 .

A uniform p (or n) field drop layer 10 can be injected into the surface of the drift region between the drain region 7 and the gate region 2 in FIG. 8 , as shown in FIG. 14 . The concentration of the above-mentioned p (or n) field-falling layer can be uniform, or the field-falling layer adopts lateral variable doping (LVD) technology, and its concentration gradually decreases from the side of the source end to the side of the drain end. Or divide the P drop field layer into a plurality of differently doped regions, use high doping in the region near the source end, and low doping in the region near the drain end, as shown in Figure 15; the above-mentioned p (or n) drop field layer It can be a single drop field layer structure, or multiple p (or n) drop field layer structures can be made on the surface at the same time as shown in Figure 16; the vertical JFET channel can be a single vertical JFET channel structure, or can be made at the same time The structure of multiple vertical JFET channels is shown in Figure 17 to realize multi-point current sampling.

Claims (11)

1, a kind of high-voltage SensorFET device with horizontal JFET structure comprises n ⁺(or p ⁺) source region (5), n ⁺(or p ⁺) drain region (7), p (or n) grid region (2), n (or p) trap (8) and p (or n) substrate (6); It is characterized in that p (or n) grid region (2) is positioned at n ⁺(or p ⁺) source region (5) and n ⁺(or p ⁺) in n (or p) trap (8) between drain region (7); Form the JFET raceway groove by pressing from both sides n (or p) trap (8) between p (or n) grid region (2) and p (or n) substrate (6), provide the IV characteristic of JFET with this; Constitute a transverse diode by p (or n) grid region (2) and n (or p) trap (8), constitute a vertical diode by p (or n) substrate (6) and n (or p) trap (8), described transverse diode and vertical diode constitute the RESURF structure, improve the puncture voltage of device with this.

2, a kind of high-voltage SensorFET device with horizontal JFET structure according to claim 1 is characterized in that, described n (or p) trap (8) replaces with n (or p) epitaxial loayer.

According to claim 1,2 described a kind of high-voltage SensorFET devices, it is characterized in that 3, comprise that also a layer (10) falls in a p (or n), described p (or n) falls a layer (10) and is positioned at p (or n) grid region (2) and n with horizontal JFET structure ⁺(or p ⁺) in n (or p) trap (8) between drain region (7).

4, a kind of high-voltage SensorFET device with horizontal JFET structure according to claim 3 is characterized in that, it is that a layer falls in the p (or n) of two differently doped regions that layer (10) falls in described p (or n).

5, a kind of high-voltage SensorFET device with horizontal JFET structure according to claim 3 is characterized in that, it is that a layer falls in the many rings of p (or n) type that a layer (10) falls in described p (or n).

6, a kind of high-voltage SensorFET device with vertical JFET structure comprises a n ⁺(or p ⁺) source region (5), two n ⁺(or p ⁺) drain region (7), two p (or n) grid regions (2), a n (or p) trap (8) and a p (or n) substrate (6); It is characterized in that two p (or n) grid regions (2) are parallel to each other, a p (or n) grid region (2) is positioned at n ⁺(or p ⁺) source region (5) and a n ⁺(or p ⁺) in n (or p) trap (8) between drain region (7), another p (or n) grid region (2) is positioned at n ⁺(or p ⁺) source region (5) and another n ⁺(or p ⁺) in n (or p) trap (8) between drain region (7); By pressing from both sides n (or p) trap (8) and two p (or n) grid regions (2) between two p (or n) grid regions (2) respectively and press from both sides n (or p) trap (8) between p (or n) substrate (6) and form the JFET raceway groove, provide the IV characteristic of JFET with this; By two p (or n) grid regions (2) respectively and n (or p) trap (8) constitute two transverse diodes, constitute a vertical diode by p (or n) substrate (6) and n (or p) trap (8), described two transverse diodes and a vertical diode constitute the RESURF structure, improve the puncture voltage of device with this.

7, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 5 is characterized in that, described n (or p) trap (8) replaces with n (or p) epitaxial loayer.

According to claim 5,6 described a kind of high-voltage SensorFET devices, it is characterized in that 8, comprise that also a layer (10) falls in two p (or n), one of them p (or n) falls a layer (10) and is positioned at n with vertical JFET structure ⁺(or p ⁺) p (or n) grid region (2) and the n of source region (5) one sides ⁺(or p ⁺) in n (or p) trap (8) between drain region (7), another p (or n) falls a layer (10) and is positioned at n ⁺(or p ⁺) p (or n) grid region (2) and the n of source region (5) opposite side ⁺(or p ⁺) in n (or p) trap (8) between drain region (7).

9, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 7 is characterized in that, it is that a layer falls in the p (or n) of two differently doped regions that layer (10) falls in described p (or n).

10, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 7 is characterized in that, it is that a layer falls in the many rings of p (or n) type that a layer (10) falls in described p (or n).

11, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 5 is characterized in that described n ⁺(or p ⁺) number of source region (5) is M (M for greater than 1 natural number), the number in described p (or n) grid region (2) is (M+1); All p (or n) grid regions (2) are parallel to each other, and with all n ⁺(or p ⁺) source region (5) in twos at interval, and all be arranged in n (or p) trap (8).

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