CN1937257A - High-voltage SensorFET device - Google Patents
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- CN1937257A CN1937257A CN 200610021845 CN200610021845A CN1937257A CN 1937257 A CN1937257 A CN 1937257A CN 200610021845 CN200610021845 CN 200610021845 CN 200610021845 A CN200610021845 A CN 200610021845A CN 1937257 A CN1937257 A CN 1937257A
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Abstract
Belonging to techniques of semiconductor power device and power IC, sensing technique of power device, the high voltage SensorFET device includes high voltage SensorFET devices with transverse/longitudinal JFET structures. JFET channel in transverse JFET structure is formed by clamping n (or p) trap (or epitaxial layer) between p (or n) gate area and p (or n) substrate. Using RESURF principle raises breakdown voltage of device. JFET channel in longitudinal JFET structure is formed by clamping n (or p) trap (or epitaxial layer) between different p (or n) gate areas as well as clamping n (or p) trap (or epitaxial layer) between p (or n) gate area and p (or n) substrate. Using RESURF principle raises breakdown voltage of device. Satidfying high withstanding voltage, the invention possesses good IV characteristic of JFET, and functions for sampling current and for providing current of charging IC in low voltage. The invention is applicable to power control, and driving motor etc.
Description
Technical field
The invention belongs to semiconductor power device technology, power device sensing technology and power integrated circuit technical field.
Background technology
In recent years, along with the development of power electronic technology, smart-power IC (SPIC) has obtained application more and more widely.SPIC is logic control circuit and power device, integrated until modulating mode, its benefit is the protective circuit that design has pair high-tension circuit and power device, so just obviously improved circuit and device at high pressure or/and the reliability under the current condition greatly.And the realization of the protective circuit of high-tension circuit and power device just relates to the signals sampling problem.At present, in power integrated circuit, the signal sampling of high-tension circuit being mainly contained dual mode, is respectively voltage sample and current sample.
In power integrated circuit, voltage sample mode commonly used is to insert the series resistance loop on the bus of circuit of high pressure.The resistance that joins with high voltage is bigger above, and the resistance that joins with ground is less below, and sampling can be got the manageable signal of low-voltage control circuit from high-voltage bus like this.But this voltage sample mode cost is higher, especially adopts the higher resistance of precision also to have withstand voltage restriction.For this reason, scholars have proposed the measure of various voltage sample modes.Document (1), T.Terashima, M.Yoshizawa, M.Fukunaga, et.al, Structure of 600V IC and A new voltage sensingdevice (structure of 600V IC and novel voltage senser element), ISPSD, 1993:224-229, structure is as shown in Figure 1.This structure devices adopts the RESURF technology to optimize the drift region electric field, and the connection of constant-current source is adopted simultaneously at the depletion layer inward flange of transversal device in the zone of its detecting voltage, has avoided the puncture of potential circuit.But this constant-current source can inject charge carrier in depletion region, influenced the Electric Field Distribution of device, thereby has directly influenced the many characteristics of device; Secondly, the position of voltage sensor is extremely responsive to main junction voltage.Owing to introduced a N at the depletion layer inward flange
+Gauging ring or P
+Gauging ring is easy to destroy the RESURF condition that satisfies its drift region, can reduce the puncture voltage of device.Document (2), HAN Lei, YE Xing-ning, CHEN Xing-bi, A Novel High-Voltage Detector Integrated into SPIC by Using FFLR (the high tension voltage detector among the be integrated in SPIC that realizes of the floating empty field limiting ring of a kind of novel usefulness), CHINESE JOURNAL OFSEMICONDUCTORS, 2001,22 (10): 1250-1254, the voltage divider principle of employing field limiting ring has realized the voltage sample to high-tension circuit, structure is as shown in Figure 2.Voltage between the adjacent ring of this structure does not change with main junction voltage, and there is relation one to one in the voltage on the field limiting ring with the main voltage of tying.Therefore, the high pressure of main knot can be utilized progressively dividing potential drop of a plurality of field limiting rings, and an outermost ring is designed to the high tension voltage detector to realize sampling the manageable voltage signal of low-voltage control circuit.But when main junction voltage raise, this structure need increase the quantity of field limiting ring and adjust the spacing of ring, thereby caused the increase of chip area.In addition, in the silicon oxidation process of planar technique, can have a certain amount of movable charge and fixed charge inevitably in the interface between oxide layer and silicon, these interface charges can obviously influence the Electric Field Distribution of field limiting ring system, thereby can't realize good voltage sample performance.Document (3), J.Petruzzello, T.Letavic, B.Dufort, SOI HighVoltage Power FET with an Internal Voltage (Current) Sensing Terminal (inside has the SOI high-voltage power field effect transistor of voltage (electric current) sampling terminal), ISPSD, 2003:224-227, structure is as shown in Figure 3.This structure is utilized the drain terminal voltage of sampling of the field plate on oxygen (FOX), by field oxygen electric capacity (C
FP) and an external capacitor C
EXT(being connected between field plate and the ground) realizes that field plate voltage and drain terminal voltage concern that one to one the dividing potential drop formula is as follows:
V wherein
FPBe field plate voltage, V
DSBe drain terminal voltage, C
FP(V
DS) represent that an oxygen electric capacity is the function of drain terminal voltage.But this structure has 2 deficiencies: the one, and an oxygen electric capacity is the function of drain terminal voltage, reduces along with the increase of drain terminal voltage, thereby can not reflect drain terminal voltage well; The 2nd, movable charge between oxide layer and the silicon interface and fixed charge make this structure can not realize good voltage sample performance.In sum, voltage sample mode or can not accurately reflect drain terminal voltage, otherwise the puncture voltage of its device architecture is lower.
Power device current sample mode usually adopts direct series connection small resistor or ammeter, but this can cause certain loss and other unfavorable factor, or utilizes the method for coupling small inductor when exchanging, said method or loss is bigger, only at the interchange condition, and need outward element.In power device, adopt the primitive unit cell parallel-connection structure more, to transversal device, also be the parallel connection of a plurality of unit.Therefore, only get one of them or smaller units, its electric current becomes relatively stricter proportionate relationship with total current, thereby realizes the current sample to power device.Document (4), Chong-Man Yun, Doo-Young Kim, Yeam-Ik Choi, et.al, AMonolithic Current Limiting Power MOSFET (monolithic has the power MOSFET of current-limiting function), IEEE, 1995:71-74, structure is as shown in Figure 4.This structure utilizes VDMOS to be made of a lot of primitive unit cells, and the source electrode of getting a part of primitive unit cell is wherein drawn separately, and the electric current that flows through on it just can react total current.Because how many electric currents distributes according to the primitive unit cell number fully, obtains sample rate current by the ratio that the primitive unit cell number is set.But this current sample Mode S ensor device needs outer meeting resistance to carry out current sample, and outer meeting resistance causes bad influence (distributing unequal such as withstand voltage reduction, electric current) to the characteristic of whole power device.
Summary of the invention
The object of the present invention is to provide the high-voltage SensorFET device with JFET structure, this device has the IV characteristic of good JFET when satisfied height is withstand voltage.This device has current sample and for low-voltage ic provides the charging current function, and is easy to integrated.
The present invention proposes the high-voltage SensorFET device of current sample pattern shown in Figure 5, this structure devices can be avoided the voltage sample and the deficiency of current-mode in the past, the device that has this sampling structure simultaneously not only can well be realized the function of current sample and control, can also carry out providing certainly of the power integrated circuit work energy by this device of sampling.As shown in Figure 6.During the Switching Power Supply operate as normal, A4=1, the power tube conducting, power tube drain terminal voltage is lower tens volts, SensorFET is operated in linear zone less D.C. resistance, MN19 pipe conducting simultaneously, and the conducting electric current of sampled power pipe is in low-voltage circuit, compare with current limitation, with the conducting duty ratio of power controlling pipe.This moment, the effect of SensorFET was that the conducting electric current of sampled power pipe is in low-voltage circuit and sample and control.
During A4=0, power tube turn-offs, and the drain terminal general value of power tube will float to the magnitude of voltage of several hectovolts at this moment.Flow through the SensorFET device do not need too big electric current this moment, only needs less current electric current to be provided for the chip internal circuit and to shunt capacitance C charging current (SensorFET provides stable low-tension supply by the internal circuit that is charged as the power supply control IC to shunt capacitance).The high drain voltage of several hectovolts but only provides little charging current to realize by SensorFET.The SensorFET of this moment is operated in the saturation region, and big direct current conducting resistance is arranged, and will produce little charging current so for the RC loop.
This structure adopts open type high pressure JFET form to realize that its concrete structure is (Fig. 7 is the concrete form of the included structure of frame of broken lines among Fig. 5) as shown in Figure 7.In addition, for the SensorFET device, the present invention also provides structure as shown in Figure 8.As shown in Figure 5, this structure utilizes transversal device by one or more unit parallel connection, gets one or more unit and carries out current sample.In structure of the present invention, when the main power tube operate as normal, its drain terminal voltage ratio is lower, this moment SensorFET JFET raceway groove pinch off not, thereby can sample electric current in the main power tube of SensorFET; When closing, power tube has no progeny, this moment device drain terminal voltage ratio higher (being generally about 600V), SensorFET can make external capacitor can provide power supply for low-voltage control circuit after power tube is opened directly for the external capacitor that serves as the low-voltage control circuit power supply charges; Simultaneously, the JFET raceway groove of SensorFET is pinch off, promptly be equivalent to the resistance that resistance is very high, dividing potential drop effect by SensorFET, can guarantee that low-voltage circuit and high-tension circuit well are connected (wherein, the sampling function of SensorFET works when power tube is worked, and this moment, its charge function stopped; When power tube turn-offed, the charge function of SensorFET worked, and the sampling function stop).Aspect withstand voltage, utilize the high voltage endurance of RESURF technology realization SensorFET, to guarantee that SensorFET can operate as normal under power tube shutoff, the higher situation of drain terminal voltage.
Detailed technology scheme of the present invention is as follows:
One. the high-voltage SensorFET device of horizontal JFET structure
The invention provides high-voltage SensorFET device, as shown in Figure 7, comprise n with horizontal JFET structure
+(or p
+) source region 5, n
+(or p
+) drain region 7, p (or n) grid region 2, n (or p) trap 8 and p (or n) substrate 6; It is characterized in that p (or n) grid region 2 is positioned at n
+(or p
+) source region 5 and n
+(or P
+) in n (or p) trap 8 between the drain region 7; Form the JFET raceway groove by pressing from both sides n (or p) trap 8 between p (or n) grid region 2 and p (or n) substrate 6, provide the IV characteristic of JFET with this; Constitute a transverse diode by p (or n) grid region 2 and n (or p) trap 8, constitute a vertical diode by p (or n) substrate 6 and n (or p) trap 8, described transverse diode and vertical diode constitute the RESURF structure, improve the puncture voltage of device with this.
Above-mentioned high-voltage SensorFET device with horizontal JFET structure, the also available n of described n (or p) trap (8) (or p) epitaxial loayer replaces.
Need to prove:
The RESURF structure requires n (or p) trap (or epitaxial loayer) 8 all to exhaust in order to obtain high puncture voltage.Exhaust entirely to occur in the avalanche breakdowns of horizontal p (or n) grid region 2/n (or p) trap (or epitaxial loayer) 8 knot before.
Two. the high-voltage SensorFET device of vertical JFET structure
The present invention also provides the high-voltage SensorFET device with vertical JFET structure, as shown in Figure 8, comprises a n
+(or p
+) source region 5, two n
+(or p
+) drain region 7, two p (or n) grid regions 2, n (or p) trap 8 and a p (or n) substrate 6; It is characterized in that two p (or n) grid region 2 is parallel to each other, a p (or n) grid region 2 is positioned at n
+(or p
+) source region 5 and a n
+(or p
+) in n (or p) trap 8 between the drain region 7, another p (or n) grid region 2 is positioned at n
+(or p
+) source region 5 and another n
+(or p
+) in n (or p) trap 8 between the drain region 7; By pressing from both sides n (or p) trap 8 and two p (or n) grid region 2 between two p (or n) grid region 2 respectively and press from both sides n (or p) trap 8 between p (or n) substrate 6 and form the JFET raceway grooves, provide the IV characteristic of JFET with this; By two p (or n) grid region 2 respectively and n (or p) trap 8 constitute two transverse diodes, constitute a vertical diode by p (or n) substrate 6 and n (or p) trap 8, described two transverse diodes and a vertical diode constitute the RESURF structure, improve the puncture voltage of device with this.It is characterized in that drain electrode, grid and source electrode all at device surface, are easy to other device integrated.
Above-mentioned high-voltage SensorFET device with vertical JFET structure, the also available n of described n (or p) trap (8) (or p) epitaxial loayer replaces.
Need to prove:
The RESURF structure requires n (or p) trap (or epitaxial loayer) 8 all to exhaust in order to obtain high puncture voltage.Exhaust entirely to occur in the avalanche breakdowns of horizontal p (or n) grid region 2/n (or p) trap (or epitaxial loayer) 8 knot before.
Operation principle of the present invention:
One, the high-voltage SensorFET device of horizontal JFET structure
High-voltage SensorFET device with horizontal JFET structure provided by the invention can improve the puncture voltage (can reach the required voltage requirement according to design) of device greatly when keeping device to have the IV characteristic of good JFET.Here be example with high-voltage SensorFET device, the operation principle of this structure among the present invention is described with horizontal JFET structure.
As shown in Figure 7, high-voltage SensorFET device with horizontal JFET structure, press from both sides n (or p) trap (or epitaxial loayer) 8 between its p (or n) grid region 2 and p (or n) substrate 6 and form the JFET raceway groove, when the drain electrode making alive, when grid and source ground, in the JFET raceway groove, form by the electric field that leaks the sensing source, many sons in the semiconductor produce the raceway groove drift current under this electric field action, when drain voltage increases, since the depletion region of p (or n) grid region 2/n (or p) trap (or epitaxial loayer) 8 knot to the depletion region of n (or p) trap (or epitaxial loayer) 8 broadenings and p (or n) substrate 6/n (or p) trap (or epitaxial loayer) 8 knots to n (or p) trap (or epitaxial loayer) 8 broadenings, final these two depletion regions will meet in raceway groove, make the raceway groove pinch off.Increase along with drain terminal voltage, device will be in the operate in saturation district, because the existence of raceway groove mudulation effect, drain current increases slightly with the increase of drain voltage during the saturation region, in order to satisfy the application requirements of SensorFET in Switching Power Supply (be drain terminal when being high pressure SensorFET be equivalent to the resistance of a big resistance) better, should make the raceway groove of JFET long as far as possible, to reduce the raceway groove mudulation effect, but this relates to the problem that conducting resistance increases again, thus channel length choose the consideration of should according to circumstances compromising.When drain terminal voltage arrives certain value greatly, when surpassing the puncture voltage of device, drain current will sharply increase.
In order to satisfy the requirement that SensorFET under high pressure uses, adopted the RESURF technology, the RESURF structure is made of 8 and vertical diode p of a transverse diode p (or n) grid region 2/n (or p) trap (or epitaxial loayer) (or n) substrate 6/n (or p) traps (or epitaxial loayer) 8, and this vertical diode provides keeps high withstand voltage space charge depletion region.The basic principle of RESURF structure is decided by three parameters: substrate doping density P
Sub, (being assumed to be even doping) impurity mean concentration N of trap
WellDrift region junction depth X with trap
JwellTherefore the integral charge in the trap is Q
n=N
Well* X
Jnwell, work as Q
nIn the time of within the specific limits, vertically the depletion region of diode in the drift region of n (or p) trap (or epitaxial loayer) 8 and transverse diode in the drift region of n (or p) trap (or epitaxial loayer) 8 depletion region be connected, make the transverse diode width of depletion region compare significantly increase with the width of depletion region that does not have p (or n) substrate 6 transverse diodes.Therefore in the obvious reduction of the transverse electric field at p (or n) grid region 2/n (or p) trap (or epitaxial loayer) 8 lateral junction places, thereby can improve device electric breakdown strength than one dimension diode.Requirement drift region in n (or p) trap (or epitaxial loayer) 8 before transverse electric field reaches critical breakdown electric field all exhausts, and this moment, the RESURF structure obtained maximum breakdown voltage.As shown in Figure 7, vertical depletion region of the drift region in n (or p) trap (or epitaxial loayer) 8 is provided by p (or n) substrate 6/n (or p) trap (or epitaxial loayer) 8 these knots, so be referred to as Single RESURF structure.
Two, the high-voltage SensorFET device of vertical JFET structure
High-voltage SensorFET device with vertical JFET structure, its operation principle is identical with the high-voltage SensorFET device of above-mentioned horizontal JFET structure.This structure is compared with the high-voltage SensorFET device of horizontal JFET structure, and difference is that its JFET raceway groove is longitudinally.
In sum, the high-voltage SensorFET device of horizontal JFET structure provided by the invention when realizing the IV characteristic of JFET well, has improved the puncture voltage of device greatly; The high-voltage SensorFET device that is easy to realize with integrated vertical JFET structure also is provided.For the P type is an example, by the emulation of MEDICI and TSUPREM4 simulator, the result is as follows with the substrate:
1. for the high-voltage SensorFET of horizontal JFET structure, when p substrate 6 concentration are 1.5 * 10
14/ cm
3, n trap (or epitaxial loayer) 8 concentration are 1.25 * 10
15/ cm
3, n trap (or epitaxial loayer) 8 junction depths (or thickness) are that the concentration in 8 μ m, p grid region 2 is 2 * 10
17/ cm
3, p grid region 2 junction depths are 1 μ m, n
+Drain region 7 and n
+The concentration in source region 5 is 6 * 10
19/ cm
3, n
+Drain region 7 and n
+When source region 5 junction depths were 0.5 μ m, its puncture voltage was 680V; When grid 3 ground connection and source electrode 4 ground connection, its IV characteristic as shown in Figure 9.
2. for the high-voltage SensorFET of vertical JFET structure, when p substrate 6 concentration are 1.5 * 10
14/ cm
3, n trap (or epitaxial loayer) 8 concentration are 5 * 10
14/ cm
3, n trap (or epitaxial loayer) 8 junction depths (or thickness) are that the concentration in 30 μ m, p grid region 2 is 8 * 10
16/ cm
3, p grid region 2 junction depths are 25 μ m, n
+Drain region 7 and n
+The concentration in source region 5 is 6 * 10
19/ cm
3, n
+Drain region 7 and n
+When source region 5 junction depths were 0.5 μ m, its puncture voltage was 890V; When grid 3 ground connection and source electrode 4 ground connection, its IV characteristic as shown in figure 10.
By Fig. 9, Figure 10 as can be known, laterally the high-voltage SensorFET of the high-voltage SensorFET of JFET structure and vertical JFET structure has the IV characteristic of good JFET when satisfied height is withstand voltage.
Description of drawings
Fig. 1 is the structural representation of existing 600V IC and novel voltage senser element.
Fig. 2 is the high tension voltage panel detector structure schematic diagram among the be integrated in SPIC that realizes of the floating empty field limiting ring of existing usefulness.
Fig. 3 is the SOI high-voltage power field-effect tube structure schematic diagram that existing inside has voltage (electric current) sampling terminal.
Fig. 4 is the power MOSFET structural representation that existing monolithic has current-limiting function.
Fig. 5 is the power MOSFET structural representation with sampling, charge function of the present invention.
Fig. 6 is the current sample and the self-powered application circuit schematic diagram of high-voltage SensorFET of the present invention.
Fig. 7 is the high-voltage SensorFET device structural representation of horizontal JFET structure of the present invention,
Wherein, the 1st, drain electrode, the 2nd, p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer.
Fig. 8 is the high-voltage SensorFET device structural representation with vertical JFET structure of the present invention,
Wherein, the 1st, drain electrode, the 2nd, p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer.
Fig. 9 is the IV characteristic curve schematic diagram of the high-voltage SensorFET device of horizontal JFET structure shown in Figure 7,
Grounded-grid wherein, source ground.
Figure 10 is the IV characteristic curve schematic diagram of the high-voltage SensorFET device of vertical JFET structure shown in Figure 8,
Grounded-grid wherein, source ground.
Figure 11 of the present inventionly has horizontal JFET structure and p (or n) and falls a high-voltage SensorFET device structural representation of layer,
Wherein, the 1st, drain electrode, the 2nd, p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer, the 10th, a layer falls in p (or n).
Figure 12 is that a high-voltage SensorFET device structural representation of layer falls in the p (or n) with horizontal JFET structure and differently doped regions of the present invention,
Wherein 1 is drain electrode, the 2nd, and p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or P
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer, 10 is that a layer falls in the p (or n) of two differently doped regions.
Figure 13 is have a horizontal JFET structure and p (or n) the type high-voltage SensorFET device structural representations that fall the field layer that encircle of the present invention more,
Wherein 1 is drain electrode, the 2nd, and p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or P
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer, the 10th, a layer falls in the many rings of p (or n) type.
Figure 14 of the present inventionly has vertical JFET structure and p (or n) and falls a high-voltage SensorFET device structural representation of layer,
Wherein, the 1st, drain electrode, the 2nd, p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer, the 10th, a layer falls in p (or n).
Figure 15 is that a high-voltage SensorFET device structural representation of layer falls in the p (or n) with vertical JFET structure and differently doped regions of the present invention,
Wherein, the 1st, drain electrode, the 2nd, p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or P
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer, 10 is that a layer falls in the p (or n) of two differently doped regions.
Figure 16 is have a vertical JFET structure and p (or n) the type high-voltage SensorFET device structural representations that fall the field layer that encircle of the present invention more,
Wherein 1 is drain electrode, the 2nd, and p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or p
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer, the 10th, a layer falls in the many rings of p (or n) type.
Figure 17 is the high-voltage SensorFET device structural representation with vertical JFET structure and multi-point sampling of the present invention,
Wherein 1 is drain electrode, the 2nd, and p (or n) grid region, the 3rd, grid, the 4th, source electrode, the 5th, n
+(or p
+) source region, the 6th, p (or n) substrate, the 7th, n
+(or P
+) drain region, the 8th, n (or p) trap or n (or p) epitaxial loayer.
Figure 18 is have a horizontal JFET structure and p (or n) the type IV characteristic curve schematic diagrames that fall the field layer that encircle shown in Figure 10 more
Grounded-grid wherein, source ground, substrate are the P type.P substrate 6 concentration are 1.5 * 10
14/ cm
3, n trap (or epitaxial loayer) 8 concentration are 2 * 10
15/ cm
3, n trap (or epitaxial loayer) 8 junction depths (or thickness) are that the concentration in 8 μ m, p grid region 2 is 2 * 10
17/ cm
3, p grid region 2 junction depths are 1 μ m, n
+Drain region 7 and n
+The concentration in source region 5 is 6 * 10
19/ cm
3, the p concentration of falling layer 10 is 2 * 10
17/ cm
3, the p junction depth that falls layer 10 is 0.5 μ m, n
+Drain region 7 and n
+When source region 5 junction depths were 0.5 μ m, its puncture voltage was 854V.Simultaneously, this structure also has the IV characteristic of good JFET.
Embodiment
Adopt the high-voltage SensorFET device structure that has the high-voltage SensorFET device structure of horizontal JFET structure and have vertical JFET structure of the present invention, can obtain IV characteristic and the withstand voltage high high pressure sampling device of good JFET.The Switching Power Supply and the motor driven that can be widely used in all kinds of current sample modes.And this class formation has the characteristics with the power integrated circuit compatibility.Along with the development of semiconductor device art, adopt the present invention can also make the high pressure JFET device of the IV characteristic of more high pressure, low on-resistance, good JFET.
During concrete enforcement, to having the high-voltage SensorFET of horizontal JFET structure, first epitaxial growth n (or p) layer or inject n (or p) trap and carry out knot on p (or n) substrate injects p (or n) grid region then and carries out knot, then injects n again
+(or P
+) drain region and source region.
To having the high-voltage SensorFET of vertical JFET structure, first epitaxial growth n (or p) layer or inject n (or p) trap and carry out knot on p (or n) substrate, there is multiple mode to realize the grid region, inject p (or n) grid region as direct photoetching, perhaps by cutting, fill to form p (or n) grid region, then inject n
+(or P
+) drain region and source region.
A high-voltage SensorFET of layer falls to having horizontal JFET structure and p (or n), first epitaxial growth n (or p) layer or inject n (or p) trap and carry out knot on p (or n) substrate, inject p (or n) grid region then and carry out knot, then inject p (or n) and fall a layer, then inject n again
+(or p
+) drain region and source region.A perhaps grid region and fall layer and form simultaneously.
In implementation process, can be as the case may be, under the constant situation of basic structure, can carry out certain accommodation design, for example:
The surface, drift region can be injected an even p (or n) and fall a layer 10 between drain region 7 among Fig. 7 and the grid region 2, as shown in figure 11.It can be uniformly that a layer concentration falls in above-mentioned p (or n), also can be to fall a layer to adopt horizontal varying doping (LVD) technology, and its concentration reduces to drain terminal one side gradually from source end one side.Perhaps P is fallen layer and is divided into a plurality of different doped regions, adopt near the zone of source end highly doped, regional low-doped near drain terminal, as shown in figure 12; It can be a single layer structure of falling that a layer falls in above-mentioned p (or n), also can make the many rings of p (or n) type simultaneously on the surface and fall a structure of layer, as shown in figure 13.
The surface, drift region can be injected an even p (or n) and fall a layer 10 between drain region 7 among Fig. 8 and the grid region 2, as shown in figure 14.It can be uniformly that a layer concentration falls in above-mentioned p (or n), also can be to fall a layer to adopt horizontal varying doping (LVD) technology, and its concentration reduces to drain terminal one side gradually from source end one side.Perhaps P is fallen layer and is divided into a plurality of different doped regions, adopt near the zone of source end highly doped, regional low-doped near drain terminal, as shown in figure 15; It can be a single layer structure of falling that a layer falls in above-mentioned p (or n), also can make a plurality of p (or n) simultaneously on the surface and fall a structure of layer as shown in figure 16; Vertically the JFET raceway groove can be single vertical JFET channel structure, and the structure that also can make a plurality of vertical JFET raceway grooves simultaneously realizes the multiple spot current sample as shown in figure 17.
Claims (11)
1, a kind of high-voltage SensorFET device with horizontal JFET structure comprises n
+(or p
+) source region (5), n
+(or p
+) drain region (7), p (or n) grid region (2), n (or p) trap (8) and p (or n) substrate (6); It is characterized in that p (or n) grid region (2) is positioned at n
+(or p
+) source region (5) and n
+(or p
+) in n (or p) trap (8) between drain region (7); Form the JFET raceway groove by pressing from both sides n (or p) trap (8) between p (or n) grid region (2) and p (or n) substrate (6), provide the IV characteristic of JFET with this; Constitute a transverse diode by p (or n) grid region (2) and n (or p) trap (8), constitute a vertical diode by p (or n) substrate (6) and n (or p) trap (8), described transverse diode and vertical diode constitute the RESURF structure, improve the puncture voltage of device with this.
2, a kind of high-voltage SensorFET device with horizontal JFET structure according to claim 1 is characterized in that, described n (or p) trap (8) replaces with n (or p) epitaxial loayer.
According to claim 1,2 described a kind of high-voltage SensorFET devices, it is characterized in that 3, comprise that also a layer (10) falls in a p (or n), described p (or n) falls a layer (10) and is positioned at p (or n) grid region (2) and n with horizontal JFET structure
+(or p
+) in n (or p) trap (8) between drain region (7).
4, a kind of high-voltage SensorFET device with horizontal JFET structure according to claim 3 is characterized in that, it is that a layer falls in the p (or n) of two differently doped regions that layer (10) falls in described p (or n).
5, a kind of high-voltage SensorFET device with horizontal JFET structure according to claim 3 is characterized in that, it is that a layer falls in the many rings of p (or n) type that a layer (10) falls in described p (or n).
6, a kind of high-voltage SensorFET device with vertical JFET structure comprises a n
+(or p
+) source region (5), two n
+(or p
+) drain region (7), two p (or n) grid regions (2), a n (or p) trap (8) and a p (or n) substrate (6); It is characterized in that two p (or n) grid regions (2) are parallel to each other, a p (or n) grid region (2) is positioned at n
+(or p
+) source region (5) and a n
+(or p
+) in n (or p) trap (8) between drain region (7), another p (or n) grid region (2) is positioned at n
+(or p
+) source region (5) and another n
+(or p
+) in n (or p) trap (8) between drain region (7); By pressing from both sides n (or p) trap (8) and two p (or n) grid regions (2) between two p (or n) grid regions (2) respectively and press from both sides n (or p) trap (8) between p (or n) substrate (6) and form the JFET raceway groove, provide the IV characteristic of JFET with this; By two p (or n) grid regions (2) respectively and n (or p) trap (8) constitute two transverse diodes, constitute a vertical diode by p (or n) substrate (6) and n (or p) trap (8), described two transverse diodes and a vertical diode constitute the RESURF structure, improve the puncture voltage of device with this.
7, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 5 is characterized in that, described n (or p) trap (8) replaces with n (or p) epitaxial loayer.
According to claim 5,6 described a kind of high-voltage SensorFET devices, it is characterized in that 8, comprise that also a layer (10) falls in two p (or n), one of them p (or n) falls a layer (10) and is positioned at n with vertical JFET structure
+(or p
+) p (or n) grid region (2) and the n of source region (5) one sides
+(or p
+) in n (or p) trap (8) between drain region (7), another p (or n) falls a layer (10) and is positioned at n
+(or p
+) p (or n) grid region (2) and the n of source region (5) opposite side
+(or p
+) in n (or p) trap (8) between drain region (7).
9, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 7 is characterized in that, it is that a layer falls in the p (or n) of two differently doped regions that layer (10) falls in described p (or n).
10, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 7 is characterized in that, it is that a layer falls in the many rings of p (or n) type that a layer (10) falls in described p (or n).
11, a kind of high-voltage SensorFET device with vertical JFET structure according to claim 5 is characterized in that described n
+(or p
+) number of source region (5) is M (M for greater than 1 natural number), the number in described p (or n) grid region (2) is (M+1); All p (or n) grid regions (2) are parallel to each other, and with all n
+(or p
+) source region (5) in twos at interval, and all be arranged in n (or p) trap (8).
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|---|---|---|---|
| CNB2006100218454A CN100446275C (en) | 2006-09-14 | 2006-09-14 | High-voltage SensorFET device |
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| CN100446275C CN100446275C (en) | 2008-12-24 |
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| CN101752208A (en) * | 2008-12-03 | 2010-06-23 | 上海芯能电子科技有限公司 | Semiconductor high-voltage terminal structure and production method thereof |
| CN101976665A (en) * | 2010-09-07 | 2011-02-16 | 电子科技大学 | Controllable self-clamp Sensor FET (Field Effect Transistor) composite longitudinal power device with multiple bleeding channels |
| CN101980363A (en) * | 2010-08-31 | 2011-02-23 | 电子科技大学 | Controllable self-clamping SensorFET composite lateral power device |
| CN101980362A (en) * | 2010-08-31 | 2011-02-23 | 电子科技大学 | Controllable self-clamping SensorFET composite vertical power device |
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| CN101976666B (en) * | 2010-09-07 | 2012-01-11 | 电子科技大学 | Controllable self-clamping SensorFET composite transverse power device with multiple release channels |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69225552T2 (en) * | 1991-10-15 | 1999-01-07 | Texas Instruments Inc., Dallas, Tex. | Lateral double-diffused MOS transistor and method for its production |
| US5873053A (en) * | 1997-04-08 | 1999-02-16 | International Business Machines Corporation | On-chip thermometry for control of chip operating temperature |
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| CN101980363B (en) * | 2010-08-31 | 2011-11-16 | 电子科技大学 | Controllable self-clamping SensorFET composite lateral power device |
| CN101980362B (en) * | 2010-08-31 | 2011-12-21 | 电子科技大学 | Controllable self-clamping SensorFET composite vertical power device |
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| CN109768089A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of voltage-controlled Sampling device based on SenseFET |
| CN110047920A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | A kind of horizontal junction grid bipolar transistor and preparation method thereof |
| CN110047920B (en) * | 2019-04-16 | 2021-06-18 | 西安电子科技大学 | Transverse junction type gate bipolar transistor and manufacturing method thereof |
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