CN104733533A - Covering type super-junction transverse double diffusion metal oxide semiconductor field effect transistor with N-type buried layer - Google Patents
Covering type super-junction transverse double diffusion metal oxide semiconductor field effect transistor with N-type buried layer Download PDFInfo
- Publication number
- CN104733533A CN104733533A CN201510112411.4A CN201510112411A CN104733533A CN 104733533 A CN104733533 A CN 104733533A CN 201510112411 A CN201510112411 A CN 201510112411A CN 104733533 A CN104733533 A CN 104733533A
- Authority
- CN
- China
- Prior art keywords
- type
- super
- field effect
- effect transistor
- type buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a new SJ-LDMOS device, and belongs to the technical field of semiconductor power devices. An N-type buried layer is introduced in a traditional SJ-LDMOS device structure and located on a super-junction layer. Compared with a traditional SJ-LDMOS, by means of the action of the N-type buried layer, charge imbalance between an N-type column region and a P-type column region in a super junction is compensated, the substrate-assisted effect is overcome, and breakdown voltage is increased; due to the N-type buried layer, a new conduction path is additionally added, and specific on-resistance is reduced. The structure has the advantages of the high breakdown voltage, the low on-resistance and charge balance in the super-junction layer. The new SJ-LDMOS device structure has the advantages of being simple in manufacturing technology and low in technology difficulty and meets the application requirement of a power electronic system more easily.
Description
Technical field
The present invention relates to semiconductor power device technology field, being specifically related to is a kind of super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor.
Background technology
Lateral double diffusion metal oxide semiconductor field effect transistor (Lateral Double-diffusedMOSFET, be called for short LDMOS) be easy to the advantage such as integrated with low-voltage device owing to having, and become the Primary Component in smart-power IC and system-on-chip designs.Be primarily characterized in that and add one section of light dope drift region relatively grown between base and drain region, the doping type of this drift region is consistent with drain region, by adding drift region, can play the effect of sharing puncture voltage, improve the puncture voltage of LDMOS.The optimization aim of LDMOS is low conducting resistance, and conduction loss is minimized.
Superjunction (super junction) structure is the NXing Zhu district and P Xing Zhu district that are alternately arranged, if replace the drift region of LDMOS with super-junction structure, just defines super junction LDMOS, is called for short SJ-LDMOS.In theory, super-junction structure can obtain high puncture voltage by the charge balance between NXing Zhu district and P Xing Zhu district, and very low conducting resistance can be obtained by heavily doped NXing Zhu district and P Xing Zhu district, therefore, superjunction devices can obtain between puncture voltage and conducting resistance two key parameters one well compromise.
But for SJ-LDMOS, due to substrate-assisted depletion NXing Zhu district (or P Xing Zhu district), when making device breakdown, P Xing Zhu district (HuoNXing Zhu district) can not exhaust completely, break the charge balance between LiaoNXing Zhu district and P Xing Zhu district, reduce the lateral breakdown voltage of SJ-LDMOS device.
Summary of the invention
The present invention proposes a kind of n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, improves the contradictory relation between puncture voltage and conduction resistance, achieves high puncture voltage and low conduction resistance.
The present invention program is as follows:
N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, comprising:
P type semiconductor substrate;
Be positioned at the adjacent P type base on N-type epitaxy layer surface on described P type semiconductor substrate and super interface; Described super interface comprises NXing Zhu district and P Xing Zhu district;
Be positioned at the N-type source region of P type base part surface;
Be positioned at the N-type drain region of super interface part surface;
Its special character is:
Be provided with N-type buried dopant layer between described P type base and N-type drain region, cover the surface of super interface remaining part.
Based on above scheme, the present invention also does following optimization further:
Above-mentioned super interface adopts the horizontal period distances in NXing Zhu district and P Xing Zhu district to discharge, and the width in each NXing Zhu district is identical, and the width in each P Xing Zhu district is identical.Further, each NXing Zhu district is preferably also identical with the width in each P Xing Zhu district.
The cross section of above-mentioned N-type buried dopant layer is regular figure (certainly, also can be irregular figure), is good with circular or rectangle.
The longitudinal section of above-mentioned N-type buried dopant layer is regular figure (certainly, also can be irregular figure), is good with circular or rectangle.
The concentration of above-mentioned N-type buried dopant layer is uniform (also can be certainly, heterogeneous).
Certainly, LDMOS of the present invention also can be P raceway groove, then " P ", " N " relation of structure and above N raceway groove scheme is exchanged, and namely changes " N-type substrate ", " N-type base ", " P type source region ", " P type drain region ", " P type buried dopant layer " into ... do not repeat them here.
Beneficial effect of the present invention is as follows:
By introducing one deck n type buried layer in traditional SJ-LDMOS device architecture, this buried regions is positioned at above super junction layer.Compared with traditional SJ-LDMOS, the present invention, by the effect of n type buried layer, compensate for the charge unbalance between super junction NeiNXing Zhu district and P Xing Zhu district, overcomes substrate secondary effects, improve puncture voltage; Meanwhile, n type buried layer additionally increases a new conductive path, reduces conduction resistance.Therefore can further be promoted than the optimization of general scheme puncture voltage and conduction resistance.
The manufacture of this programme device is simple, and operability is stronger.
Accompanying drawing explanation
Fig. 1 is the schematic three dimensional views of n type buried layer cover type super-junction laterally double-diffusion metal oxide semiconductor field effect tube structure of the present invention.
Fig. 2 be in Fig. 1 drift region along the sectional view in AOC direction.
Embodiment
See Fig. 1 and Fig. 2, specifically introduce new construction in the embodiment of the present invention for a kind of n type buried layer cover type (N raceway groove) super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor below.Those skilled in the art should recognize, this embodiment is not limiting the scope of the invention.
This n type buried layer cover type half super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, it comprises:
P type semiconductor substrate 1;
Be positioned at the adjacent P type base 2 on N-type epitaxy layer surface on described P type semiconductor substrate 1 and super interface; Super interface adopts NXing Zhu district 4 and the horizontal period distances in P Xing Zhu district 5 to discharge (in figure simplified schematic one-period), and the width in each NXing Zhu district is identical, and the width in each P Xing Zhu district is identical; Further, each NXing Zhu district is preferably also identical with the width in each P Xing Zhu district;
Be positioned at the N-type source region 3 of P type base 2 part surface;
Be positioned at the N-type drain region 6 of super interface part surface;
Be provided with N-type buried dopant layer 7 between described P type base and N-type drain region, cover the surface of super interface remaining part, namely as all regions in Fig. 1 between P type base and N-type drain region are covered by N-type buried dopant layer completely.
The manufacture method of above-mentioned n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, its step comprises:
P type base is formed in described P type semiconductor substrate upper epitaxial layer;
N-type source region is formed in described P type base;
Form super interface in the adjacent position of described P type semiconductor substrate and P type base, comprise NXing Zhu district and the P Xing Zhu district of the discharge of horizontal period distances;
Described super interface forms n type buried layer;
Described n type buried layer and super interface form heavily doped N-type drain region.
Concrete doping process, technology existing very ripe in prior art, is not described in detail in this.
Technical scheme of the present invention, by the effect of n type buried layer, compensate for the charge unbalance between super junction NeiNXing Zhu district and P Xing Zhu district, overcomes substrate secondary effects, improve puncture voltage; Meanwhile, n type buried layer additionally increases a new conductive path, reduces conduction resistance.Hence improving the contradictory relation between the puncture voltage of LDMOS and conduction resistance, therefore providing a kind of new device architecture for realizing integrated technology.
Claims (10)
1.N type buried regions cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, comprising:
P type semiconductor substrate;
Be positioned at the adjacent P type base on N-type epitaxy layer surface on described P type semiconductor substrate and super interface; Described super interface comprises NXing Zhu district and P Xing Zhu district;
Be positioned at the N-type source region of P type base part surface;
Be positioned at the N-type drain region of super interface part surface;
It is characterized in that:
Be provided with N-type buried dopant layer between described P type base and N-type drain region, cover the surface of super interface remaining part.
2. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1, it is characterized in that: described super interface adopts the horizontal period distances in NXing Zhu district and P Xing Zhu district to discharge, the width in each NXing Zhu district is identical, and the width in each P Xing Zhu district is identical.
3. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 and 2, is characterized in that: the cross section of described N-type buried dopant layer and/or longitudinal section are regular figure.
4. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 3, is characterized in that: described regular figure is circular or rectangle.
5. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1, is characterized in that: the concentration of described N-type buried dopant layer is uniform.
6.P type buried regions cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor, comprising:
N type semiconductor substrate;
Be positioned at the adjacent N-type base of P type epi-layer surface on described N type semiconductor substrate and super interface; Described super interface comprises NXing Zhu district and P Xing Zhu district;
Be positioned at the P type source region of N-type base part surface;
Be positioned at the P type drain region of super interface part surface;
It is characterized in that:
Be provided with P type buried dopant layer between described N-type base and P type drain region, cover the surface of super interface remaining part.
7. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 6, it is characterized in that: described super interface adopts the horizontal period distances in NXing Zhu district and P Xing Zhu district to discharge, the width in each NXing Zhu district is identical, and the width in each P Xing Zhu district is identical.
8. the n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 6 or 7, is characterized in that: cross section and/or the longitudinal section of described P type buried dopant layer are regular figure.
9. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 8, is characterized in that: described regular figure is circular or rectangle.
10. n type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor according to claim 6, is characterized in that: the concentration of described P type buried dopant layer is uniform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510112411.4A CN104733533B (en) | 2015-03-13 | 2015-03-13 | N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510112411.4A CN104733533B (en) | 2015-03-13 | 2015-03-13 | N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104733533A true CN104733533A (en) | 2015-06-24 |
| CN104733533B CN104733533B (en) | 2018-02-27 |
Family
ID=53457239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510112411.4A Active CN104733533B (en) | 2015-03-13 | 2015-03-13 | N type buried layer cover type super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104733533B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090309132A1 (en) * | 2006-11-30 | 2009-12-17 | Jun Cai | Integrated latch-up free insulated gate bipolar transistor |
| CN102130176A (en) * | 2010-12-31 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer |
| CN104009090A (en) * | 2014-05-29 | 2014-08-27 | 西安电子科技大学 | Transverse double-diffusion metal oxide semiconductor field effect transistor |
-
2015
- 2015-03-13 CN CN201510112411.4A patent/CN104733533B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090309132A1 (en) * | 2006-11-30 | 2009-12-17 | Jun Cai | Integrated latch-up free insulated gate bipolar transistor |
| CN102130176A (en) * | 2010-12-31 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer |
| CN104009090A (en) * | 2014-05-29 | 2014-08-27 | 西安电子科技大学 | Transverse double-diffusion metal oxide semiconductor field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104733533B (en) | 2018-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102610643B (en) | Trench MOSFET device | |
| CN103165678B (en) | Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device | |
| CN101552291B (en) | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels | |
| CN107316899B (en) | Semi-super junction device and manufacturing method thereof | |
| US9837532B2 (en) | Laterally diffused metal oxide semiconductor device and manufacturing method therefor | |
| CN102244092A (en) | Junction termination structure of transverse high-pressure power semiconductor device | |
| CN104124274A (en) | Super junction lateral double diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN102130164A (en) | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) | |
| CN102376762A (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| KR20180083925A (en) | Lateral diffusion metal oxide semiconductor field effect transistor | |
| CN103872133A (en) | Short channel trench mosfets | |
| CN102610641A (en) | High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN102263125A (en) | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides | |
| CN105047693B (en) | A kind of junction termination structures of transverse direction high voltage power device | |
| CN110047930A (en) | VDMOS device | |
| CN105140269B (en) | A kind of junction termination structures of transverse direction high voltage power device | |
| CN103426913B (en) | A kind of partial SOI ultra-junction high-voltage power semiconductor device | |
| CN103107191B (en) | High-voltage P-type LDMOS structure and manufacture method thereof | |
| CN106206677B (en) | The junction termination structures of lateral high voltage power device | |
| CN202454560U (en) | Trench MOSFET device | |
| CN104733533A (en) | Covering type super-junction transverse double diffusion metal oxide semiconductor field effect transistor with N-type buried layer | |
| CN104716190B (en) | The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half | |
| CN107359119B (en) | Super junction power device and manufacturing method thereof | |
| CN104821335B (en) | The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of n type buried layer cover type half | |
| CN204289463U (en) | Super junction-semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |