CN102593007B - Super junction device with multiple embedded P islands and N channels and preparation method thereof - Google Patents
Super junction device with multiple embedded P islands and N channels and preparation method thereof Download PDFInfo
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- CN102593007B CN102593007B CN201210076796.XA CN201210076796A CN102593007B CN 102593007 B CN102593007 B CN 102593007B CN 201210076796 A CN201210076796 A CN 201210076796A CN 102593007 B CN102593007 B CN 102593007B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 17
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 230000000903 blocking effect Effects 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 18
- 210000000746 body region Anatomy 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000003292 diminished effect Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
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Abstract
The invention provides a super junction device with multiple embedded P islands and N channels and a preparation method thereof. The super junction device comprises a semiconductor substrate, an N-type drift region formed on the semiconductor substrate, P-type body regions on one side of the N-type drift region, and N-type leakage regions on the other side of the N-type drift region, wherein a plurality of parallel island-shaped P areas are formed in the N-type drift region at intervals, and each island-shaped P area is gradually diminished in a linear manner from N-type source regions to the N-type leakage regions; the function of the substrate-assisted depletion effect is sequentially enhanced from source ends to leakage ends under a high voltage, so that the island-shaped P areas are correspondingly decreased from the source ends to the leakage ends, and accordingly, the complementation and offset to the substrate-assisted depletion effect are realized, and the purpose of charge balance is achieved.
Description
Technical field
The present invention relates to a kind of semiconductor device and preparation method thereof, particularly relate to super junction device of a kind of embedded many P island N raceway groove and preparation method thereof.
Background technology
Power integrated circuit also claims high voltage integrated circuit sometimes, it is the important branch that hyundai electronics is learned, can be various power conversions and energy processing unit provides the new-type circuit of high speed, high integration, low-power consumption and anti-irradiation, is widely used in many key areas such as the current consumption fields such as electric control system, automotive electronics, display device driving, communication and illumination and national defence, space flight.The rapid expansion of its range of application, also has higher requirement to the high tension apparatus of its core.
For power device MOSFET, guaranteeing that under the prerequisite of puncture voltage, the conducting resistance that must reduce as much as possible device improves device performance.But between puncture voltage and conducting resistance, there is a kind of approximate quadratic relationship, form so-called " silicon limit ".In order to solve this contradiction, forefathers proposed drift region based on three-dimensional RESURF technology by P, the alternate super-junction structure forming of N post for optimizing the drift region Electric Field Distribution of high tension apparatus.This structure is keeping, under the constant prerequisite of conducting resistance, improving puncture voltage, the limit of the power MOS (Metal Oxide Semiconductor) device theory that breaks traditions.The theoretical foundation of this technology is that charge compensation is theoretical, and when drift region applies voltage and reaches certain value, drift region reaches completely and exhausts, and Electric Field Distribution is more even, has improved the breakdown characteristics of device.Guaranteeing, under the constant prerequisite of puncture voltage, can significantly to improve the doping content of drift region, reduce conducting resistance.Conventional power MOSFET device " the silicon limit " has been broken in the proposition of super-junction structure.
Super-junction structure is applied to vertical VDMOS device at first, expands to afterwards horizontal LDMOS device.Forming at present the horizontal super-junction structure of N ditch, is mainly repeatedly that Implantation forms column P district in N-type drift region.Extenuate substrate-assisted depletion effect and also propose several different methods, as extra increase N-type layer, adopt Sapphire Substrate or etched substrate etc.Refer to Fig. 1, be shown as the structural representation of horizontal super junction-semiconductor device in prior art, as shown in the figure, the structure of described super junction-semiconductor device comprises: P type substrate 11, on P type substrate 11, be provided with super-junction structure 12 and P type tagma 13, the 121HeNXing district, p type island region 122 that super-junction structure 12 is distributed alternately by connection source-drain area direction forms, and is provided with N-type source region 14, P type body contact zone 15 and gate oxide 16 above P type tagma 13, is provided with N-type drain region 17 above super-junction structure 12.Because above-mentioned transversary is more conducive to the integrated application of high-density power of new generation, it is the focus of contemporary power device research.
But super-junction structure has also brought new problem for transversal device: the first, in the desirable P that can exhaust completely, N post district technique, be difficult to form; Second, substrate participates in exhausting of Chao Jiezhu district and causes substrate-assisted depletion effect, and the width of depletion layer is not at the drain terminal of device to the diverse location of source direction etc., this has just brought the problem of drift region Electric Field Distribution inequality, need to be optimized device making technics and structure.
Summary of the invention
The shortcoming of prior art, the object of the present invention is to provide super junction device of a kind of embedded many P island N raceway groove and preparation method thereof, for solving the problem of prior art drift region Electric Field Distribution inequality in view of the above.
For achieving the above object and other relevant objects, the invention provides the preparation method of the super junction device of a kind of embedded many P island N raceway groove, described preparation method at least comprises the following steps:
1) provide semi-conductive substrate, by N-type Implantation, in described Semiconductor substrate, prepare one deck N-type drift region; One mask plate that offers the many groups of Implantation windows that are arranged in parallel is provided, and described many group Implantation windows reduce successively from a side trend opposite side of described mask plate;
2) to B Implanted ion in described N-type drift region and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of described mask plate;
3) by described Semiconductor substrate annealing, with a plurality of island P district that forms apart from one another by and be arranged in parallel in described N-type drift region, and respectively You Qi one end, this island P district diminishes towards other end linearity;
4) on described N-type drift region and the stub end that closes on described island P district prepare P type tagma, and prepare N-type source region, P type body contact zone and gate oxide above described P type tagma; On described N-type drift region and the little head end that closes on described island P district prepare N-type drain region.
In preparation method's of the present invention step 2) in, by repeatedly repeating to B Implanted ion in described N-type drift region and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of described mask plate, and through described step 3) in after annealing, with in described N-type drift region, form a plurality of apart from one another by and be laterally arranged in parallel and island P district that parallel longitudinal is arranged.
Described Semiconductor substrate is body silicon substrate or SOI substrate.
Described N-type drift region and island P district are formed in the top layer silicon of described SOI substrate.
P island structure from large to small in the direction of ChaoNXing drain region, Wei CongNXing source region, described island P district.
The present invention also provides a kind of embedded many P island N raceway groove super junction device, comprise: Semiconductor substrate, be formed on the N-type drift region in described Semiconductor substrate, be positioned at described N-type drift region one side and include the P type tagma of N-type source region, P type body contact zone and gate oxide, and be positioned at the N-type drain region on the opposite side of described N-type drift region, wherein, in described N-type drift region, be formed with a plurality of apart from one another by and the island P district that is arranged in parallel, and respectively ChaoNXing drain region, YouNXing source region, this island P district direction linearity diminishes.
Preferably, a plurality of island P district forming in described N-type drift region apart from one another by and be laterally arranged in parallel and parallel longitudinal is arranged.
Preferably, described Semiconductor substrate is body silicon substrate or SOI substrate.
Preferably, described N-type drift region and island P district are formed in the top layer silicon of described SOI substrate.
Preferably, P island structure from large to small in the direction of ChaoNXing drain region, Wei CongNXing source region, described island P district.
As mentioned above, super junction device of embedded many P of the present invention island N raceway groove and preparation method thereof, is directly by Implantation, in N-type drift region, to form a plurality of embedded island P districts.Embedded island P district around any one direction is N-type, exhaust between the two, because under high pressure substrate-assisted depletion effect effect strengthens successively from source to drain terminal, therefore island P district correspondingly from source to drain terminal direction from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating, finally reach charge balance, and then solved the problem of drift region Electric Field Distribution inequality in prior art.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of horizontal super junction-semiconductor device in prior art.
Fig. 2, Fig. 4 and Fig. 5 are shown as the view that the present invention prepares embedded many P island N raceway groove super-junction structure.
Fig. 3 is shown as the mask plate structure schematic diagram using in preparation method of the present invention.
Fig. 6 is shown as the super junction device structural representation of the embedded many P of the present invention island N raceway groove.
Fig. 7 is shown as another execution mode schematic diagram of preparation method of the present invention.
Element numbers explanation
11 P type substrates
12 super-junction structures
121 p type island regions
122NXing district
13,24 P type tagmas
14,25 N-type source regions
15,26 P type body contact zones
16,27 gate oxides
17,28 N-type drain regions
21 Semiconductor substrate
22 N-type drift regions
23 island P districts
3 mask plates
31 Implantation windows
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 2 to Fig. 7.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment mono-
The preparation method who the invention provides the super junction device of a kind of embedded many P island N raceway groove, this preparation method comprises the following steps:
In step 1) in, semi-conductive substrate 21 is provided, by N-type Implantation, in described Semiconductor substrate 21, prepare one deck N-type drift region 22; Particularly, described Semiconductor substrate 21 is body silicon substrate or SOI substrate.Refer to Fig. 2, as shown in the figure, in the present embodiment, the Semiconductor substrate 21 of take temporarily describes as SOI substrate as example, described N-type drift region 22 is formed in the top layer silicon of described SOI substrate, particularly, in the top layer silicon of described SOI substrate, mix the N-type ion (as phosphorus, arsenic, antimony etc.) of V group element, make it to replace the position of silicon atom in lattice to form N-type drift region 22.
Then, one mask plate 3 that offers the many groups of Implantation windows 31 that are arranged in parallel is provided, described many group Implantation windows 31 reduce successively from a side trend opposite side of described mask plate 3, and a side trend opposite side shield portions of described mask plate 3 increases successively.Refer to Fig. 3, be shown as the mask plate structure schematic diagram using in preparation method of the present invention.
In step 2) in, to B Implanted ion in described N-type drift region 22 and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of described mask plate 3; Refer to Fig. 4, by an Implantation window 31 1 side trend opposite sides, reduce successively, and the mask plate that shield portions increases successively, is used to form the boron Implantation of many P island structure in N-type drift region 22, to reach the object of the CONCENTRATION DISTRIBUTION of controlling boron ion.
In step 3) in, by step 2) in Semiconductor substrate 21 annealing of B Implanted ion, with a plurality of island P district 23 that forms apart from one another by and be arranged in parallel in described N-type drift region 22, and respectively 23You Qi one end, this island P district diminishes towards other end linearity, refers to Fig. 5.
In step 4) in, on described N-type drift region 22 and the stub end that closes on described island P district 23 prepare P type tagma 24, and prepare N-type source region 25, P type body contact zone 26 and gate oxide 27 above described P type tagma 24; On described N-type drift region 22 and the little head end that closes on described island P district 23 prepare N-type drain region 28.Refer to Fig. 6, described island P district 23 is P island structure from large to small 28 directions of 25ChaoNXing drain region, N-type source region, the stub end of this P island structure closes on described P type tagma 24, the little head end of this P island structure closes on described N-type drain region 28, because any one direction around embedded island P district 23 is N-type, exhaust between the two, and because under high pressure substrate-assisted depletion effect effect strengthens successively from source to drain terminal, therefore island P district 23 correspondingly from source to drain terminal direction from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating, finally reach charge balance.
Embodiment bis-
The present embodiment and step 1 in above-described embodiment one) and step 4) identical, so it will not go into details, in the step 2 in this enforcement, by repeatedly repeating to B Implanted ion in described N-type drift region 22 and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of described mask plate 3, and in step 3) in annealed, and then can in described N-type drift region 22, form a plurality of apart from one another by and be laterally arranged in parallel and island P district 23 that parallel longitudinal is arranged, be as shown in Figure 7.
Embodiment tri-
The present invention also provides a kind of embedded many P island N raceway groove super junction device, refer to Fig. 6, be shown as the super junction device structural representation of the embedded many P of the present invention island N raceway groove, as shown in the figure, the super junction device of described embedded many P island N raceway groove comprises: Semiconductor substrate 21, be formed on the N-type drift region 22 in described Semiconductor substrate 21, be positioned at the P type tagma 24 of described N-type drift region 22 1 sides, and be positioned at the N-type drain region 28 on 22 opposite sides of described N-type drift region, on described P type body 24, include N-type source region 25, P type body contact zone 27 and gate oxide 27.
In described N-type drift region 22, be formed with a plurality of apart from one another by and the island P district 23 that is arranged in parallel, and respectively 25ChaoNXing drain region, 23YouNXing source region, this island P district 28 direction linearities diminish.Described Semiconductor substrate 21 is body silicon substrate or SOI substrate.
In concrete preparation process, described N-type drift region 22 is to form by B Implanted ion and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of the mask plate of default figure.Refer to Fig. 4, the mask plate 3 of described default figure offers the many groups of Implantation windows 31 that are arranged in parallel, described many group Implantation windows 31 reduce successively from a side trend opposite side of described mask plate 3, and a side trend opposite side shield portions of described mask plate 3 increases successively.; in the process of B Implanted ion, by an Implantation window 31 1 sides trends opposite sides, reduce successively, and the mask plate that increases successively of shield portions; be used to form the boron Implantation of many P island structure in P type drift region 22, to reach the object of the CONCENTRATION DISTRIBUTION of controlling boron ion.
In the present embodiment, the Semiconductor substrate 21 of take temporarily describes as SOI substrate as example, described N-type drift region 22 is formed in the top layer silicon of described SOI substrate, particularly, in the top layer silicon of described SOI substrate, mix V group element (as phosphorus, arsenic, antimony etc.), make it to replace the position of silicon atom in lattice to form N-type drift region 22.Described N-type drift region 22 and island P district 23 are formed in the top layer silicon of described SOI substrate.Described island P district 23 is P island structure from large to small 28 directions of 25ChaoNXing drain region, N-type source region, the stub end of this P island structure closes on described P type tagma 24, the little head end of this P island structure closes on described N-type drain region 28, because any one direction around embedded island P district 23 is N-type, exhaust between the two, and because under high pressure substrate-assisted depletion effect effect strengthens successively from source to drain terminal, therefore island P district 23 correspondingly from source to drain terminal direction from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating, finally reach charge balance.
In another embodiment, a plurality of island P district 23 forming in described N-type drift region 22 apart from one another by and be laterally arranged in parallel and parallel longitudinal is arranged.
In sum, super junction device of embedded many P of the present invention island N raceway groove and preparation method thereof, is directly by Implantation, in N-type drift region, to form a plurality of embedded island P districts.Embedded island P district around any one direction is N-type, exhaust between the two, because under high pressure substrate-assisted depletion effect effect strengthens successively from source to drain terminal, therefore island P district correspondingly from source to drain terminal direction from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating, finally reach charge balance, and then solved the problem of drift region Electric Field Distribution inequality in prior art.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (6)
1. a preparation method for the super junction device of embedded many P island N raceway groove, is characterized in that, described preparation method at least comprises the following steps:
1) provide semi-conductive substrate, by N-type Implantation, in described Semiconductor substrate, prepare one deck N-type drift region; One mask plate that offers the many groups of Implantation windows that are arranged in parallel is provided, and described many group Implantation windows reduce successively from a side trend opposite side of described mask plate;
2) to B Implanted ion in described N-type drift region and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of described mask plate;
3) by described Semiconductor substrate annealing, with a plurality of island P district that forms apart from one another by and be arranged in parallel in described N-type drift region, and respectively You Qi one end, this island P district diminishes towards other end linearity;
4) on described N-type drift region and the stub end that closes on described island P district prepare P type tagma, and prepare N-type source region, P type body contact zone and gate oxide above described P type tagma; On described N-type drift region and the little head end that closes on described island P district prepare N-type drain region.
2. the preparation method of the super junction device of embedded many P according to claim 1 island N raceway groove, it is characterized in that: in described step 2) in, by repeatedly repeating to B Implanted ion in described N-type drift region and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of described mask plate, and through described step 3) in after annealing, in described N-type drift region, form a plurality of apart from one another by and be laterally arranged in parallel and island P district that parallel longitudinal is arranged.
3. the preparation method of the super junction device of embedded many P according to claim 1 island N raceway groove, is characterized in that: described Semiconductor substrate is body silicon substrate or SOI substrate.
4. the preparation method of the super junction device of embedded many P according to claim 3 island N raceway groove, is characterized in that: described N-type drift region and island P district are formed in the top layer silicon of described SOI substrate.
5. according to the preparation method of the super junction device of embedded many P island N raceway groove described in claim 1,2 or 4, it is characterized in that: P island structure from large to small in the direction of ChaoNXing drain region, Wei CongNXing source region, described island P district.
6. the super junction device of embedded many P island N raceway groove of preparing according to the preparation method described in claim 1-5 any one, it is characterized in that, comprise: Semiconductor substrate, be formed on the N-type drift region in described Semiconductor substrate, be positioned at described N-type drift region one side and include N-type source region, the P type tagma of P type body contact zone and gate oxide, and be positioned at the N-type drain region on the opposite side of described N-type drift region, wherein, in described N-type drift region, be formed with a plurality of apart from one another by and the island P district that is arranged in parallel, described N-type drift region is to form by B Implanted ion and by the CONCENTRATION DISTRIBUTION of blocking to control boron ion of the mask plate of default figure, and respectively ChaoNXing drain region, YouNXing source region, this island P district direction linearity diminishes, a plurality of island P district forming in described N-type drift region apart from one another by and be laterally arranged in parallel and parallel longitudinal is arranged, P island structure from large to small in the direction of ChaoNXing drain region, Wei CongNXing source region, described island P district, described Semiconductor substrate is body silicon substrate or SOI substrate, described N-type drift region and island P district are formed in the top layer silicon of described SOI substrate.
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| CN102969244B (en) * | 2012-12-11 | 2015-03-25 | 中国科学院上海微系统与信息技术研究所 | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof |
| CN103579351A (en) * | 2013-11-22 | 2014-02-12 | 电子科技大学 | LDMOS (laterally diffused metal oxide semiconductor) device provided with super-junction buried layer |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
| CN108447787A (en) * | 2018-03-20 | 2018-08-24 | 重庆大学 | A kind of transverse direction super-junction structure gallium nitride HEMT device and its manufacturing method |
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| CN101916780A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | LDMOS device with multilayer super-junction structure |
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| WO1998020562A1 (en) * | 1996-11-05 | 1998-05-14 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region and method of making the same |
| CN101834207A (en) * | 2010-04-27 | 2010-09-15 | 上海北京大学微电子研究院 | Double-diffusion metal oxide semiconductor field effect tube structure and manufacturing method thereof |
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