CN100370625C

CN100370625C - Integrated high-voltage P-type LDMOS transistor structure and production thereof

Info

Publication number: CN100370625C
Application number: CNB2005100961620A
Authority: CN
Inventors: 庄奕琪; 李小明; 张丽; 邓永洪
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2005-10-14
Filing date: 2005-10-14
Publication date: 2008-02-20
Anticipated expiration: 2025-10-14
Also published as: CN1779987A

Abstract

The present invention discloses the structure of an integrated high-voltage LDMOS transistor and a method for preparing the integrated high-voltage LDMOS transistor. A buried layer 2 is arranged between a P-type substrate 1 and an N-type epitaxial layer 2, a field oxide layer 9 arranged between a source region and a drain region on the epitaxial layer is used as a thick grid oxide layer on which an N-type polysilicon gate 8 is arranged, and the extended part of the thick gate oxide layer is a field plate 12. A low-concentration P-type region 5 is arranged in the drain region, and a P+ region 7D is arranged in the P-type region, wherein both sides of the P+ region are provided with P-type drift regions 4D, the center of the source region is provided with an N+ contact region 6 whose both sides are provided with P+ regions 7S, and one side of each of the P+ regions is provided with a P-type drift region 4S. The present invention has the preparing procedure that the buried layer is injected, the epitaxial layer grows, the field oxidation of the epitaxial layer is performed, and the low-concentration P-type region of the drain region, the N+ contact region of the source region, the P + region of the drain region, and the P+ region of the source region are sequentially injected on the epitaxial layer. The present invention has the advantage of high breakdown voltage, and can be used for high-voltage power integrated circuits.

Description

High-voltage P-type LDMOS transistor structure that can be integrated and preparation method thereof

Technical field

The present invention be a kind of be applied to high-voltage power integrated circuit can be integrated the structural design and the preparation method of high-voltage P-type LDMOS transistor of epitaxy technique.

Background technology

At present, the high-voltage power integrated circuit technology is widely used and develops, as is applied to the fields such as driving of automatic test equipment, main exchange switch, linear power integrated circuit, Electric Machine Control, power control, integrated high voltage amplifier, flat panel display.

In high-voltage power integrated circuit, generally high voltage power device and low pressure numeral or analog circuit are integrated in on the chip piece, therefore require high tension apparatus on manufacturing process, to want compatible, and wish not occupy the requirement that performance under the situation of too big area reaches circuit at high tension apparatus, therefore, the quality of the design of high tension apparatus will directly influence the quality of chip performance.Ldmos transistor is the how sub-device of the lateral channel of high-frequency and high-voltage and little electric current, has higher puncture voltage (a few hectovolt) and short characteristics such as (nanosecond) switching time, can satisfy the requirement of power integrated circuit mesohigh device.

Domestic for high-voltage LDMOS transistor done some research, proposed some new structures, but major part concentrates on all on the p-n technology.For example number of patent application is: but 02112705 disclosed be exactly the ldmos transistor that a kind of flat panel display chip for driving of compatibility standard body silicon low voltage CMOS technology is used, its structure is the dark N type trap of preparation on P type substrate, preparation P type drift region in this dark N type trap, but, to accomplish that therefore the above withstand voltage device of 100V is relatively more difficult because this structure will spread very dark trap difficulty when technology realizes bigger.

And the load current of extension ldmos transistor in ldmos transistor along raceway groove and drift region lateral flow to contact point, parallel with silicon face, therefore can obtain than the higher withstand voltage very thick epitaxial loayer that need not, the dark expansion with the difficulty of isolating reduces, but to realize integratedly with present this existing ldmos transistor structure, certain difficulty is arranged on technology.

The content of invention

The purpose of this invention is to provide a kind of high-voltage P-type LDMOS transistor structure that can be integrated and preparation method thereof, to solve the integration problem of ldmos transistor.

The object of the present invention is achieved like this:

Device of the present invention is to be provided with N type extension on P type substrate, on N type extension, be provided with drain region and source region, be provided with buried regions between P type substrate and N type extension, be provided with field oxide as thick grating oxide layer between source, drain region, this thick grating oxide layer is provided with the N type polysilicon bar; Be provided with the low concentration p type island region in the drain region, be provided with heavily doped P+ district in this p type island region, the both sides in this P+ district are equipped with the P type drift region in drain region; Be provided with heavily doped N+ contact zone in the middle of the source region, the both sides of this N+ contact zone are equipped with heavily doped P+ district, one side the P type drift region that respectively is provided with the source region in each P+ district.

Above-mentioned P type ldmos transistor structure, wherein the prolongation of polysilicon gate is as field plate, be implemented in improve under the situation that does not increase mask plate withstand voltage.

Preparation of devices method of the present invention is as follows:

At first get P type silicon single crystal and make substrate, and on this substrate, make n type buried layer; Then at the epitaxial loayer of the superficial growth N of substrate type, and on epitaxial loayer the P type drift region in injection source, drain region; Then at superficial growth one deck thick field oxide layer of the epitaxial loayer of N type, and on thick field oxide layer deposit and etch polysilicon grid; Then on epitaxial loayer, inject the p type island region of the low concentration in drain region, the N+ contact zone in source region, the P+ district of source-drain area successively; Afterwards, anneal, deposit boron-phosphorosilicate glass, contact hole photoetching, deposit aluminium and anti-carve aluminium, passivation, alloy.

The present invention has following advantage

1, the present invention is owing to use than the source region of low doping concentration P field implanted layer as ldmos transistor, the drift region in drain region, thereby can improve the withstand voltage of device well, the horizontal withstand voltage of device depends primarily on the length and the concentration of drift region.

2. the present invention can improve withstand voltage under the situation that does not increase mask plate owing to adopt the prolongation polysilicon gate to do field plate.

3. the present invention is owing to do the boron injection of low concentration in the drain region, and this layer has increased the junction depth of drain region doping and the radius of curvature of knot as the diffusing protection layer, has reduced the concentration gradient that drain region P+ mixes, thereby has improved the puncture voltage of drain region and N extension.

4. the present invention is owing to adopt field oxide as gate oxide, so can in device fabrication processes, can effectively reduce the plate number, reduce cost, simultaneously, can make the withstand voltage scope of gate source voltage reach hundreds of volts, more wide applications is arranged in high-voltage power integrated circuit.

5. the present invention makes the method for device, easy and extension low voltage CMOS device and low voltage dipole device compatibility.

Description of drawings

Fig. 1 is a longitudinal profile structure chart of the present invention

Fig. 2 is the procedure chart that the present invention makes device

Fig. 3 is the source drain breakdown curve chart with the device of the present invention of MEDICI emulation

Embodiment

Below in conjunction with accompanying drawing the present invention is described in further detail:

With reference to Fig. 1, structure of the present invention, comprise P type substrate 1, N type extension 3, be provided with buried regions 2 between P type substrate and N type extension, be provided with drain region and source region on N type extension 3, the drain region is provided with low concentration p type island region 5 on the N extension, the inside of this low concentration p type island region 5 is provided with heavily doped P type layer 7D, and both sides are equipped with the P type drift region 4D in drain region; Be provided with heavily doped N type district 6 in the middle of the source region, both sides are provided with heavily doped p type island region 7S, are provided with the P type drift region 4S in source region on the both sides of this heavily doped p type island region; Be provided with field oxide 9 as thick grid oxygen between source, drain region, thick grid oxygen is provided with N type polysilicon bar 8, and the prolongation 12 of this polysilicon gate 8 is as field plate; Surface at field oxide 9 and polysilicon gate 8 is equipped with boron-phosphorosilicate glass 10; In the source, the surface, drain region all is carved with contact hole, is equipped with aluminum metal 11 in the contact hole.

With reference to Fig. 2, the process of preparation device of the present invention is as follows:

One. getting resistivity is P type＜100 of 5～10 Ω cm〉the crystal orientation silicon single crystal does substrate 1;

Two. on substrate 1, carry out the n type buried layer photoetching, make n type buried layer 2 by injecting stilba matter then;

Three. growth thickness is the N type epitaxial loayer 3 of 12um on substrate 1;

Four. make P type place on epitaxial loayer 3, promptly at first carry out the photoetching of P field, carry out P field boron then and inject, peak concentration is 1 * 10 ¹⁶Cm ^-3, joint is 3um deeply, has formed drift region, the source region 4S and drift region, the drain region 4D of ldmos transistor;

Five. carrying out an oxidation on epitaxial loayer 3 surfaces, is the field oxide 9 of 10000 dusts with the LOCOS technology layer thickness of growing;

Six. at epitaxial loayer 3 surface deposition thickness is the N type polysilicon of 800 dusts, and carries out photoetching, forms the polysilicon gate 8 and the prolongation 12 thereof of ldmos transistor;

Seven. make low concentration p type island region 5 on epitaxial loayer 3 surfaces, promptly at first carry out the photoetching of low concentration p type island region 5, carry out boron then and inject, carry out boron again and advance, the joint after the propelling is 3um deeply, and peak concentration is 5 * 10 ¹⁶Cm ^-3, the diffusing protection ring in formation ldmos transistor drain region;

Eight. make the N+ contact zone 6 in the source region of ldmos transistor on epitaxial loayer 3 surfaces, promptly at first carry out the photoetching of N+ contact zone, the phosphorus that carries out the N+ contact zone then injects, and peak concentration is 1 * 10 ²⁰Cm ^-3, joint is 0.6um deeply;

Nine. make the P+ district on epitaxial loayer 3 surfaces, promptly at first carry out the photoetching of P+ district, carry out P+ boron then and inject, peak concentration is 1 * 10 ²⁰Cm ^-3, joint is 0.6um deeply, forms ldmos transistor source region P+ district 7S and drain region P+ district 7D;

Ten. carry out the ion implantation annealing, promptly anneal under nitrogen atmosphere, the foreign ion that source-drain area is injected activates, and source-and-drain junction is advanced;

11. carry out successively on epitaxial loayer 3 surfaces: deposit boron-phosphorosilicate glass 10 → backflow boron-phosphorosilicate glass is made surperficial planarization → lithography contact hole → deposit aluminium 11 → photoetching aluminium and is formed connection → passivation layer silicon nitride deposition → carry out at last alloy;

The step of above photoetching all adopts conventional processing procedure, i.e. gluing → add mask plate → exposure → development → corrosion.

Effect of the present invention can prove by following test and emulation:

1. the ldmos transistor single tube in the technology controlling and process unit is tested, its condition is:

Room temperature T=300K, gate source voltage are zero, and when drain current reached 1um, getting the voltage that the drain-source utmost point applied was puncture voltage.

Test result shows that puncture voltage reaches 135 volts.

2. be in the plasma flat-plate demonstration high pressure addressing driving chip of 100V at the maximum working voltage that is integrated with LDMOS, performance to entire chip is tested, test result is: withstand voltage surpasses 100V, the output voltage of every road power output part can reach 90V, the output current on every road is 60mA, and all parameters meet the requirements.

3. adopt the device simulation software MEDICI of international specialty that this device is carried out emulation, emulation mode is as follows:

Source electrode connecting to neutral current potential, grid connecting to neutral current potential, the current potential of drain electrode raises gradually from zero.Get drain current densities and reach 1 * 10 ^-9Source-drain voltage during A/um is a puncture voltage.

Simulation curve as shown in Figure 3, wherein to be connect voltage unit by drain electrode be V to abscissa, ordinate is the logarithm of drain line current density, unit is A/um, as shown in Figure 3, puncture voltage reaches 160V.

Claims

One kind can be integrated the structure of high-voltage P-type LDMOS transistor, be on P type substrate (1), to be provided with N type extension (3), on N type extension (3), be provided with drain region and source region, it is characterized in that:

Be provided with buried regions (2) between P type substrate (1) and the N type extension (3);

Be provided with field oxide (9) as thick grating oxide layer between source, drain region, this thick grating oxide layer is provided with N type polysilicon bar (8);

Be provided with low concentration p type island region (5) in the drain region, this p type island region (5) lining is provided with heavily doped P+ district (7D), and the both sides in this P+ district (7D) are equipped with the P type drift region (4D) in drain region;

Is provided with heavily doped N+ contact zone (6) in the middle of the source region, the both sides of this N+ contact zone (6) are equipped with heavily doped P+ district (7S), each P+ district (7S) one side the P type drift region (4S) that respectively is provided with the source region.
2. the structure of high-voltage P-type LDMOS transistor that can be integrated according to claim 1, the prolongation (12) that it is characterized in that adopting polysilicon gate (8) is as field plate.
3. method for preparing claim 2 transistor arrangement, carry out according to the following procedure:

At first get P type silicon single crystal and make substrate (1), and on this substrate, make n type buried layer (2); Then at the epitaxial loayer (3) of the superficial growth N of substrate (1) type, and on this epitaxial loayer the P type drift region (4S, 4D) in injection source, drain region; Then at superficial growth one deck thick field oxide layer (9) of the epitaxial loayer (3) of N type, and on this thick field oxide layer deposit and etching polycrystalline brick grid (8) and prolongation (12) thereof; Then on epitaxial loayer (3), inject the p type island region (5) of the low concentration in drain region, the N+ contact zone (6) in source region, the P+ district (7D) in drain region, the P+ district (7S) in source region successively.