CN102664181B - Ultrahigh voltage BCD (Bipolar CMOS DMOS) process and ultrahigh voltage BCD device - Google Patents
Ultrahigh voltage BCD (Bipolar CMOS DMOS) process and ultrahigh voltage BCD device Download PDFInfo
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Abstract
The invention provides an ultrahigh voltage BCD process which can be used for realizing integration of a plurality of semiconductor devices. An ultrahigh voltage BCD device comprises a high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) manufactured on an N-type extension, a high-voltage floating tub structure, a low-voltage PMOS (P-channel Metal Oxide Semiconductor) transistor, a low-voltage NMOS (N-channel Metal Oxide Semiconductor) transistor, a low-voltage VNPN transistor, a VDNMOS, a Zener diode, a low-voltage NLDMOS, an LPNP, and a symmetrical drain extension EDPMOS. The process has an N-type buried layer which penetrates through a P-type substrate and an N-type extension, a PN junction through isolation structure is formed between the high-voltage structure and the low-voltage structure. The high-voltage BCD process integrates devices of a plurality of voltage levels, wherein the high-voltage floating tub structure can provide process platform support for application of a bridge type circuit.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, relate in particular to a kind of superhigh pressure BCD semiconductor technology and superhigh pressure BCD device.
Background technology
BCD is a kind of monolithic integrated technique technology, and this technology can be made bipolar transistor (Bipolar Junction Transistor), CMOS and DMOS device on same chip.BCD technique not only combines the advantage of bipolar device high transconductance, strong load driving force and the high and low power consumption of CMOS integrated level, and integrated enter high withstand voltage DMOS power device.Because DMOS has the characteristic of high pressure and speed-sensitive switch simultaneously, thereby to be operated in the power management chip of BCD technique manufacture be under high pressure and high frequency, is the ideal technology of manufacturing high-performance electric source chip.Adopt the monolithic integrated chip of BCD technique manufacture can improve systematic function, save the encapsulation overhead of circuit, and there is better reliability.The main application fields of BCD technique is power management (power supply and battery control), display driver, the fields such as automotive electronics, Industry Control.Due to the continuous expansion of the application of BCD technique, more and more higher to the requirement of BCD technique.At present, BCD technique is mainly towards high pressure, high power, high density direction differentiation development.
In high voltage integrated circuit (HVIC) field, superhigh pressure integrated circuit HVIC between 300V-800V is very important part, owing to thering is high-reliability, integrated, and the outstanding advantages such as energy-efficient is subject to industry favor, its product is widely used in energy-saving illumination, capability correction, the Switching Power Supply of consumer electronics and PC, the aspects such as motor driving.And the Major Difficulties of the realization of such HVIC and key are the high-pressure process platforms that its design is supported.
300V-800V ultrahigh voltage BCD technology is except the integrated superhigh pressure DMOS of needs, CMOS and bipolar transistor; conventionally also need voltage stabilizing Zener diode; the devices such as high value polysilicon resistance and high pressure JFET; often need high pressure (350V-800V); middle pressure (10V-40V); low pressure (5V) all integrates, all very high to the requirement of the integrated compatibility of the technique of device and the isolation of different voltage levvl.In addition, according to the concrete application demand of HVIC circuit, technique is also had to many special requirements, as the current electric ballast for energy-saving illumination and motor driving application, all adopt the bridge circuit topological structure of half-bridge or full-bridge, the drive circuit of the high side power pipe of half-bridge and full-bridge need to have voltage to arrive the unsteady current potential translation circuit of a few hectovolt high pressure at 0V, the structures such as high pressure floating basin isolation structure and bootstrap diode, this just has higher requirement to High voltage BCD process.
Summary of the invention
Technical problem to be solved by this invention has been to provide the device of a kind of superhigh pressure BCD semiconductor technology and ultrahigh voltage BCD technology realization, to solve the integration problem of multiple voltage horizontal device.
In order to solve the problems of the technologies described above, technical scheme of the present invention is: a kind of superhigh pressure BCD semiconductor technology is provided, and the integrated device of its realization comprises: EDPMOS is extended in the high-voltage LDMOS, high pressure floating basin structure, low pressure PMOS pipe, low pressure NMOS pipe, low pressure VNPN pipe, VDNMOS, Zener diode, low pressure NLDMOS, LPNP and the symmetrical drain electrode that are made in N-type extension.This technique has n type buried layer, and described n type buried layer runs through described P type substrate and described N-type extension, is formed with PN junction to logical isolation structure between high-low pressure structure; Described high pressure floating basin structure comprises that multiple P-top encircle and be positioned at high pressure N+ and the n type buried layer of N trap, and described multiple P-top rings and described high pressure N+ are all positioned at N-type extension, and described high pressure floating basin structure Yi Qi center is symmetrical.
Further, described high-voltage LDMOS comprises drain region and the P type PBD that multiple P-top rings, first kind high pressure N+ level form, in described P type PBD, include the source electrode of Equations of The Second Kind high pressure N+ formation and form the Yuan Lou P+ district that PBD ohmic contact is drawn, described Equations of The Second Kind high pressure N+ contacts with described Yuan Lou P+ district, and described Yuan Lou P+ district all exposes to contact window, described Equations of The Second Kind high pressure N+ part exposes to contact window, symmetrical centered by the drain electrode that described high-voltage LDMOS forms by described first kind high pressure N+ level.
Further, described low pressure VNPN pipe, in its N trap, there is high pressure N+ as collector electrode, in the base stage that its P type PBD forms, include Equations of The Second Kind high pressure N+ level as emitter and form the Yuan Lou P+ district that PBD ohmic contact is drawn, and described Equations of The Second Kind high pressure N+ and described Yuan Lou P+ district have contact window separately.
Further, described Zener diode comprises N+, n type buried layer and multiple dark P well structure, and described multiple dark P traps are mutually overlapping to reduce anode dead resistance, and overlapping with described n type buried layer respectively.
Further, described low pressure NLDMOS, in its P type PBD, include the source of Equations of The Second Kind high pressure N+ level formation and form the Yuan Lou P+ district that PBD ohmic contact is drawn, in its N-type lightly mixed drain area, there is the drain electrode that first kind high pressure N+ forms, described P type PBD and described N-type lightly mixed drain area are all included in N trap, and described low pressure NLDMOS is symmetrical centered by described first kind high pressure N+.
Further, described LPNP include low pressure source leak N+ as the base of N trap draw, P type PBD is as emitter and collector, described low pressure source is leaked N+ and P type PBD is all included in N trap, and described LPNP is symmetrical centered by its emitter.
Further, the drain electrode of described symmetry extend EDPMOS include low pressure source leak N+ as N trap draw, P type PBD extends as drain electrode, in described P type PBD, comprises active LouP+ district, low pressure source is leaked N+ and P type PBD is all included in N trap.
Further, described PN junction comprises overlapping dark P trap and p type buried layer mutually to logical isolation structure.
Further, the doping of described dark P trap and p type buried layer connects N-type extension.
Further, the thickness of described N-type extension is 5 ~ 25 microns.
The invention provides a kind of ultrahigh voltage BCD technology, comprise the steps: to inject by antimony on P type silicon substrate and phosphorus injection formation n type buried layer; B Implanted forms p type buried layer; Growth N-type extension is done the photoetching of P isolation well in described extension and dark P isolation well injects, and advances, and the dark P trap of formation and the doping of p type buried layer connect described extension and have overlapping; The hard mask oxide layer of growing, does the photoetching of N trap, and wet etching goes out N trap window, carries out N trap phosphorus and injects; Do the photoetching of P trap, wet etching goes out P trap window, carries out P trap boron and injects; Do active mask, wet etching goes out high voltage active region, heat growth high-pressure area gate oxide; Do dual gate oxide mask, wet etching goes out CMOS active region, heat growth CMOS gate oxide, depositing polysilicon doping; Do polysilicon photoetching, etching, and thermal growth oxide layer; Do P-top photoetching, carry out P-top injection, and pick into; Do PBD photoetching, carry out P-body injection, and pick into; Do emitter photoetching, carry out high pressure N+ injection, leak in the source that forms high pressure, the emitter of bipolar transistor and Zener diode source class; Do CMOS P+ layer photoetching, carry out boron injection, form CMOS source/drain electrode; Do CMOS N+ layer photoetching, carry out phosphorus injection, form CMOS source/drain electrode; The low piezodielectric oxide layer of deposit level, deposit silicon nitride barrier layer, the thick oxide isolation layer of deposit high pressure, anneal, activation of source leaks the impurity injecting simultaneously, does the photoetching of field plate level, and the thick oxide isolation layer of wet etching high pressure, be parked on silicon nitride, remove the silicon nitride in window;
Do the photoetching of contact hole level, the low piezodielectric oxide layer of etching forms contact hole, carries out adhesion layer titanium and barrier layer titanium nitride deposit, thermal annealing, deposited metal; Do the photoetching of metal level level, etching, and deposit passivation layer; Do the photoetching of PAD level, etch away the passivation layer of PAD window, carry out alloy technique.
Further, antimony implantation dosage is 1E15 magnitude, and phosphorus implantation dosage is 1E13 magnitude.
Further, the junction breakdown voltage between described n type buried layer and described P substrate is higher than 750v.
Superhigh pressure BCD semiconductor device provided by the invention has comprised the device of multiple voltage level, and high pressure floating basin structure wherein, can provide technique platform support for the application of bridge circuit.
Ultrahigh voltage BCD technology provided by the invention, the method of this process using P type Grown N-type extension, not only realize the integrated of multiple voltage horizontal device, and can form bridge circuit and drive necessary high pressure floating basin structure, for the application of bridge circuit provides technique platform support, in addition, this technique has extensibility, can add level to form the High voltage BCD process of multiple layer metal, also can add high resistance barrier to obtain high value polycrystalline resistor etc.
Further, while forming n type buried layer, the N+ that P injection forms after high annealing advances all encases, and has increased the PN junction radius of curvature of N+ buried regions border and P substrate by such processing.
Further, encircled by P-top, P type substrate and N-type extension, P+(can be that P-body injects or dark P isolation well injects) to realize surface high withstand voltage.
Brief description of the drawings
Fig. 1 a is high-voltage LDMOS and the high pressure floating basin cross-sectional view in the superhigh pressure BCD semiconductor device that provides of the embodiment of the present invention;
Fig. 1 b is the cross-sectional view of low pressure PMOS pipe in the superhigh pressure BCD semiconductor device that provides of the embodiment of the present invention, low pressure NMOS pipe, low pressure VNPN pipe, VDNMOS, Zener diode;
Fig. 1 c is the cross-sectional view that EDPMOS is extended in low pressure NLDMOS, LPNP in the superhigh pressure BCD semiconductor device that provides of the embodiment of the present invention and symmetrical drain electrode;
Fig. 2 is the process module schematic diagram of the ultrahigh voltage BCD technology step that provides of the embodiment of the present invention.
Embodiment
A kind of superhigh pressure BCD semiconductor device and the ultrahigh voltage BCD technology that the present invention are proposed below in conjunction with the drawings and specific embodiments are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only for convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, superhigh pressure BCD semiconductor device provided by the invention has comprised the device of multiple voltage level, and high pressure floating basin structure wherein, can provide technique platform support for the application of bridge circuit; Ultrahigh voltage BCD technology provided by the invention, the method of this process using P type Grown N-type extension, not only realize the integrated of multiple voltage horizontal device, and can form bridge circuit and drive necessary high pressure floating basin structure, for the application of bridge circuit provides technique platform support, in addition, this technique has extensibility, can add level to form the High voltage BCD process of multiple layer metal, also can add high resistance barrier to obtain high value polycrystalline resistor etc.
Fig. 1 a is high-voltage LDMOS and the high pressure floating basin cross-sectional view in the superhigh pressure BCD semiconductor device that provides of the embodiment of the present invention; Fig. 1 b is the cross-sectional view of low pressure PMOS pipe in the superhigh pressure BCD semiconductor device that provides of the embodiment of the present invention, low pressure NMOS pipe, low pressure VNPN pipe, VDNMOS, Zener diode; Fig. 1 c is the cross-sectional view that EDPMOS is extended in low pressure PMOS, low pressure NMOS, low pressure NLDMOS, LPNP and the symmetrical drain electrode in the superhigh pressure BCD semiconductor device that provides of the embodiment of the present invention.With reference to Fig. 1 a, Fig. 1 b and Fig. 1 c, the superhigh pressure BCD semiconductor device providing, this device comprises: EDPMOS12 is extended in the high-voltage LDMOS 1, high pressure floating basin structure 2, low pressure PMOS pipe 3, low pressure NMOS pipe 4, low pressure VNPN pipe 5, VDNMOS6, Zener diode 7, low pressure PMOS8, low pressure NMOS9, low pressure NLDMOS10, LPNP11 and the symmetrical drain electrode that are made in N-type extension 102, and all there is n type buried layer 103, between high-low pressure structure, be formed with PN junction to logical isolation structure 104; Described high pressure floating basin structure 2 comprises multiple P-top rings 105 and the high pressure N+107 that is positioned at N trap 106, and described multiple P-top rings 105 and described high pressure N+107 are all positioned at N-type extension 102, and described high pressure floating basin structure 2 Yi Qi centers are symmetrical.In the present embodiment, the thickness of described N-type extension 102 is 5 ~ 25 microns.
Described high-voltage LDMOS 1 comprises drain region and the P type PBD202 that multiple P-top rings 105, first kind high pressure N+201 level form, in described P type PBD202, include source electrode and Yuan Lou P+ district 109 the drawing as P type tagma of Equations of The Second Kind high pressure N+203 as LDMOS, described Equations of The Second Kind high pressure N+203 contacts with described Yuan Lou P+ district 109, symmetrical centered by the drain electrode of the LDMOS that described high-voltage LDMOS 1 forms by described first kind high pressure N+201.On P type PBD202, part is coated with high voltage grid oxidation layer 204 and polysilicon gate 205 successively.
With reference to Fig. 1 b, described low pressure PMOS pipe 3 and described low pressure NMOS pipe 4 comprise n type buried layer 103, wherein, in the N-type extension 102 of low pressure PMOS pipe 3, comprise N trap 106, in N trap 106, comprise multiple described Yuan Lou P+ district 109, wherein in two described Yuan Lou P+ districts 109, be coated with polysilicon gate 205, in the N-type extension 102 of described low pressure NMOS pipe 4, comprise P trap 108, in P trap 108, comprise N-type lightly doped drain 401 and high pressure N+107, wherein, in N-type lightly doped drain 401, include low pressure source and leak N+402; In the N-type extension 102 of described low pressure VNPN pipe 5, comprise N trap 106 and P type PBD202, in its N trap 106, there is high pressure N+107 as collector electrode, in the base stage that its P type PBD202 forms, include Equations of The Second Kind high pressure N+203 and draw as ohmic contact as emitter and Yuan Lou P+ district 109; In the N-type extension 102 of described VDNMOS6, comprise N trap 106 and multiple P type PBD202, P type PBD202 comprises that the PBD that high pressure N+107 source electrode and Yuan Lou P+ district 109 form draws.Described Zener diode 7 comprises n type buried layer 103 and multiple dark P trap 701, and described multiple dark P traps 701 are mutually overlapping, and overlapping with described n type buried layer 103 respectively, also include high pressure N+107 in N-type extension 102.
With reference to Fig. 1 c, described low pressure NLDMOS10, in its P type PBD202, including the PBD that Equations of The Second Kind high pressure N+203 forms as source electrode and Yuan Lou P+ district 109 draws, in its N-type lightly mixed drain area 401, there is high pressure N+107 as drain electrode, described P type PBD202 and described N-type lightly mixed drain area 401 are all included in N trap 106, and described low pressure NLDMOS10 is symmetrical centered by described high pressure N+107.
Further, described LPNP11 include low pressure source leak N+402 as N trap draw, P type PBD202 form collector and emitter, described low pressure source is leaked N+402 and P type PBD202 is all included in N trap 106, and described LPNP11 is symmetrical centered by described P type emitter 107; The drain electrode of described symmetry extend EDPMOS12 include low pressure source leak N+402 as N trap draw, P type PBD202 extends as drain electrode, in described P type PBD202, comprises active LouP+ district 109, low pressure source is leaked N+402 and P type PBD202 is all included in N trap 106.In Fig. 1 c, also include the PMOS of 15V and the NMOS of 15v, the low pressure PMOS pipe 3 in its structure and Fig. 1 b and the structure of low pressure NMOS pipe 4 are similar, do not repeat them here.
In the present embodiment, with reference to Fig. 1 a, Fig. 1 b and Fig. 1 c, described PN junction comprises mutually overlapping dark P trap 1041 and p type buried layer 1042 to logical isolation structure 104, and described dark P trap 1041 connects N-type extension 102 with the doping of p type buried layer 1042.
Fig. 2 is the process module schematic diagram of the ultrahigh voltage BCD technology step that provides of the embodiment of the present invention.。With reference to Fig. 2, the embodiment of the present invention provides a kind of ultrahigh voltage BCD technology, and this technique comprises the following steps:
S201, on P type silicon substrate, inject by antimony and phosphorus inject form n type buried layer;
S202, B Implanted form p type buried layer;
S203, growth N-type extension are done the photoetching of P isolation well in described extension and dark P isolation well injects, and advance, and the dark P trap of formation and the doping of p type buried layer connect described extension and have overlapping;
S204, do the photoetching of N trap, wet etching goes out N trap window, carries out N trap phosphorus and injects;
S205, do the photoetching of P trap, wet etching goes out P trap window, carries out P trap boron and injects;
S206, do active mask, wet etching goes out high voltage active region, heat growth high-pressure area gate oxide;
S207, do dual gate oxide mask, wet etching goes out CMOS active region, heat growth CMOS gate oxide, depositing polysilicon doping;
S208, do polysilicon photoetching, etching, and thermal growth oxide layer;
S209, do P-top photoetching, carry out P-top injection, and pick into;
S210, do PBD photoetching, carry out P-body injection, and pick into;
S211, do emitter photoetching, carry out high pressure N+ injection, leak in the source that forms high pressure, the emitter of bipolar transistor and Zener diode source class;
S212, do CMOS P+ layer photoetching, carry out boron injection, form CMOS source/drain electrode;
S213, do CMOS N+ layer photoetching, carry out phosphorus injection, form CMOS source/drain electrode;
S214, the low piezodielectric oxide layer of deposit level, deposit silicon nitride barrier layer, the thick oxide isolation layer of deposit high pressure, anneal, activation of source leaks the impurity injecting simultaneously, does the photoetching of field plate level, and the thick oxide isolation layer of wet etching high pressure, be parked on silicon nitride, remove the silicon nitride in window;
S215, do the photoetching of contact hole level, the low piezodielectric oxide layer of etching forms contact hole, carries out adhesion layer titanium and barrier layer titanium nitride deposit, thermal annealing, deposited metal;
S216, do the photoetching of metal level level, etching, and deposit passivation layer;
S217, do the photoetching of PAD level, etch away the passivation layer of PAD window, carry out alloy technique.
In the present embodiment, n type buried layer 103 adopts antimony and twice injection of phosphorus, antimony implantation dosage is 1E15 magnitude, phosphorus implantation dosage is 1E13 magnitude, the N-that phosphorus injection forms after high annealing advances can inject the N+ forming by antimony and all encase, increased the PN junction radius of curvature of N+ buried regions 103 borders and P substrate by such processing, the junction breakdown voltage between N+ buried regions 103 and described P substrate 101 is higher than 750v.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (13)
1. the integrated device that superhigh pressure BCD semiconductor technology realizes, it is characterized in that, device comprises: EDPMOS is extended in the high-voltage LDMOS, high pressure floating basin structure, low pressure PMOS pipe, low pressure NMOS pipe, low pressure VNPN pipe, VDNMOS, Zener diode, low pressure NLDMOS, LPNP and the symmetrical drain electrode that are made in N-type extension, described integrated device has n type buried layer, described n type buried layer runs through P type substrate and described N-type extension, is formed with PN junction to logical isolation structure between high-low pressure structure;
Described high pressure floating basin structure comprises multiple P-top rings, is positioned at high pressure N+ and the n type buried layer of N trap, and described multiple P-top rings and described high pressure N+ are all positioned at N-type extension, and described high pressure floating basin structure Yi Qi center is symmetrical.
2. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, it is characterized in that, described high-voltage LDMOS comprises multiple P-top rings, the source that first kind high pressure N+ level forms, drain region and P type PBD tagma, in described P type PBD tagma, include the Yuan Lou P+ district that the source electrode of Equations of The Second Kind high pressure N+ level formation and the ohmic contact of formation PBD are drawn, the source electrode that described Equations of The Second Kind high pressure N+ level forms contacts with described Yuan Lou P+ district, and described Yuan Lou P+ district all exposes to contact window, described Equations of The Second Kind high pressure N+ part exposes to contact window, symmetrical centered by the drain electrode that described high-voltage LDMOS forms by described first kind high pressure N+ level.
3. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, it is characterized in that, described low pressure VNPN pipe, in its N trap, there is first kind high pressure N+ collector electrode, in its P type PBD base, include the source region that Equations of The Second Kind high pressure N+ level forms and form the Yuan Lou P+ district that PBD ohmic contact is drawn, and described Equations of The Second Kind high pressure N+ and described Yuan Lou P+ district have contact window separately.
4. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, it is characterized in that, described Zener diode comprises high pressure N+, multiple dark P traps and n type buried layer, described multiple dark P trap is mutually overlapping to reduce dead resistance, and overlapping with described n type buried layer respectively.
5. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, it is characterized in that, described low pressure NLDMOS, in its P type PBD, include the source region of Equations of The Second Kind high pressure N+ level formation and form the Yuan Lou P+ district that PBD ohmic contact is drawn, in its N-type lightly mixed drain area, there is first kind high pressure N+ drain region, described P type PBD and described N-type lightly mixed drain area are all included in N trap, and described low pressure NLDMOS is symmetrical centered by described high pressure N+ drain electrode.
6. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, it is characterized in that, described LPNP include low pressure source leak N+ as the base of N trap draw, P type PBD is as emitter and collector, described low pressure source is leaked N+ and P type PBD is all included in N trap, and described LPNP is symmetrical centered by its emitter.
7. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, it is characterized in that, the drain electrode of described symmetry extend EDPMOS include low pressure source leak N+ as N trap draw, P type PBD extends as drain electrode, in described P type PBD, comprise active LouP+ district, low pressure source is leaked N+ and P type PBD is all included in N trap.
8. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, is characterized in that, described PN junction comprises overlapping dark P trap and p type buried layer mutually to logical isolation structure.
9. the integrated device that superhigh pressure BCD semiconductor technology according to claim 8 realizes, is characterized in that, the doping of described dark P trap and p type buried layer connects N-type extension and forms logical isolation.
10. the integrated device that superhigh pressure BCD semiconductor technology according to claim 1 realizes, is characterized in that, the thickness of described N-type extension is 5～25 microns.
11. 1 kinds for realizing the ultrahigh voltage BCD technology of integrated device as claimed in claim 1, it is characterized in that, comprises the steps:
On P type silicon substrate, inject by antimony and phosphorus injection formation n type buried layer;
B Implanted forms p type buried layer;
Growth N-type extension is done the photoetching of P isolation well in described extension and dark P isolation well injects, and advances, and the dark P trap of formation and the doping of p type buried layer connect described extension and have overlapping;
Do the photoetching of N trap, wet etching goes out N trap window, carries out N trap phosphorus and injects;
Do the photoetching of P trap, wet etching goes out P trap window, carries out P trap boron and injects;
Do active mask, wet etching goes out high voltage active region, heat growth high-pressure area gate oxide;
Do dual gate oxide mask, wet etching goes out CMOS active region, heat growth CMOS gate oxide, depositing polysilicon doping;
Do polysilicon photoetching, etching, and thermal growth oxide layer;
Do P-top photoetching, carry out P-top injection, and pick into;
Do PBD photoetching, carry out P-body injection, and pick into;
Do emitter photoetching, carry out high pressure N+ injection, leak in the source that forms high pressure, the emitter of bipolar transistor and Zener diode source class;
Do CMOS P+ layer photoetching, carry out boron injection, form CMOS source/drain electrode;
Do CMOS N+ layer photoetching, carry out phosphorus injection, form CMOS source/drain electrode;
The low piezodielectric oxide layer of deposit level, deposit silicon nitride barrier layer, the thick oxide isolation layer of deposit high pressure, anneal, activation of source leaks the impurity injecting simultaneously, does the photoetching of field plate level, and the thick oxide isolation layer of wet etching high pressure, be parked on silicon nitride, remove the silicon nitride in window;
Do the photoetching of contact hole level, the low piezodielectric oxide layer of etching forms contact hole, carries out adhesion layer titanium and barrier layer titanium nitride deposit, thermal annealing, deposited metal;
Do the photoetching of metal level level, etching, and deposit passivation layer;
Do the photoetching of PAD level, etch away the passivation layer of PAD window, carry out alloy technique.
12. ultrahigh voltage BCD technologies according to claim 11, is characterized in that, described antimony implantation dosage is 1E15 magnitude, and described phosphorus implantation dosage is 1E13 magnitude.
13. ultrahigh voltage BCD technologies according to claim 11, is characterized in that, the junction breakdown voltage between described n type buried layer and described P type silicon substrate is higher than 750v.
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