CN107221558B - SOI (silicon on insulator) layer variable-doping BCD (Bipolar complementary Metal oxide semiconductor) device and manufacturing method thereof - Google Patents
SOI (silicon on insulator) layer variable-doping BCD (Bipolar complementary Metal oxide semiconductor) device and manufacturing method thereof Download PDFInfo
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- 239000010703 silicon Substances 0.000 title description 4
- 230000000295 complement effect Effects 0.000 title description 2
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 238000002955 isolation Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 210000003850 cellular structure Anatomy 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
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- 239000012535 impurity Substances 0.000 claims description 8
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- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
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Abstract
The invention provides a BCD device with an SOI layer being doped variably and a manufacturing method thereof.A cellular structure comprises a substrate, an epitaxial layer, STI isolation, an oxygen buried layer, a P well, a P-type heavily doped region, an N-type heavily doped region, a DMOS source electrode, a contact electrode of a first P well, a DMOS gate electrode, a PMOS gate electrode, an NMOS gate electrode, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode, a DMOS drain electrode, a BJT base electrode, a BJT emitter electrode and a BJT collector electrode; the number of current carriers is increased when the DMOS device is in an on state, the specific on-resistance of the DMOS device is further reduced, the loss of the device is reduced, and the performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an SOI (silicon on insulator) layer variable-doping BCD (bipolar-CMOS-DMOS) device and a manufacturing method thereof.
Background
The power integrated circuit integrates a high-voltage power device, a control circuit, a peripheral interface circuit, a protection circuit and the like on the same chip, and is used as a bridge of a system signal processing part and an execution part, and has very wide application. The power integration technology is a means for implementing a power integrated circuit, and needs to implement compatibility between high voltage and low voltage, high performance, high efficiency, and high reliability on a limited chip area. Before the middle of the 20 th century and the 80 th era, power integrated circuits were mainly manufactured by bipolar technology, however, as the functional requirements of the control part are continuously improved, the power consumption and the area of the integrated circuits are larger and larger, and therefore, a BCD integration technology capable of integrating the advantages of 3 active devices is developed. The BCD process can fully play the advantages of 3 active devices such as low noise, high precision and large current density of a bipolar device, high integration and low power consumption of a CMOS device, fast switching speed and high input impedance of a DMOS device and the like, and has very wide application.
Compared with the traditional bulk silicon technology, the SOI technology has the advantages of high speed, low power consumption, high integration level, small parasitic effect, good isolation characteristic, small latch-up effect, strong radiation resistance and the like, so that the reliability and the soft error resistance of the integrated circuit are greatly improved, and the SOI technology is gradually becoming a mainstream technology for manufacturing the integrated circuit with high speed, low power consumption, high integration level and high reliability.
The BCD process integrates DMOS devices, CMOS devices, and BJT devices, and is receiving a high level of attention in the industry. The article "the semiconductor roadmap for power management in the new millennium" shows a structure similar to that shown in fig. 1, in which NMOS is fabricated in Pwell and PMOS is fabricated directly on N-epi, and since the concentration of N-epi is generally low, the structure is prone to short channel effect as the device size decreases. To avoid this problem, the article "Design and optimization of 700V HVIC technology with multi-wiring structure" shows a structure similar to that shown in FIG. 2, i.e., PMOS of CMOS device is fabricated in Nwell. However, in this method, a mask is added, which increases the cost, and is not favorable for cost saving in mass production, and it is an important task to adapt the BCD device to the size reduction of the device without adding an extra version number.
Disclosure of Invention
In view of the above disadvantages of the prior art, the present invention provides a BCD device with variable doping of SOI layer and a method for manufacturing the same, which aims to adapt the BCD device to the reduction of the device size, reduce the cost, and simultaneously reduce the specific on-resistance of the DMOS device without adding extra layout.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a BCD device with an SOI layer being doped variably comprises a cellular structure of the BCD device, wherein the cellular structure comprises a substrate, a first epitaxial layer, a second epitaxial layer, a first STI isolation, a second STI isolation, a third STI isolation, a buried oxide layer, a first P well, a third P well, a fourth P well, a DMOS source P-type heavily doped region, a third P-type heavily doped region, a fourth P-type heavily doped region, a fifth P-type heavily doped region, a DMOS source N-type heavily doped region, a DMOS drain N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, a fourth N-type heavily doped region, a fifth N-type heavily doped region, a DMOS source electrode, a contact electrode of the first P well, a gate electrode, a PMOS gate electrode, an NMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode, a BJT base electrode, a BJT emitter electrode, a BJT collector electrode, a PMOS source electrode, a PMOS collector electrode, a buried oxide layer, the second epitaxial layer is arranged on the upper surface of the first epitaxial layer, the first STI isolator is arranged on the left side of the first P well, the lower surface of the first P well is contacted with the upper surface of the buried oxide layer, the upper surface of the first P well is connected with the upper surface of the second epitaxial layer, a DMOS source P-type heavily doped region and a DMOS source N-type heavily doped region which are independent of each other are arranged in the first P well, the DMOS drain N-type heavily doped region is arranged on the right side of the first P well, the second STI isolator is arranged on the right side of the DMOS drain N-type heavily doped region, the lower surface of the second STI isolator is contacted with the upper surface of the buried oxide layer, the third P-type STI heavily doped region is arranged on the right side of the second STI heavily doped region, the fourth P-type heavily doped region is arranged on the right side of the third P-type heavily doped region, the third P well is arranged on the right side of the fourth P-type heavily doped region, and a second N-type heavily doped, the third STI is arranged on the right side of the third P well, the lower surface of the third STI is contacted with the upper surface of the buried oxide layer, the fourth P well is arranged on the right side of the third STI, a fifth P-type heavily doped region and a fourth N-type heavily doped region which are independent from each other and spaced from each other are arranged in the fourth P well, the fifth N-type heavily doped region is arranged on the right side of the fourth P well, the DMOS source electrode is arranged above the DMOS source N-type heavily doped region, the contact electrode of the first P well is arranged above the DMOS source P-type heavily doped region, the DMOS gate electrode is arranged above the first P well, the left end part of the DMOS gate electrode covers the DMOS source N-type heavily doped region and is not contacted with the DMOS source electrode, the PMOS gate electrode is arranged above the third P-type heavily doped region and the fourth P-type heavily doped region, the left end part of the PMOS gate electrode covers the third P-type heavily doped region and is not contacted, the right end part of the NMOS gate electrode is covered with a fourth P-type heavily doped region and is not contacted with a PMOS drain electrode, the NMOS gate electrode is arranged above a second N-type heavily doped region and a third N-type heavily doped region, the left end part of the NMOS gate electrode is covered with the second N-type heavily doped region and is not contacted with an NMOS drain electrode, the right end part of the NMOS gate electrode is covered with the third N-type heavily doped region and is not contacted with an NMOS source electrode, the DMOS drain electrode is arranged above the DMOS drain N-type heavily doped region, the BJT base electrode is arranged above a fifth P-type heavily doped region, the BJT emitter electrode is arranged above the fourth N-type heavily doped region, the BJT collector electrode is arranged above the fifth N-type heavily doped region, the PMOS source electrode is arranged above the third P-type heavily doped region, the PMOS drain electrode is arranged above the fourth P-type heavily doped region, and the NMOS source electrode is arranged above the third, the NMOS drain electrode is arranged above the second N-type heavily doped region.
Specifically, the third epitaxial layer 2-3 and the fourth epitaxial layer 2-4 … …, namely an nth epitaxial layer 2-N are arranged above the second epitaxial layer, wherein N is 3, 4, 5, 6 … …; the upper surface of the first P well is connected to the upper surface of the N-th epitaxial layer 2-N, where N is 3, 4, 5, 6 … ….
Specifically, the SOI layer variable-doping BCD device further comprises a P-type doping region, the upper surface of the P-type doping region is tangent to the upper surface of the second epitaxial layer, and the P-type doping region is arranged between the first P-well and the DMOS drain N-type heavily doped region.
Specifically, the SOI layer variable-doping BCD device further comprises a P-type doping region, the upper surface of the P-type doping region is connected with the upper surface of the Nth epitaxial layer 2-N, and the P-type doping region is arranged between the first P well and the DMOS drain N-type heavily doped region.
Specifically, the upper surface of the P-type doped region arranged between the first P-well and the DMOS drain N-type heavily doped region is not tangent to the upper surface of the second epitaxial layer.
Specifically, the upper surface of the P-type doped region arranged between the first P-well and the DMOS drain N-type heavily doped region is not connected to the upper surface of the N-th epitaxial layer 2-N.
Specifically, the PMOS source electrode and the PMOS drain electrode are interchanged, and the NMOS source electrode and the NMOS drain electrode are interchanged.
In order to achieve the above object, the present invention further provides a method for manufacturing the above SOI layer variable doping BCD device, including the steps of:
step 1: the SOI material comprises a silicon-on-insulator layer containing a first epitaxial layer and a second epitaxial layer; or in addition to the first epitaxial layer and the second epitaxial layer, an nth epitaxial layer 2-N is further included above the second epitaxial layer, where N is 3, 4, 5, 6 … …;
step 2: forming a first STI isolation, a second STI isolation and a third STI isolation through local oxidation or groove etching filling;
and step 3: forming a first P well, a third P well and a fourth P well through photoetching, exposure, development and ion implantation, and performing junction pushing;
and 4, step 4: carrying out local oxidation to form a gate oxide layer;
and 5: depositing a polysilicon gate to form a DMOS gate electrode, a PMOS gate electrode and an NMOS gate electrode;
step 6: forming a DMOS source P-type heavily doped region, a third P-type heavily doped region, a fourth P-type heavily doped region and a fifth P-type heavily doped region through photoetching, exposure, development and ion implantation;
and 7: forming a DMOS source N-type heavily doped region, a DMOS drain N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, a fourth N-type heavily doped region and a fifth N-type heavily doped region through photoetching, exposure, development and ion implantation;
and 8: and (4) performing contact hole etching, metal deposition and etching to respectively form a DMOS source electrode, a contact electrode of the first P well, a DMOS drain electrode, a BJT base electrode, a BJT emitter electrode, a BJT collector electrode, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode and an NMOS drain electrode.
Specifically, before step 3, P-type impurity ion implantation is performed to form a P-type doped region, and the upper surface of the P-type doped region is connected to the upper surface of the second epitaxial layer or the nth epitaxial layer 2-N, where N is 3, 4, 5, 6 … ….
Specifically, before step 3, P-type impurity ion implantation is performed to form a P-type doped region, and epitaxial growth is performed again so that the upper surface of the P-type doped region is not in contact with the upper surface of the second epitaxial layer, and if an nth epitaxial layer 2-N is included, the P-type doped region is not connected with the upper surface of the nth epitaxial layer 2-N, where N is 3, 4, 5, and 6 … ….
The invention also provides an L IGBT, CMOS and BJT integrated device, wherein the DMOS drain N-type heavily doped region in the device is changed into a collector P-type heavily doped region.
The invention has the beneficial effects that: the double-layer variable doping SOI layer or the multi-layer variable doping SOI layer is utilized, and the variable doping concentration of the SOI layer is utilized to serve as an Nwell area introduced for restraining short channel effect in the CMOS by adjusting different concentrations of each epitaxial layer. On one hand, the method can reduce the mask in the Nwell area in the BCD process, is beneficial to reducing the cost of mass production products and improving the competitiveness of the products; on the other hand, the concentration of the Nwell region is usually much higher than that of the epitaxial layer, so that the concentration of the epitaxial layer serving as the Nwell region is also increased, the number of carriers in an on state of the DMOS device is increased, the specific on-resistance of the DMOS device is further reduced, the device loss is reduced, and the performance of the device is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional BCD device structure.
Fig. 2 is a schematic cross-sectional view of a BCD device structure that suppresses short channel effects.
Fig. 3 is a cross-sectional view of a structure of a dual-variation doped SOI BCD device with the upper surface of the P-type doped region connected to the upper surface of the second epitaxial layer in accordance with the present invention.
Fig. 4 is a cross-sectional schematic view of a structure of a dual-variation doped SOI BCD device without a P-type doped region in accordance with the present invention.
Fig. 5 is a cross-sectional schematic view of a structure of a SOI BCD device of the present invention with dual-variation doping and a P-type doped region having an upper surface that is not connected to an upper surface of the second epitaxial layer.
Fig. 6 is a cross-sectional view of a structure of a SOI BCD device of the present invention with multiple doping and a P-type doped region top surface connected to a second epitaxial layer top surface.
Fig. 7 is a cross-sectional view of a poly-doped SOI BCD device structure without P-type doped regions in accordance with the present invention.
Fig. 8 is a cross-sectional schematic view of a structure of an SOI BCD device of the present invention with multiple doping and without the upper surface of the P-type doped region connected to the upper surface of the second epitaxial layer.
Fig. 9 is a cross-sectional illustration of an SOI L IGBT-CMOS-BJT integrated device structure without P-type doped regions of the present invention.
Wherein 1 is a substrate, 131 is a first STI isolation, 132 is a second STI isolation, 133 is a third STI isolation, 134 is a buried oxide layer, 2 is a first epitaxial layer, 21 is a second epitaxial layer, 2-N is an nth epitaxial layer, 311 is a first P isolation, 312 is a second P isolation, 313 is a third P isolation, 314 is a P-type doped region, 31 is a first P well, 32 is a second P well, 33 is a third P well, 34 is a fourth P well, 35 is a first P-type lightly doped region, 36 is a second P-type lightly doped region, 310 is a DMOS source P-type heavily doped region, 37 is a third P-type heavily doped region, 38 is a fourth P-type heavily doped region, 39 is a fifth P-type heavily doped region, 4 is a DMOS source N-type heavily doped region, 41 is a DMOS drain N-type heavily doped region, 42 is a first N-type heavily doped region, 43 is a second N-type region, 44 is a third N-type region, and 45 is a fourth N-type heavily doped region, 46 is a fifth N-type heavily doped region, 47 is an Nwell region, 48 is an Nbuffer region, 5 is a DMOS source electrode, 51 is a contact electrode of the first P- well 31, 6 is a DMOS gate electrode, 61 is a DMOS second gate electrode, 62 is a PMOS gate electrode, 63 is an NMOS gate electrode, 7 is a DMOS drain electrode, 8 is a BJT base electrode, 9 is a BJT emitter electrode, 10 is a BJT collector electrode, 11 is a PMOS source electrode, 12 is an NMOS source electrode, 13 is a PMOS drain electrode, 14 is an NMOS drain electrode, and 3111 is a collector P-type heavily doped region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
Fig. 4 is a schematic diagram of a structure of a SOI layer variable-doping BCD device according to the present invention, wherein a cell structure of the device includes a substrate 1, a first epitaxial layer 2, a second epitaxial layer 21, a first STI isolation 131, a second STI isolation 132, a third STI isolation 133, a buried oxide layer 134, a first P well 31, a third P well 33, a fourth P well 34, a DMOS source P-type heavily doped region 310, a third P-type heavily doped region 37, a fourth P-type heavily doped region 38, a fifth P-type heavily doped region 39, a DMOS source N-type heavily doped region 4, a DMOS drain N-type heavily doped region 41, a second N-type heavily doped region 43, a third N-type heavily doped region 44, a fourth N-type heavily doped region 45, a fifth N-type heavily doped region 46, a DMOS source electrode 5, a contact electrode 51 of the first P well 31, a DMOS gate electrode 6, a PMOS gate electrode 62, an NMOS gate electrode 63, a PMOS source electrode 11, a PMOS drain electrode 13, an NMOS source electrode 12, an NMOS, the DMOS drain electrode 7, the BJT base electrode 8, the BJT emitter electrode 9, and the BJT collector electrode 10, wherein the buried oxide layer 134 is disposed on the upper surface of the substrate 1, the first epitaxial layer 2 is disposed on the upper surface of the buried oxide layer 134, the second epitaxial layer 21 is disposed on the upper surface of the first epitaxial layer 2, the first STI isolation 131 is disposed on the left side of the first P-well 31, the lower surface thereof is in contact with the upper surface of the buried oxide layer 134, the upper surface of the first P-well 31 is connected to the upper surface of the second epitaxial layer 21, the first P-well 31 is internally provided with a DMOS source P-type heavily doped region 310 and a DMOS source N-type heavily doped region 4 which are independent of each other, the DMOS drain N-type heavily doped region 41 is disposed on the right side of the first P-well 31, the second STI isolation 132 is disposed on the right side of the DMOS drain N-type heavily doped region 41, the lower surface thereof is in contact with the upper surface of the buried oxide layer 134, the third P, the fourth P-type heavily doped region 38 is disposed at the right side of the third P-type heavily doped region 37, the third P-well 33 is disposed at the right side of the fourth P-type heavily doped region 38, the second N-type heavily doped region 43 and the third N-type heavily doped region 44 which are independent of each other are disposed inside the third P-well 33, the third STI isolation 133 is disposed at the right side of the third P-well 33, the lower surface thereof is in contact with the upper surface of the buried oxide layer 134, the fourth P-well 34 is disposed at the right side of the third STI isolation 133, the fifth P-type heavily doped region 39 and the fourth N-type heavily doped region 45 which are independent of each other and spaced apart from each other are disposed inside the fourth P-well 34, the fifth N-type heavily doped region 46 is disposed at the right side of the fourth P-well 34, the DMOS source electrode 5 is disposed above the source N-type heavily doped region 4, the contact electrode 51 of the first P-well 31 is disposed above the DMOS source P-type heavily doped region 310, the DMOS gate electrode 6 is disposed above the first P-well 31, the left end portion thereof covers the DMOS source N-type heavily doped region 4 and does not contact with the DMOS source electrode 5, the PMOS gate electrode 62 is disposed above the third P-type heavily doped region 37 and the fourth P-type heavily doped region 38, the left end portion thereof covers the third P-type heavily doped region 37 and does not contact with the PMOS source electrode 11, the right end portion thereof covers the fourth P-type heavily doped region 38 and does not contact with the PMOS drain electrode 13, the NMOS gate electrode 63 is disposed above the second N-type heavily doped region 43 and the third N-type heavily doped region 44, the left end portion thereof covers the second N-type heavily doped region 43 and does not contact with the NMOS drain electrode 14, the right end portion thereof covers the third N-type heavily doped region 44 and does not contact with the NMOS source electrode 12, the DMOS drain electrode 7 is disposed above the DMOS drain N-type heavily doped region 41, the BJT base electrode 8 is disposed above the fifth P-type heavily doped region 39, the BJT emitter electrode 9 is disposed above the fourth heavily doped N-type region 45, the BJT collector electrode 10 is disposed above the fifth heavily doped N-type region 46, the PMOS source electrode 11 is disposed above the third heavily doped P-type region 37, the PMOS drain electrode 13 is disposed above the fourth heavily doped P-type region 38, the NMOS source electrode 12 is disposed above the third heavily doped N-type region 44, and the NMOS drain electrode 14 is disposed above the second heavily doped N-type region 43.
The manufacturing method of the SOI layer variable-doping BCD device comprises the following steps:
step 1: the SOI layer comprises a first epitaxial layer 2 and a second epitaxial layer 21;
step 2: forming a first STI isolation 131, a second STI isolation 132, and a third STI isolation 133 by local oxidation or trench filling;
and step 3: forming a first P well 31, a third P well 33 and a fourth P well 34 by photoetching, exposure, development and ion implantation, and performing junction pushing;
and 4, step 4: carrying out local oxidation to form a gate oxide layer;
and 5: depositing a polysilicon gate to form a DMOS gate electrode 6, a PMOS gate electrode 62 and an NMOS gate electrode 63;
step 6: forming a DMOS source P-type heavily doped region 310, a third P-type heavily doped region 37, a fourth P-type heavily doped region 38 and a fifth P-type heavily doped region 39 by photolithography, exposure, development and ion implantation;
and 7: forming a DMOS source N-type heavily doped region 4, a DMOS drain N-type heavily doped region 41, a second N-type heavily doped region 43, a third N-type heavily doped region 44, a fourth N-type heavily doped region 45 and a fifth N-type heavily doped region 46 by photoetching, exposure, development and ion implantation;
and 8: and (3) performing contact hole etching, depositing metal and etching to form a DMOS source electrode 5, a contact electrode 51 of the first P well 31, a DMOS drain electrode 7, a BJT base electrode 8, a BJT emitter electrode 9, a BJT collector electrode 10, a PMOS source electrode 11, a PMOS drain electrode 13, an NMOS source electrode 12 and an NMOS drain electrode 14 respectively.
The SOI layer variable-doping BCD device provided by the technical scheme is characterized in that: with a double layer variable doped SOI layer, the variable doping concentration of the SOI layer is used to act as Nwell region 47 introduced to suppress short channel effects in CMOS by adjusting the different concentrations of each epitaxial layer. On one hand, the method can reduce the mask of the Nwell area 47 in the BCD process, is beneficial to reducing the cost of mass production products and improving the competitiveness of the products; on the other hand, the concentration of the Nwell region is usually much higher than that of the epitaxial layer, so that the concentration of the epitaxial layer serving as the Nwell region is also increased, the number of carriers in an on state of the DMOS device is increased, the specific on-resistance of the DMOS device is further reduced, the device loss is reduced, and the performance of the device is improved.
Example 2
As shown in fig. 3, this embodiment is substantially the same as embodiment 1, and its main difference is that in the SOI layer variable doping BCD device, a P-type doped region 314 is further included between the first P-well 31 and the DMOS drain N-type heavily doped region 41, and its upper surface is tangent to the upper surface of the second epitaxial layer 21.
The manufacturing method of the above-described SOI layer-variant doped BCD device is substantially the same as that in embodiment 1, except that: before step 3, P-type impurity ion implantation is performed to form a P-type doped region 314, so that the upper surface of the P-type doped region is tangent to the upper surface of the second epitaxial layer 21.
Example 3
As shown in fig. 5, this embodiment is substantially the same as embodiment 1, and its main difference is that the upper surface of the P-type doped region 314 disposed between the first P-well 31 and the DMOS drain N-type heavily doped region 41 is not tangent to the upper surface of the second epitaxial layer 21.
The manufacturing method of the above-described SOI layer-variant doped BCD device is substantially the same as that in embodiment 1, except that: before step 3, P-type impurity ion implantation is performed to form a P-type doped region 314, and epitaxial growth is performed again so that the upper surface of the P-type doped region is not tangent to the upper surface of the second epitaxial layer 21.
Example 4
As shown in fig. 6, this embodiment is substantially the same as embodiment 2, and its main difference is that the above-mentioned SOI layer-variant doped BCD device includes multiple epitaxial layers, that is, above the second epitaxial layer 21, a third epitaxial layer 2-3, a fourth epitaxial layer 2-4 … …, an nth epitaxial layer 2-N, where N is 3, 4, 5, 6 … …; the upper surface of the first P well 31 is connected to the upper surface of the N-th epitaxial layer 2-N, where N is 3, 4, 5, 6 … ….
The manufacturing method of the above-described SOI layer-variant doped BCD device is substantially the same as that in embodiment 1, except that: step 1: the silicon-on-insulator layer of SOI material contains a first epitaxial layer 2, a second epitaxial layer 21, and an nth epitaxial layer 2-N above the second epitaxial layer, where N is 3, 4, 5, 6 … ….
Before step 3, P-type impurity ion implantation is performed to form a P-type doped region 314, and the upper surface of the P-type doped region is connected to the upper surface of the N-th epitaxial layer 2-N, where N is 3, 4, 5, and 6 … ….
Example 5
As shown in fig. 7, this embodiment is substantially the same as embodiment 4, and the main difference is that the SOI layer variable-doping BCD device does not include the P-type doped region 314 disposed between the first P-well 31 and the DMOS drain N-type heavily doped region 41.
The manufacturing method of the above-described SOI layer-variant doped BCD device is substantially the same as that in embodiment 1, except that: step 1: the silicon-on-insulator layer of SOI material contains a first epitaxial layer 2, a second epitaxial layer 21, and an nth epitaxial layer 2-N above the second epitaxial layer, where N is 3, 4, 5, 6 … ….
Example 6
As shown in fig. 8, this embodiment is substantially the same as embodiment 4, and its main difference is that the upper surface of the P-type doped region 314 disposed between the first P-well 31 and the DMOS drain N-type heavily doped region 41 is not tangent to the upper surface of the second epitaxial layer 21.
The manufacturing method of the above-described SOI layer-variant doped BCD device is substantially the same as that in embodiment 1, except that: step 1: the silicon-on-insulator layer of SOI material contains a first epitaxial layer 2, a second epitaxial layer 21, and an nth epitaxial layer 2-N above the second epitaxial layer, where N is 3, 4, 5, 6 … ….
Before step 3, P-type impurity ion implantation is performed to form a P-type doped region 314, and epitaxial growth is performed again so that the upper surface of the P-type doped region is not connected to the upper surface of the N-th epitaxial layer 2-N, where N is 3, 4, 5, 6 … ….
Example 7
As shown in fig. 9, this embodiment is substantially the same as embodiment 5, and its main difference is that this embodiment changes DMOS drain N-type heavily doped region 41 into collector P-type heavily doped region 3111, so as to form L IGBT-CMOS-BJT integrated device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. An SOI layer variable-doping BCD device is characterized in that: the cellular structure comprises a substrate (1), a first epitaxial layer (2), a second epitaxial layer (21), a first STI isolator (131), a second STI isolator (132), a third STI isolator (133), a buried oxide layer (134), a first P well (31), a third P well (33), a fourth P well (34), a DMOS source P type heavily doped region (310), a third P type heavily doped region (37), a fourth P type heavily doped region (38), a fifth P type heavily doped region (39), a DMOS source N type heavily doped region (4), a DMOS drain N type heavily doped region (41), a second N type heavily doped region (43), a third N type heavily doped region (44), a fourth N type heavily doped region (45), a fifth N type heavily doped region (46), a DMOS source electrode (5), a contact electrode (51) of the first P well (31), a DMOS gate electrode (6), a PMOS gate electrode (62) and an NMOS gate electrode (63), a PMOS source electrode (11), a PMOS drain electrode (13), an NMOS source electrode (12), an NMOS drain electrode (14), a DMOS drain electrode (7), a BJT base electrode (8), a BJT emitter electrode (9), and a BJT collector electrode (10), wherein the buried oxide layer (134) is arranged on the upper surface of the substrate (1), the first epitaxial layer (2) is arranged on the upper surface of the buried oxide layer (134), the second epitaxial layer (21) is arranged on the upper surface of the first epitaxial layer (2), the first STI (shallow trench isolation) 131 is arranged on the left side of the first P-well (31), the lower surface of the first P-well is contacted with the upper surface of the buried oxide layer (134), the upper surface of the first P-well (31) is connected with the upper surface of the second epitaxial layer (21), and a source P-type heavily doped region (310) and a DMOS source N-type heavily doped region (4) which are independent from each other are arranged in the first P-well (31), the DMOS drain N-type heavily doped region (41) is arranged on the right side of the first P well (31), the second STI isolation (132) is arranged on the right side of the DMOS drain N-type heavily doped region (41), the lower surface of the DMOS drain N-type heavily doped region is contacted with the upper surface of the buried oxide layer (134), the third P-type heavily doped region (37) is arranged on the right side of the second STI isolation (132), the fourth P-type heavily doped region (38) is arranged on the right side of the third P-type heavily doped region (37), the third P well (33) is arranged on the right side of the fourth P-type heavily doped region (38), the third P well (33) is internally provided with a second N-type heavily doped region (43) and a third N-type heavily doped region (44) which are independent of each other, the third STI isolation (133) is arranged on the right side of the third P well (33), the lower surface of the third STI isolation (133) is contacted with the upper surface of the buried oxide layer (134), and the fourth P well (34) is arranged on the right side, a fifth P-type heavily doped region (39) and a fourth N-type heavily doped region (45) which are independent from each other and spaced from each other are arranged in the fourth P-well (34), the fifth N-type heavily doped region (46) is arranged on the right side of the fourth P-well (34), the DMOS source electrode (5) is arranged above the DMOS source N-type heavily doped region (4), the contact electrode (51) of the first P-well (31) is arranged above the DMOS source P-type heavily doped region (310), the DMOS gate electrode (6) is arranged above the first P-well (31), the left end part of the DMOS source N-type heavily doped region (4) is covered with the DMOS source electrode (5) and is not contacted with the DMOS source electrode (5), the PMOS gate electrode (62) is arranged above the third P-type heavily doped region (37) and the fourth P-type heavily doped region (38), the left end part of the PMOS gate electrode is covered with the third P-type heavily doped region (37) and is not contacted with the PMOS source electrode (11), the right end part of the NMOS gate electrode (63) is arranged above the second N-type heavily doped region (43) and the third N-type heavily doped region (44), the left end part of the NMOS gate electrode covers the second N-type heavily doped region (43) and is not contacted with the NMOS drain electrode (14), the right end part of the NMOS gate electrode covers the third N-type heavily doped region (44) and is not contacted with the NMOS source electrode (12), the DMOS drain electrode (7) is arranged above the DMOS drain N-type heavily doped region (41), the BJT base electrode (8) is arranged above the fifth P-type heavily doped region (39), the BJT emitter electrode (9) is arranged above the fourth N-type heavily doped region (45), the BJT collector electrode (10) is arranged above the fifth N-type heavily doped region (46), and the PMOS source electrode (11) is arranged above the third P-type heavily doped region (37), the PMOS drain electrode (13) is arranged above the fourth P-type heavily doped region (38), the NMOS source electrode (12) is arranged above the third N-type heavily doped region (44), and the NMOS drain electrode (14) is arranged above the second N-type heavily doped region (43);
the second epitaxial layer (21) is provided with a 3 rd epitaxial layer (2-3) and a 4 th epitaxial layer (2-4) … …, wherein the upper surface of the first P well (31) is connected with the upper surface of the N epitaxial layer (2-N), and N is 3, 4, 5, 6 … ….
2. The SOI layer variable-doping BCD device of claim 1, wherein: comprises a P-type doped region (314) with the upper surface tangent to the upper surface of the second epitaxial layer (21), wherein the P-type doped region (314) is arranged between the first P-well (31) and the DMOS drain N-type heavily doped region (41).
3. The SOI layer variable-doping BCD device of claim 1, wherein: comprises a P-type doped region (314), the upper surface of the P-type doped region is connected with the upper surface of the N-th epitaxial layer (2-N), and the P-type doped region (314) is arranged between the first P-well (31) and the DMOS drain N-type heavily doped region (41).
4. The SOI layer variable-doping BCD device of claim 1, wherein: the upper surface of the P-type doped region (314) arranged between the first P well (31) and the DMOS drain N-type heavily doped region (41) is not tangent to the upper surface of the second epitaxial layer (21).
5. The SOI layer variable-doping BCD device of claim 1, wherein: the upper surface of the P-type doped region (314) arranged between the first P well (31) and the DMOS drain N-type heavily doped region (41) is not connected with the upper surface of the N epitaxial layer (2-N).
6. The SOI layer variable-doping BCD device of claim 1, wherein: the PMOS source electrode (11) and the PMOS drain electrode (13) are mutually exchanged, and the NMOS source electrode (12) and the NMOS drain electrode (14) are mutually exchanged.
7. The method of claim 1, comprising the steps of:
step 1: the SOI layer comprises a first epitaxial layer (2) and a second epitaxial layer (21) on an SOI material; in addition to the first epitaxial layer (2) and the second epitaxial layer (21), an Nth epitaxial layer (2-N) is contained above the second epitaxial layer, wherein N is 3, 4, 5, 6 … …;
step 2: forming a first STI isolation (131), a second STI isolation (132) and a third STI isolation (133) by local oxidation or notch filling;
and step 3: forming a first P well (31), a third P well (33) and a fourth P well (34) through photoetching, exposure, development and ion implantation, and performing junction pushing;
and 4, step 4: carrying out local oxidation to form a gate oxide layer;
and 5: depositing a polysilicon gate to form a DMOS gate electrode (6), a PMOS gate electrode (62) and an NMOS gate electrode (63);
step 6: forming a DMOS source P-type heavily doped region (310), a third P-type heavily doped region (37), a fourth P-type heavily doped region (38) and a fifth P-type heavily doped region (39) through photoetching, exposure, development and ion implantation;
and 7: forming a DMOS source N-type heavily doped region (4), a DMOS drain N-type heavily doped region (41), a second N-type heavily doped region (43), a third N-type heavily doped region (44), a fourth N-type heavily doped region (45) and a fifth N-type heavily doped region (46) through photoetching, exposure, development and ion implantation;
and 8: and performing contact hole etching, metal deposition and etching to respectively form a DMOS source electrode (5), a contact electrode (51) of the first P well (31), a DMOS drain electrode (7), a BJT base electrode (8), a BJT emitter electrode (9), a BJT collector electrode (10), a PMOS source electrode (11), a PMOS drain electrode (13), an NMOS source electrode (12) and an NMOS drain electrode (14).
8. The method of claim 7, wherein the step of forming a BCD device comprises: before step 3, P-type impurity ion implantation is performed to form a P-type doped region 314, and the upper surface of the P-type doped region is connected with the upper surface of the second epitaxial layer 21 or the upper surface of the Nth epitaxial layer 2-N, wherein N is 3, 4, 5, 6 … ….
9. The method of claim 7, wherein the step of forming a BCD device comprises: before step 3, P-type impurity ion implantation is performed to form a P-type doped region (314), and epitaxial growth is performed again so that the upper surface of the P-type doped region is not in contact with the upper surface of the second epitaxial layer (21), and if an Nth epitaxial layer (2-N) is included, the P-type doped region is not connected with the upper surface of the Nth epitaxial layer (2-N), wherein N is 3, 4, 5, and 6 … ….
10. An L IGBT, CMOS and BJT integrated device, characterized in that the DMOS drain N-type heavily doped region (41) in any one of the devices of claims 1 to 6 is changed to a collector P-type heavily doped region (3111).
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| CN102201406A (en) * | 2011-04-26 | 2011-09-28 | 电子科技大学 | Bipolar CMOS DMOS (BCD) integrated device based on N type extension layer and manufacture method thereof |
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| CN102169890A (en) * | 2011-05-03 | 2011-08-31 | 浙江大学 | Isolation structure for high-voltage power integrated circuit |
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