CN114512536B - Super junction semiconductor device - Google Patents

Super junction semiconductor device Download PDF

Info

Publication number
CN114512536B
CN114512536B CN202210402006.6A CN202210402006A CN114512536B CN 114512536 B CN114512536 B CN 114512536B CN 202210402006 A CN202210402006 A CN 202210402006A CN 114512536 B CN114512536 B CN 114512536B
Authority
CN
China
Prior art keywords
region
type
semiconductor device
source
segmented body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210402006.6A
Other languages
Chinese (zh)
Other versions
CN114512536A (en
Inventor
苑羽中
张玉琦
戴银
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Original Assignee
Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing Electronics Shaoxing Corp SMEC filed Critical Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority to CN202210402006.6A priority Critical patent/CN114512536B/en
Publication of CN114512536A publication Critical patent/CN114512536A/en
Application granted granted Critical
Publication of CN114512536B publication Critical patent/CN114512536B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a super junction semiconductor device. In at least one cellular structure of the super junction semiconductor device, a first type body region comprises at least two segmented body regions arranged in a third direction, a source region is arranged on the surface, far away from a drain region, of one part of the segmented body regions, a gate oxide layer is arranged on the surface, far away from the drain region, of the other part of the segmented body regions, and a gate is arranged on the surface, far away from the segmented body regions, of the gate oxide layer.

Description

Super junction semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a super junction semiconductor device.
Background
A longitudinally-extending P-type doped column is inserted into a drift region of a traditional power device of the super-junction semiconductor device, PN junctions formed by the P-type doped column and an adjacent N-type doped column are mutually depleted in an off state, a 3D-RESURF (reduced surface electric field) effect is formed, and the device voltage resistance is met while a smaller on-resistance Ron can be obtained.
As shown in fig. 1 and fig. 2, in a cell structure of a super junction semiconductor device, a P-type doped column 11 disposed in a drift region 10 is provided with a P-type body region 20 (P body) on top, an N + source region 20a for contacting with a source metal (not shown) of the device is disposed on a top surface of the P-type body region 20, and a gate oxide layer 13 and a polysilicon gate 14 are disposed on the N-type doped column 12, wherein the gate oxide layer 13 is in contact with both the P-type doped column 11 and the N-type doped column 12, the polysilicon gate 14 and the source metal are isolated from each other by a dielectric material 15, an N + drain region 16 is located below the drift region 10, and the N + drain region 16 is for contacting with a drain metal (not shown) of the device. In the cellular structure, the vertically extending P-type doped column 11 forms a shielding effect on the polysilicon gate 14, so that the miller capacitance Cgd is low, which easily causes the turn-off speed to be too fast, generates a large overshoot voltage, and may cause a serious EMI problem.
Increasing the miller capacitance Cgd appropriately can reduce the turn-off speed and reduce the overshoot voltage, but increasing the miller capacitance Cgd at once also causes an increase in Qg (gate charge), resulting in increased switching losses and possibly also affecting the device withstand voltage level, so it is preferable to increase the miller capacitance Cgd to reduce the turn-off speed and reduce the overshoot voltage while avoiding affecting Qg and device withstand voltage performance.
Disclosure of Invention
In order to increase the Miller capacitance Cgd to reduce the turn-off speed and the overshoot voltage and simultaneously have small influence on Qg and the voltage resistance of the device, the invention provides a super junction semiconductor device.
The super junction semiconductor device comprises at least one cellular structure, wherein the cellular structure comprises a drain region, a drift region, a gate oxide layer and a grid which are sequentially arranged in a first direction, and a first type doping column and a second type doping column which are arranged in a second direction vertical to the first direction and are adjacent to each other are arranged in the drift region; the cellular structure further comprises a first-type body region and a source region, the first-type body region is positioned at the end, far away from the drain region, of the first-type doping column in the first direction, the first-type body region comprises at least two segmented body regions arranged in a third direction, the third direction intersects with a plane formed by the second direction and the first direction, and the source region is arranged on the surface, far away from the drain region, of one part of the segmented body regions; the gate oxide layer is arranged on the surface of the other part of the segmented body area far away from the drain area, and the gate is arranged on the surface of the gate oxide layer far away from the segmented body area.
Optionally, in the third direction, a second-type isolation region is disposed between two adjacent segmented body regions, and the second-type isolation region is connected to the second-type doped column.
Optionally, in the first direction, the depth of the second-type isolation region is greater than or equal to the depth of the first-type body region.
Optionally, the gate oxide layer covers a surface of the other part of the segmented body region far away from the drain region, and extends to cover a surface of the second-type isolation region far away from the drain region and a part of the surface of the source region.
Optionally, when the PN junction formed by the first-type doped column and the second-type doped column is depleted, the second-type isolation region is not depleted.
Optionally, in all the segmented body regions, except the segmented body region provided with the source region, the gate oxide layers are arranged on the surfaces, far away from the drain region, of the rest of the segmented body regions.
Optionally, the first type body region includes two segmented body regions arranged in a third direction, the source region is disposed on a surface of one of the segmented body regions away from the drain region, and the gate oxide layer is disposed on a surface of the other segmented body region away from the drain region.
Optionally, the first type body region includes three segment body regions arranged in a third direction, the source region is disposed on a surface of the segment body region located in the middle, the surface being far away from the drain region, and the gate oxide layer is disposed on surfaces of the other two segment body regions, the surfaces being far away from the drain region.
Optionally, the cell structure further includes a source, the source is in contact with the source region, and the gate is isolated from the source by a dielectric material.
Optionally, a body region extraction region is further disposed on the surface of the segmented body region where the source region is disposed, and the source, the source region, and the body region extraction region are in contact with each other.
Optionally, the second direction, the first direction and the third direction are perpendicular to each other.
In the super junction semiconductor device, in at least one cellular structure, a first type body region comprises at least two segmented body regions arranged in a third direction, a source region is arranged on the surface of one part of the segmented body regions far away from the drain region, a gate oxide layer is arranged on the surface of the other part of the segmented body regions far away from the drain region, and a gate is arranged on the surface of the gate oxide layer far away from the segmented body regions.
Drawings
Fig. 1 is a schematic diagram of a cell structure of a super junction semiconductor device.
Fig. 2 is a simulation diagram of the cell structure shown in fig. 1.
Fig. 3 is a schematic diagram of a cell structure of another superjunction semiconductor device.
Fig. 4 is a simulation diagram of the cell structure shown in fig. 3.
Fig. 5 is a schematic diagram of a cell structure of a super junction semiconductor device according to an embodiment of the present invention.
Fig. 6 is a simulation diagram of the cell structure shown in fig. 5.
Fig. 7 is a schematic diagram of a cell structure of a super junction semiconductor device according to another embodiment of the present invention.
Fig. 8 is a diagram of a depletion state of the cell structure shown in fig. 4.
Fig. 9 is a diagram of a depletion state of the cell structure shown in fig. 6.
Fig. 10 is a voltage withstand curve of the cell structure shown in fig. 4 and 6.
FIG. 11 is a plot of Vds-Cgd and Vds-Cds for the cell structures shown in FIGS. 2, 4 and 6. Description of reference numerals:
10. a 100-drift region; 11. a 110-P type doped column; 12. 120-N type doped columns; 20. a 200-P type body region; 20a, 200a-N + source regions; 200 b-body lead-out region; 13. 130-gate oxide layer; 14. 140-polysilicon gate; 15. 150-a dielectric material; 16. a 160-N + drain region; a 300-N type isolation region; 210-a first segmented body region; 220-a second segmented body region; 230-third subsection volume.
Detailed Description
The superjunction semiconductor device of the present invention is described in further detail below with reference to the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in a very simplified form and are not to scale, this being done for convenience and clarity only to aid in the description of embodiments of the invention. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "at … …" can also include "at … …" and other orientational relationships.
It should be noted that the superjunction semiconductor device according to the embodiment of the present invention may be an N-type or P-type device, depending on the type of mobile ions in the channel. When the superjunction semiconductor device to be manufactured is an N-type device, the first type described below is a P-type, and the second type is an N-type. It is understood that interchanging the doping type of the N-type device between N-type and P-type results in a P-type device structure. The dopant of the source region in the N-type device is, for example, phosphorus or arsenic, and the dopant of the source region in the P-type device is, for example, boron or indium. The following examples are mainly described with reference to N-type devices.
Referring to fig. 1 and 2, in a cell structure of a super junction semiconductor device, a P-type doped column 11 extending longitudinally forms a shielding effect on a polysilicon gate 14, so that a miller capacitance Cgd is low, which easily causes an excessively fast turn-off speed, generates a large overshoot voltage, and may cause a serious EMI problem.
Referring to fig. 3 and 4, in the cell structure of the super junction semiconductor device with increased Cgd relative to the super junction semiconductor device shown in fig. 1 and 2, the polysilicon gate 14 extends for a length in the Z direction, and the top of the N-type doped column 12 also extends for a length in the Z direction, where the Z direction is orthogonal to (perpendicular to) the X direction and the Y direction, the Z direction is the arrangement direction of the P-type doped column 11 and the N-type doped column 12, and the X direction is the column extension direction (i.e., depth direction) of the P-type doped column 11. In the cell structure shown in fig. 3 and 4, similar to the cell structure shown in fig. 1 and 2, in the X direction, the gate oxide layer 13 covers the top surface of the N-type doped column 12 and extends to cover a part of the N + source region 20a of the top surface of the P-type body region 20 (located on the top of the P-type doped column 11), and the polysilicon gate 14 covers the top surface of the gate oxide layer 13.
The cell structure shown in fig. 3 and 4 increases the width of the polysilicon gate 14 in the Z direction relative to the cell structure shown in fig. 1 and 2, which is beneficial to increase the miller capacitance Cgd, but on one hand, the increase effect of the polysilicon gate 14 on the miller capacitance Cgd is limited because the width of the polysilicon gate is limited by the chip pitch (pitch), and on the other hand, the surface electric field of the cell structure shown in fig. 3 and 4 is too strong, and the withstand voltage performance is significantly reduced relative to the cell structure shown in fig. 1 and 2.
In order to increase the miller capacitance Cgd to reduce the turn-off speed and the overshoot voltage, and avoid affecting Qg (the increase of Qg causes the increase of the switching loss) and the voltage withstanding performance of the device, the embodiment of the invention introduces a super junction semiconductor device.
The Miller capacitance Cgd of the super junction semiconductor device is usually subjected to sudden change along with drain-source voltage Vds, because the cell sizes of the P-type doped columns and the N-type doped columns which are transversely and alternately arranged in the drift region are smaller, PN junctions formed by the P-type doped columns and the N-type doped columns are completely depleted under the lower drain-source voltage Vds, and transverse depletion layers are rapidly merged to cause the depletion layers to widen, so that the Miller capacitance Cgd is subjected to sharp drop at a certain drain-source voltage and then slowly rises. The inventor researches and discovers that Qg is basically generated in a low drain-source voltage Vds region, so that the reasonable adjustment direction of the Miller capacitance Cgd is to increase the Miller capacitance Cgd in a larger drain-source voltage Vds region and not obviously change the Miller capacitance Cgd in a smaller drain-source voltage Vds region.
Fig. 5 is a schematic diagram of a cell structure of a super junction semiconductor device according to an embodiment of the present invention. Fig. 6 is a simulation diagram of the cell structure shown in fig. 5. Referring to fig. 5 and 6, an embodiment of the present invention relates to a super junction semiconductor device, which includes at least one cell structure, where the cell structure includes a drain region, a drift region 100, a gate oxide layer 130, and a gate electrode sequentially arranged in a first direction (X direction shown in fig. 5), and a first-type doped column and a second-type doped column arranged and adjacent to each other in a second direction (Z direction shown in fig. 5) perpendicular to the first direction are arranged in the drift region 100; the first-type body region is positioned at the end, far away from the drain region, of the first-type doping column in the first direction, the first-type body region comprises at least two segmented body regions arranged in a third direction, the third direction intersects with a plane formed by the second direction and the first direction, and the source region is arranged on the surface, far away from the drain region, of one part of the segmented body regions; the gate oxide layer 130 is arranged on the surface of the other part of the segmented body region far away from the drain region, and the gate is arranged on the surface of the gate oxide layer far away from the segmented body region.
For convenience of understanding, the super junction semiconductor device according to the embodiment of the present invention is exemplarily illustrated below by taking the first type as a P-type doping column and the second type as an N-type doping column, where the first type doping column is a P-type doping column 110, the second type doping column is an N-type doping column 120, the first type body region is a P-type body region 200, the source region is an N + source region 200a, and the drain region is an N + drain region 160.
Of the first direction, the second direction and the third direction, the second direction refers to a lateral direction of the drift region 100, i.e., a direction in which the P-type doped column 110 and the N-type doped column 120 are arranged, and is shown as a Z direction in fig. 5; the first direction refers to the thickness direction of the drift region 100, i.e., the depth direction of the P-type doped column 110 and the N-type doped column 120, which is shown as the X direction in fig. 5; the third direction intersects a plane formed by the first direction and the second direction, for example, at an acute angle or a right angle, and illustratively, the third direction is perpendicular to the plane formed by the first direction and the second direction, so that the first direction, the second direction and the third direction are orthogonal, that is, perpendicular to each other two by two, as shown in fig. 5, the third direction is shown as a Y direction, and the X direction, the Y direction and the Z direction are directly exemplified below.
Referring to fig. 5 and 6, the at least one cell structure of the superjunction semiconductor device of the present embodiment includes an N + drain region 160, a drift region 100, a gate oxide layer 130, and a polysilicon gate 140, which are sequentially disposed in an X direction (from bottom to top in fig. 5). P-type doped columns 110 and N-type doped columns 120 are arranged and adjacent to each other in the Z direction in the drift region 100. The cell structure further includes a P-type body region 200 and an N + source region 200a, and in the X direction, the P-type body region 200 is located at an end portion of the P-type doped column 110 far from the N + drain region 160. The P-type body region 200 includes at least two segmented body regions (a first segmented body region 210, a second segmented body region 220 and a third segmented body region 230 shown in fig. 5) arranged in the Y direction, wherein an N + source region 200a is disposed on a surface of a portion of the segmented body region away from the N + drain region 160, a gate oxide layer 130 is disposed on a surface of another portion of the segmented body region away from the N + drain region 160, and a polysilicon gate 140 is disposed on a surface of the gate oxide layer 130 away from the segmented body region.
The super junction semiconductor device of the embodiment of the invention is arranged on a substrate, and the substrate can be a silicon substrate or other substrates. The substrate having a second type of doping, e.g., heavy N-type doping, may serve as the N + drain region 160 of the above-described cell structure, and the superjunction semiconductor device may include a drain metal (not shown) disposed on a back surface of the substrate and shared by the cell structures in the superjunction semiconductor device. For example, an epitaxial layer doped with a second type is disposed on the substrate, the drift region 100 of the super junction semiconductor device is disposed in the epitaxial layer, and an implantation layer doped with a first type (for example, doped with a P type) is formed in the epitaxial layer, and the implantation layer and the adjacent epitaxial layer respectively form the first-type doped column and the second-type doped column, where a cell structure includes one first-type doped column and one second-type doped column. The super junction semiconductor device can comprise a plurality of cellular structures with the same or different structures, wherein at least one cellular structure adopts the structure described in the embodiment of the invention. As shown in fig. 5, the gate oxide layer 130 and the polysilicon gate 140 are disposed on the N-type doped column 120, that is, in the X direction, the gate oxide layer 130 covers the surface of the N-type doped column 120 on the side away from the N + drain region 160, and the polysilicon gate 140 covers the surface of the gate oxide layer 130, in this embodiment, the gate oxide layer 130 and the polysilicon gate 140 are further disposed on the P-type doped column 110.
Referring to fig. 5 and 6, in the embodiment of the invention, the P-type body region 200 is disposed at the end of the P-type doped column 110 far from the N + drain region 160 in the X direction, and the P-type body region 200 may be formed at the end of the P-type doped column 110 by implantation and annealing. The P-type body region 200 includes at least two segmented body regions arranged in the Y direction, and of the segmented body regions, two adjacent segmented body regions may be separated by decreasing the doping concentration or changing the doping ion type. In this embodiment, in the Y direction, an N-type isolation region 300 is disposed between two adjacent segmented body regions to isolate the adjacent segmented body regions. In order to avoid the influence of the segmented body regions with the N + source region on the electric fields of other segmented body regions, the N-type isolation region 300 may be a region formed by extending the top of the N-type doped column 120 toward the P-type doped column 110 along the Z direction. In the cell structure of the embodiment of the invention, when the PN junctions formed by the P-type doped column 110 and the N-type doped column 120 are depleted, the N-type isolation region 300 disposed between two adjacent segment body regions is not depleted, so as to ensure that a better isolation effect is obtained.
Referring to fig. 5 and 6, an N + source region 200a is disposed on a surface of a portion of the segmented body region away from the N + drain region 160 in the X direction, and the N + source region 200a may be formed on top of the P-type body region 200 by implantation and annealing. The gate oxide layer 130 is disposed (referred to herein as a stacked arrangement) on a surface of another portion of the segmented body region remote from the N + drain region 160. Polysilicon gates 140 are disposed on the surface of the gate oxide 130 away from the segmented body regions. Here, "a part of the segmented body region" and "another part of the segmented body region" refer to different segmented body regions. Referring to fig. 5, the gate oxide layer 130 may cover the entire surface of the other partial segment body region away from the N + drain region 160, and the gate oxide layer 130 may also extend to cover the entire surface of the N-type isolation region 300 and a partial surface of the N + source region 200 a. In addition, the gate oxide layer 130 may also extend over the entire surface of the N-type doped column 120 away from the N + drain region 160.
The number of segmented body regions where the N + source region 200a is disposed and the number of segmented body regions where the gate oxide layer 130 is disposed may be set as desired. Referring to fig. 5 to 7, in the at least one unit cell structure of the super junction semiconductor device according to the embodiment of the present invention, of all the segmented body regions of the P-type body region 200, except the segmented body region provided with the source region (here, the N + source region 200 a), the surfaces of the rest of the segmented body regions, which are far away from the N + drain region 160, are provided with the gate oxide layer 130; i.e. each segmented body region is either provided with a source region or covered by the gate oxide layer 130. This allows the gate to have a larger area to help increase the miller capacitance Cgd. Without limitation, in some embodiments, a surface of the at least one segmented body region distal from the N + drain region 160 may also be covered by a dielectric material that is not a gate oxide layer 130.
In this embodiment, the N-type isolation region 300 separates the segmented body regions of the gate oxide layer 130 and the polysilicon gate 140 from the segmented body regions of the source region, which can weaken the shielding effect of the P-type doped column 110 on the polysilicon gate 140. To enhance the isolation effect, in some embodiments, the depth of the N-type isolation region 300 is greater than or equal to the depth of the P-type body region 200 in the X-direction.
Referring to fig. 5 and 6, in an embodiment, the P-type body region 200 includes three segment body regions arranged in the Y direction, which are respectively referred to as a first segment body region 210, a second segment body region 220 and a third segment body region 230, the second segment body region 220 is located in the middle, the N + source region 200a is disposed on the surface of the second segment body region 220, the gate oxide layer 130 is disposed on the surfaces of the other two segment body regions (the first segment body region 210 and the second segment body region 220), for example, the surfaces of the first segment body region 210 and the second segment body region 220 are all covered by the gate oxide layer 130, and the surface of the gate oxide layer 130 away from the first segment body region 210 and the second segment body region 220 is all covered by the polysilicon gate 140. Fig. 7 is a schematic diagram of a cell structure of a super junction semiconductor device according to another embodiment of the present invention. Referring to fig. 7, in another embodiment, the P-type body region 200 includes two said segment body regions arranged in the Y-direction, the N + source region 200a is disposed on the surface of one of said segment body regions, the gate oxide layer 130 is disposed on the surface of the other of said segment body regions, the gate oxide layer 130 may entirely cover the surface of the other of said segment body regions, and the surface of the gate oxide layer 130 remote from the segment body regions is entirely covered by the polysilicon gate 140. In a specific application, the number of segment body regions and the position and size of each segment body region in the Y direction, the number and size of the N-type isolation region 300, the number of segment body regions where the N + source region 200a is disposed, and the number of segment body regions where the gate oxide layer 130 is disposed may be set as required.
The above cell structure of the embodiment of the present invention may further include a source, wherein the source is in contact with the N + source region 200a, and the polysilicon gate 140 is isolated from the source by the dielectric material 150. In addition, the segmented body surface provided with the N + source region 200a may be further provided with a body extraction region 200b, and the N + source region 200a and the body extraction region 200b are in contact with each other, and after the source is formed on the segmented body, any two of the source, the N + source region 200a and the body extraction region 200b are in contact with each other (i.e., the three are in contact with each other).
Fig. 8 is a diagram of a depletion state of the cell structure shown in fig. 4. Fig. 9 is a diagram of a depletion state of the cell structure shown in fig. 6. Where the white line represents the depletion layer boundary. FIG. 10 is a voltage endurance curve of the cell structures shown in FIGS. 4 and 6, wherein the cell structure shown in FIG. 4 corresponds to curve BV1, and the cell structure shown in FIG. 6 corresponds to curve BV 2. Referring to fig. 8 to 10, in terms of voltage resistance, the cell structure withstand voltage (BVdss) in the embodiment of the present invention shown in fig. 6 is higher, which can reach the level of the cell structure shown in fig. 2, while the voltage resistance performance of the Cgd-increased cell structure shown in fig. 4 is significantly degraded due to the excessively strong surface electric field.
Fig. 11 is Vds-Cgd and Vds-Cds curves for the cell structures shown in fig. 2, 4, and 6, where fig. 2 represents a conventional superjunction semiconductor device, corresponding to curves Cgd1 and Cds1 in fig. 11; fig. 4 represents a superjunction semiconductor device with enhanced Cgd, corresponding to curves Cgd2 and Cds2 in fig. 11; fig. 6 represents a superjunction semiconductor device of an embodiment of the present invention, corresponding to curves Cgd3 and Cds3 in fig. 11. Referring to fig. 11, it can be seen that, compared with the conventional superjunction semiconductor device, the miller capacitance Cgd of the superjunction semiconductor device according to the embodiment of the present invention is increased by a small amount when the drain-source voltage Vds is low, and is increased significantly when the drain-source voltage Vds is high, and as the drain-source voltage Vds is increased, the miller capacitance Cgd of the superjunction semiconductor device according to the embodiment of the present invention can reach the same level as that of the superjunction semiconductor device shown in fig. 4, and as shown in fig. 10, the superjunction semiconductor device according to the embodiment of the present invention has better voltage endurance and thus better comprehensive performance compared with the superjunction semiconductor device shown in fig. 4.
In the at least one cell structure of the super junction semiconductor device of the embodiment of the invention, the first type body region at the end of the first type doped column comprises at least two segmented body regions arranged in the third direction, a source region for connecting a source electrode is arranged on the surface of one part of the segmented body region far away from the drain region, a gate oxide layer is arranged on the surface of the other part of the segmented body region far away from the drain region, and a gate electrode is arranged on the surface of the gate oxide layer far away from the segmented body region, in the cellular structure, a segmented body region provided with a gate oxide layer and a gate electrode is separated from a segmented body region provided with a source region, the shielding effect of the first type doping column on the grid can be weakened, the Miller capacitance Cgd can be increased compared with the traditional structure, the reduction of turn-off speed is facilitated, overshoot voltage is reduced, the EMI problem is improved, and researches show that the influence on Qg and the voltage resistance of a device is small.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims (11)

1. The super junction semiconductor device is characterized by comprising at least one cellular structure, wherein the cellular structure comprises a drain region, a drift region, a gate oxide layer and a grid which are sequentially arranged in a first direction, and a first type doping column and a second type doping column which are arranged and adjacent in a second direction vertical to the first direction are arranged in the drift region; the cellular structure further comprises:
a first type body region located at an end of the first type doping column away from the drain region in the first direction, the first type body region comprising at least two segmented body regions arranged in a third direction, the third direction intersecting a plane formed by the second direction and the first direction;
the source region is arranged on the surface of one part of the segmented body region far away from the drain region;
the gate oxide layer is arranged on the surface of the other part of the segmented body region far away from the drain region, and the gate is arranged on the surface of the gate oxide layer far away from the segmented body region.
2. The superjunction semiconductor device of claim 1, wherein in the third direction, a second-type isolation region is disposed between two adjacent segmented body regions, the second-type isolation region being connected to the second-type doped column.
3. The superjunction semiconductor device of claim 2, wherein, in the first direction, a depth of the second-type isolation region is greater than or equal to a depth of the first-type body region.
4. The superjunction semiconductor device of claim 2, wherein the gate oxide layer covers a surface of the other portion of the segmented body region remote from the drain region and extends over a surface of the second-type isolation region remote from the drain region and a portion of the surface of the source region.
5. The superjunction semiconductor device of claim 2, wherein the second-type isolation region is not depleted when a PN junction formed by the first-type doped column and the second-type doped column is depleted.
6. The superjunction semiconductor device according to claim 1, wherein of all the segmented body regions, except the segmented body region where a source region is provided, surfaces of the rest of the segmented body regions, which are far from the drain region, are provided with the gate oxide layer.
7. The superjunction semiconductor device of claim 1, wherein the first type body region includes two of the segmented body regions arranged in a third direction, the source region being disposed at a surface of one of the segmented body regions remote from the drain region, and the gate oxide layer being disposed at a surface of the other of the segmented body regions remote from the drain region.
8. The superjunction semiconductor device of claim 1, wherein the first type body region includes three of the segmented body regions arranged in a third direction, the source region being disposed on a surface of the segmented body region located in the middle, which is remote from the drain region, and the gate oxide layer being disposed on a surface of the other two of the segmented body regions, which is remote from the drain region.
9. The superjunction semiconductor device of any one of claims 1 to 8, wherein the cellular structure further comprises a source, the source being in contact with the source region, the gate being isolated from the source by a dielectric material.
10. The superjunction semiconductor device according to claim 9, wherein the segmented body surface provided with the source region is further provided with a body region extraction region, and the source, the source region, and the body region extraction region are in contact with each other.
11. The superjunction semiconductor device according to any one of claims 1 to 8, wherein the second direction, the first direction, and the third direction are perpendicular two by two.
CN202210402006.6A 2022-04-18 2022-04-18 Super junction semiconductor device Active CN114512536B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210402006.6A CN114512536B (en) 2022-04-18 2022-04-18 Super junction semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210402006.6A CN114512536B (en) 2022-04-18 2022-04-18 Super junction semiconductor device

Publications (2)

Publication Number Publication Date
CN114512536A CN114512536A (en) 2022-05-17
CN114512536B true CN114512536B (en) 2022-07-15

Family

ID=81555594

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210402006.6A Active CN114512536B (en) 2022-04-18 2022-04-18 Super junction semiconductor device

Country Status (1)

Country Link
CN (1) CN114512536B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107123674A (en) * 2016-02-25 2017-09-01 苏州东微半导体有限公司 A kind of semiconductor super junction power device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5762689B2 (en) * 2010-02-26 2015-08-12 株式会社東芝 Semiconductor device
KR101452098B1 (en) * 2013-03-29 2014-10-16 삼성전기주식회사 Power semiconductor device and fabricating of the same
JP2016162861A (en) * 2015-02-27 2016-09-05 株式会社東芝 Semiconductor device
US9312381B1 (en) * 2015-06-23 2016-04-12 Alpha And Omega Semiconductor Incorporated Lateral super-junction MOSFET device and termination structure
CN111133586B (en) * 2017-10-05 2023-04-07 三菱电机株式会社 Semiconductor device with a plurality of semiconductor chips
CN109888004A (en) * 2019-01-08 2019-06-14 上海华虹宏力半导体制造有限公司 IGBT device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107123674A (en) * 2016-02-25 2017-09-01 苏州东微半导体有限公司 A kind of semiconductor super junction power device

Also Published As

Publication number Publication date
CN114512536A (en) 2022-05-17

Similar Documents

Publication Publication Date Title
US7923804B2 (en) Edge termination with improved breakdown voltage
US7504307B2 (en) Semiconductor devices including voltage-sustaining space-charge zone and methods of manufacture thereof
CN107482061B (en) Super junction device and manufacturing method thereof
CN106298932A (en) Lateral super junction MOSFET element and end on structure
US12057482B2 (en) MOSFET with distributed doped P-shield zones under trenches
CN106165101B (en) Semiconductor device
CN102376762B (en) Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
US11437510B2 (en) Trench MOSFET and method of manufacturing trench MOSFET
CN106816468B (en) Lateral diffusion metal oxide semiconductor field effect transistor with RESURF structure
CN108122975A (en) Superjunction devices
US11316021B2 (en) High density power device with selectively shielded recessed field plate
CN105027290B (en) The MOSFET technologies of adaptive charge balance
CN107564965B (en) Transverse double-diffusion MOS device
US20060043434A1 (en) Semiconductor devices and methods of manufacture thereof
CN111463131A (en) Super junction semiconductor device and manufacturing method thereof
CN114512536B (en) Super junction semiconductor device
CN111697058B (en) Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
CN115332338A (en) Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN115332340A (en) Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN112635559B (en) Planar gate superjunction MOSFET
US20210066494A1 (en) Semiconductor device
CN102522338A (en) Forming method of high-voltage super-junction metal oxide semiconductor field effect transistor (MOSFET) structure and P-shaped drift region
CN106684120B (en) Local unbalanced super-junction structure capable of improving voltage resistance
CN112864244B (en) Superjunction device
US20230163167A1 (en) Semiconductor device including a trench gate structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant