CN102593007A - Super junction device with multiple embedded P islands and N channels and preparation method thereof - Google Patents
Super junction device with multiple embedded P islands and N channels and preparation method thereof Download PDFInfo
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- CN102593007A CN102593007A CN201210076796XA CN201210076796A CN102593007A CN 102593007 A CN102593007 A CN 102593007A CN 201210076796X A CN201210076796X A CN 201210076796XA CN 201210076796 A CN201210076796 A CN 201210076796A CN 102593007 A CN102593007 A CN 102593007A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 230000003292 diminished effect Effects 0.000 claims abstract description 4
- 229910052796 boron Inorganic materials 0.000 claims description 20
- -1 boron ion Chemical class 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 17
- 230000000903 blocking effect Effects 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 18
- 210000000746 body region Anatomy 0.000 abstract 1
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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Abstract
The invention provides a super junction device with multiple embedded P islands and N channels and a preparation method thereof. The super junction device comprises a semiconductor substrate, an N-type drift region formed on the semiconductor substrate, P-type body regions on one side of the N-type drift region, and N-type leakage regions on the other side of the N-type drift region, wherein a plurality of parallel island-shaped P areas are formed in the N-type drift region at intervals, and each island-shaped P area is gradually diminished in a linear manner from N-type source regions to the N-type leakage regions; the function of the substrate-assisted depletion effect is sequentially enhanced from source ends to leakage ends under a high voltage, so that the island-shaped P areas are correspondingly decreased from the source ends to the leakage ends, and accordingly, the complementation and offset to the substrate-assisted depletion effect are realized, and the purpose of charge balance is achieved.
Description
Technical field
The present invention relates to a kind of semiconductor device and preparation method thereof, particularly relate to ultra junction device of a kind of embedded many P island N raceway groove and preparation method thereof.
Background technology
Power integrated circuit is also claimed high voltage integrated circuit sometimes; It is the important branch that hyundai electronics is learned; Can be various Power Conversions and energy processing unit provides the new-type circuit of high speed, high integration, low-power consumption and anti-irradiation, is widely used in many key areas such as current consumption fields such as electric control system, automotive electronics, display device driving, communication and illumination and national defence, space flight.The rapid expansion of its range of application is also had higher requirement to the high tension apparatus of its core.
As far as power device MOSFET, under the prerequisite that guarantees puncture voltage, the conducting resistance that must reduce device as much as possible improves device performance.But there is a kind of approximate quadratic relationship between puncture voltage and the conducting resistance, forms so-called " silicon limit ".In order to solve this contradiction, forefathers have proposed to be used to optimize by P, the alternate super-junction structure that constitutes of N post based on the drift region of three-dimensional RESURF technology the drift region Electric Field Distribution of high tension apparatus.This structure is keeping improving puncture voltage under the constant prerequisite of conducting resistance, and the theoretical limit of power MOS (Metal Oxide Semiconductor) device breaks traditions.This technological theoretical foundation is that charge compensation is theoretical, and when the drift region applied voltage and reaches certain value, the drift region reached fully and exhausts, and Electric Field Distribution is more even, has improved the breakdown characteristics of device.Guaranteeing significantly to improve the doping content of drift region under the constant prerequisite of puncture voltage, reduce conducting resistance.Conventional power MOSFET device " the silicon limit " has been broken in the proposition of super-junction structure.
Super-junction structure is applied to vertical VDMOS device at first, expands to horizontal LDMOS device afterwards.Forming the horizontal super-junction structure of N ditch at present, mainly is repeatedly that ion is infused in formation column P district in the N type drift region.Extenuate substrate-assisted depletion effect and also propose several different methods,, adopt Sapphire Substrate or etched substrate etc. like extra increase N type layer.See also Fig. 1; Be shown as the structural representation of horizontal ultra junction-semiconductor device in the prior art, as shown in the figure, the structure of described ultra junction-semiconductor device comprises: P type substrate 11; On P type substrate 11, be provided with super-junction structure 12 and P type tagma 13; Super-junction structure 12 is made up of with N type district 122 p type island region 121 that connection source-drain area direction distributes alternately, and above P type tagma 13, is provided with N type source region 14, P type body contact zone 15 and gate oxide 16, above super-junction structure 12, is provided with N type drain region 17.Because above-mentioned transversary more helps the integrated application of high-density power of a new generation, be the focus of contemporary power device research.
But super-junction structure is used for transversal device has also brought new problem: the first, be difficult on the desirable P that can exhaust fully, the N post district technology form; Second; Substrate is participated in exhausting of ultra knot post district and is caused substrate-assisted depletion effect; And the width of depletion layer do not wait at the drain terminal of the device diverse location to the source extreme direction, and this need be optimized device making technics and structure with regard to having brought the uneven problem of drift region Electric Field Distribution.
Summary of the invention
The shortcoming of prior art the object of the present invention is to provide ultra junction device of a kind of embedded many P island N raceway groove and preparation method thereof in view of the above, is used for solving the uneven problem of prior art drift region Electric Field Distribution.
For realizing above-mentioned purpose and other relevant purposes, the present invention provides the preparation method of the ultra junction device of a kind of embedded many P island N raceway groove, and said preparation method may further comprise the steps at least:
1) semi-conductive substrate is provided, is infused in preparation one deck N type drift region on the said Semiconductor substrate through N type ion; Provide one to offer the mask plates that ion that many groups are arranged in parallel injects window, said many group ions inject windows and reduce successively from the side trend opposite side of said mask plate;
2) in said N type drift region, inject boron ion and blocking by said mask plate to control the CONCENTRATION DISTRIBUTION of boron ion;
3) with the annealing of said Semiconductor substrate, with in said N type drift region, form apart from one another by and a plurality of island P district of being arranged in parallel, and respectively this island P district is diminished towards other end linearity by the one of which end;
4) on said N type drift region and the stub end that closes on said island P district prepare P type tagma, and above said P type tagma, prepare N type source region, P type body contact zone and gate oxide; On said N type drift region and the little head end that closes on said island P district prepare N type drain region.
Step 2 in preparation method of the present invention) in; Through repeatedly repeating in said N type drift region, to inject boron ion and blocking by said mask plate to control the CONCENTRATION DISTRIBUTION of boron ion; And in said step 3) after the annealing, with in said N type drift region, form a plurality of apart from one another by and laterally be arranged in parallel and island P district that parallel longitudinal is arranged.
Said Semiconductor substrate is body silicon substrate or SOI substrate.
Said N type drift region and island P district are formed in the top layer silicon of said SOI substrate.
Said island P district be from N type source region towards N type drain region direction on from large to small P island structure.
The present invention also provides a kind of embedded many P island N raceway groove ultra junction device; Comprise: Semiconductor substrate; Be formed on the N type drift region on the said Semiconductor substrate; Be positioned at said N type drift region one side and include the P type tagma of N type source region, P type body contact zone and gate oxide, and be positioned at the N type drain region on the opposite side of said N type drift region, wherein; Be formed with in the said N type drift region a plurality of apart from one another by and the island P district that is arranged in parallel, and respectively the direction linearity diminishes towards N type drain region by N type source region in this island P district.
Preferably, a plurality of island P district that forms in the said N type drift region apart from one another by and laterally be arranged in parallel and parallel longitudinal is arranged.
Preferably, said Semiconductor substrate is body silicon substrate or SOI substrate.
Preferably, said N type drift region and island P district are formed in the top layer silicon of said SOI substrate.
Preferably, said island P district be from N type source region towards N type drain region direction on from large to small P island structure.
As stated, ultra junction device of embedded many P of the present invention island N raceway groove and preparation method thereof is directly to be infused in through ion to form a plurality of embedded island P districts in the N type drift region.Any one direction is the N type around the embedded island P district; Exhaust between the two; End strengthens to drain terminal successively from the source owing to substrate-assisted depletion effect effect under high pressure, thus island P district correspondingly from the source end to the drain terminal direction on from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating; Finally reach charge balance, and then solved Electric Field Distribution uneven problem in drift region in the prior art.
Description of drawings
Fig. 1 is shown as the structural representation of horizontal ultra junction-semiconductor device in the prior art.
Fig. 2, Fig. 4 and Fig. 5 are shown as the view that the present invention prepares embedded many P island N raceway groove super-junction structure.
Fig. 3 is shown as the mask plate structure sketch map that uses among the preparation method of the present invention.
Fig. 6 is shown as the ultra junction device structural representation of the embedded many P of the present invention island N raceway groove.
Fig. 7 is shown as another execution mode sketch map of preparation method of the present invention.
The element numbers explanation
11 P type substrates
12 super-junction structures
121 p type island regions
122 N type districts
13,24 P type tagmas
14,25 N type source regions
15,26 P type body contact zones
16,27 gate oxides
17,28 N type drain regions
21 Semiconductor substrate
22 N type drift regions
23 island P districts
3 mask plates
31 ions inject window
Embodiment
Below through specific instantiation execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention can also implement or use through other different embodiment, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 2 to Fig. 7.Need to prove; The diagram that is provided in the present embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality; Kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.
Embodiment one
The present invention provides the preparation method of the ultra junction device of a kind of embedded many P island N raceway groove, and this preparation method may further comprise the steps:
In step 1), semi-conductive substrate 21 is provided, be infused in preparation one deck N type drift region 22 on the said Semiconductor substrate 21 through N type ion; Particularly, said Semiconductor substrate 21 is body silicon substrate or SOI substrate.See also Fig. 2; As shown in the figure, in the present embodiment, be that the SOI substrate is that example describes with Semiconductor substrate 21 temporarily; Said N type drift region 22 is formed in the top layer silicon of said SOI substrate; Particularly, in the top layer silicon of said SOI substrate, mix the N type ion (like phosphorus, arsenic, antimony etc.) of V group element, the position that makes it to replace silicon atom in the lattice is to form N type drift region 22.
Then; Provide one to offer the mask plates 3 that the ion that is arranged in parallel injects window 31 of organizing more; Said many group ion injection windows 31 reduce from the side trend opposite side of said mask plate 3 successively, and a side of said mask plate 3 trend opposite side shield portions increases successively.See also Fig. 3, be shown as the mask plate structure sketch map that uses among the preparation method of the present invention.
In step 2) in, boron ion and blocking in said N type drift region 22, injected by said mask plate 3 to control the CONCENTRATION DISTRIBUTION of boron ion; See also Fig. 4; Promptly injecting window 31 1 sides trend opposite side through an ion reduces successively; And the mask plate that shield portions increases successively, the boron ion that is used to form many P island structure in the N type drift region 22 injects, to reach the purpose of the CONCENTRATION DISTRIBUTION of controlling the boron ion.
In step 3); With step 2) middle Semiconductor substrate 21 annealing of injecting the boron ion; With in said N type drift region 22, form apart from one another by and a plurality of island P district 23 of being arranged in parallel, and respectively this island P district 23 is diminished towards other end linearity by the one of which end, sees also Fig. 5.
In step 4), on said N type drift region 22 and the stub end that closes on said island P district 23 prepare P type tagma 24, and above said P type tagma 24, prepare N type source region 25, P type body contact zone 26 and gate oxide 27; On said N type drift region 22 and the little head end that closes on said island P district 23 prepare N type drain region 28.See also Fig. 6; Said island P district 23 be from N type source region 25 towards N type drain region 28 directions on from large to small P island structure, the stub end of this P island structure closes on said P type tagma 24, the little head end of this P island structure closes on said N type drain region 28; Because any one direction is the N type around the embedded island P district 23; Exhaust between the two, and end strengthens to drain terminal successively from the source owing to substrate-assisted depletion effect effect under high pressure, thus island P district 23 correspondingly from the source end to the drain terminal direction on from large to small; To realize and the counteracting of substrate-assisted depletion effect action compensating, finally reach charge balance.
Embodiment two
Step 1) and step 4) are identical in present embodiment and the foregoing description one; So will not give unnecessary details; In the step 2 in this enforcement, through repeatedly repeating in said N type drift region 22 to inject the boron ion and, and in step 3), anneal by the CONCENTRATION DISTRIBUTION of blocking of said mask plate 3 with control boron ion; And then can in said N type drift region 22, form a plurality of apart from one another by and laterally be arranged in parallel and island P district 23 that parallel longitudinal is arranged, be as shown in Figure 7.
Embodiment three
The present invention also provides a kind of embedded many P island N raceway groove ultra junction device; See also Fig. 6; Be shown as the ultra junction device structural representation of the embedded many P of the present invention island N raceway groove, as shown in the figure, the ultra junction device of said embedded many P island N raceway groove comprises: Semiconductor substrate 21; Be formed on the N type drift region 22 on the said Semiconductor substrate 21; Be positioned at the P type tagma 24 of said N type drift region 22 1 sides, and be positioned at the N type drain region 28 on 22 opposite sides of said N type drift region, include N type source region 25, P type body contact zone 27 and gate oxide 27 on the said P type body 24.
Be formed with in the said N type drift region 22 a plurality of apart from one another by and the island P district 23 that is arranged in parallel, and respectively 28 direction linearities diminish towards N type drain region by N type source region 25 in this island P district 23.Said Semiconductor substrate 21 is body silicon substrate or SOI substrate.
In concrete preparation process, said N type drift region 22 is through injecting the boron ion and forming by the CONCENTRATION DISTRIBUTION of blocking with control boron ion of the mask plate of preset figure.See also Fig. 4; The mask plate 3 of described preset figure offers the ion injection window 31 that many groups are arranged in parallel; Said many group ion injection windows 31 reduce from the side trend opposite side of said mask plate 3 successively, and a side of said mask plate 3 trend opposite side shield portions increases successively.Promptly; In the process of injecting the boron ion, inject window 31 1 sides trend opposite side through an ion and reduce successively, and the mask plate that increases successively of shield portions; The boron ion that is used to form many P island structure in the P type drift region 22 injects, to reach the purpose of the CONCENTRATION DISTRIBUTION of controlling the boron ion.
In the present embodiment; Be that the SOI substrate is that example describes with Semiconductor substrate 21 temporarily; Said N type drift region 22 is formed in the top layer silicon of said SOI substrate; Particularly, in the top layer silicon of said SOI substrate, mix V group element (like phosphorus, arsenic, antimony etc.), the position that makes it to replace silicon atom in the lattice is to form N type drift region 22.Said N type drift region 22 and island P district 23 are formed in the top layer silicon of said SOI substrate.Said island P district 23 be from N type source region 25 towards N type drain region 28 directions on from large to small P island structure; The stub end of this P island structure closes on said P type tagma 24; The little head end of this P island structure closes on said N type drain region 28, because any one direction is the N type around the embedded island P district 23, exhausts between the two; And end strengthens to drain terminal successively from the source owing to substrate-assisted depletion effect effect under high pressure; Therefore island P district 23 correspondingly from the source end to the drain terminal direction on from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating, finally reach charge balance.
In another embodiment, a plurality of island P district 23 that forms in the said N type drift region 22 apart from one another by and laterally be arranged in parallel and the parallel longitudinal arrangement.
In sum, ultra junction device of embedded many P of the present invention island N raceway groove and preparation method thereof is directly to be infused in through ion to form a plurality of embedded island P districts in the N type drift region.Any one direction is the N type around the embedded island P district; Exhaust between the two; End strengthens to drain terminal successively from the source owing to substrate-assisted depletion effect effect under high pressure, thus island P district correspondingly from the source end to the drain terminal direction on from large to small, to realize and the counteracting of substrate-assisted depletion effect action compensating; Finally reach charge balance, and then solved Electric Field Distribution uneven problem in drift region in the prior art.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.
Claims (10)
1. the preparation method of the ultra junction device of embedded many P island N raceway groove is characterized in that said preparation method may further comprise the steps at least:
1) semi-conductive substrate is provided, is infused in preparation one deck N type drift region on the said Semiconductor substrate through N type ion; Provide one to offer the mask plates that ion that many groups are arranged in parallel injects window, said many group ions inject windows and reduce successively from the side trend opposite side of said mask plate;
2) in said N type drift region, inject boron ion and blocking by said mask plate to control the CONCENTRATION DISTRIBUTION of boron ion;
3) with the annealing of said Semiconductor substrate, with in said N type drift region, form apart from one another by and a plurality of island P district of being arranged in parallel, and respectively this island P district is diminished towards other end linearity by the one of which end;
4) on said N type drift region and the stub end that closes on said island P district prepare P type tagma, and above said P type tagma, prepare N type source region, P type body contact zone and gate oxide; On said N type drift region and the little head end that closes on said island P district prepare N type drain region.
2. the preparation method of the ultra junction device of embedded many P according to claim 1 island N raceway groove; It is characterized in that: in said step 2) in; Through repeatedly repeating in said N type drift region, to inject boron ion and blocking by said mask plate to control the CONCENTRATION DISTRIBUTION of boron ion; And in said step 3) after the annealing, in said N type drift region, form a plurality of apart from one another by and laterally be arranged in parallel and island P district that parallel longitudinal is arranged.
3. the preparation method of the ultra junction device of embedded many P according to claim 1 island N raceway groove is characterized in that: said Semiconductor substrate is body silicon substrate or SOI substrate.
4. the preparation method of the ultra junction device of embedded many P according to claim 3 island N raceway groove is characterized in that: said N type drift region and island P district are formed in the top layer silicon of said SOI substrate.
5. according to the preparation method of claim 1, the ultra junction device of 2 or 4 described embedded many P island N raceway grooves, it is characterized in that: said island P district is from large to small P island structure on from N type source region towards N type drain region direction.
6. ultra junction device of embedded many P island N raceway groove; It is characterized in that; Comprise: Semiconductor substrate, be formed on the N type drift region on the said Semiconductor substrate, be positioned at said N type drift region one side and include the P type tagma of N type source region, P type body contact zone and gate oxide; And be positioned at the N type drain region on the opposite side of said N type drift region; Wherein, be formed with in the said N type drift region a plurality of apart from one another by and the island P district that is arranged in parallel, and respectively the direction linearity diminishes towards N type drain region by N type source region in this island P district.
7. the ultra junction device of embedded many P according to claim 6 island N raceway groove is characterized in that: a plurality of island P district that forms in the said N type drift region apart from one another by and laterally be arranged in parallel and parallel longitudinal is arranged.
8. the ultra junction device of embedded many P according to claim 6 island N raceway groove is characterized in that: said Semiconductor substrate is body silicon substrate or SOI substrate.
9. the ultra junction device of embedded many P according to claim 8 island N raceway groove is characterized in that: said N type drift region and island P district are formed in the top layer silicon of said SOI substrate.
10. according to claim 6, the ultra junction device of 7 or 9 described embedded many P island N raceway grooves, it is characterized in that: said island P district is from large to small P island structure on from N type source region towards N type drain region direction.
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| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
| CN108447787A (en) * | 2018-03-20 | 2018-08-24 | 重庆大学 | A kind of transverse direction super-junction structure gallium nitride HEMT device and its manufacturing method |
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| CN102969244B (en) * | 2012-12-11 | 2015-03-25 | 中国科学院上海微系统与信息技术研究所 | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof |
| CN103579351A (en) * | 2013-11-22 | 2014-02-12 | 电子科技大学 | LDMOS (laterally diffused metal oxide semiconductor) device provided with super-junction buried layer |
| CN104409519A (en) * | 2014-11-10 | 2015-03-11 | 电子科技大学 | Diode with floating island structure |
| CN108447787A (en) * | 2018-03-20 | 2018-08-24 | 重庆大学 | A kind of transverse direction super-junction structure gallium nitride HEMT device and its manufacturing method |
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