JP6597826B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as a diode used in a high voltage power module (≧ 600 V).

  Since the dawn of the semiconductor in the 1950s, various studies have been made on the high-frequency oscillation phenomenon (see, for example, Non-Patent Document 1) and the destruction phenomenon (see, for example, Non-Patent Document 2) in Si-based pin diodes. In recent years, these phenomena that cause malfunctions of peripheral circuits and surge destruction of the devices themselves have been attracting attention again in power devices that are operating at higher speeds (see, for example, Non-Patent Document 3).

In fast recovery diodes, these phenomena have been found to be significant under hard recovery conditions such as high Vcc, high wiring inductance (Ls), low operating temperature, and low current density (JA) (eg, non-patent literature). 5, 11). In the high-speed recovery diode, the above-mentioned problems are caused by so-called “soft recovery” such as adoption of a thick n ⁻ -type drift layer or a thick n-type buffer layer and application of lifetime control technology (for example, see Non-Patent Documents 5 to 7). It has been solved. However, these methods have a trade-off relationship between EMI (Electromagnetic Compatibility) noise, breakdown tolerance, and total loss, and it is difficult to achieve both at a high level.

On the other hand, the main characteristics of the diode are remarkably improved by a diode (see, for example, non-patent documents 4, 8, and 9) in which a p ⁺ -type layer is formed on the back surface including an RFC diode (for example, refer to non-patent documents 10 to 14). It was. However, as further development issues, expansion of the operating temperature range to the high temperature side by lowering the leakage current, improvement of the maximum cut-off current density by lowering VF (voltage drop when the diode is on) in the high current density region, and Improvements in avalanche resistance by strengthening the buffer structure remained.

In addition, a diode has been proposed in which an n-type buffer layer having an intermediate impurity concentration is provided between an n ⁻ -type drift layer and an n-type cathode layer (see, for example, Patent Documents 1 and 2). Although the specific numerical value of the concentration gradient of the n-type buffer layer is not described in Patent Document 1, from FIG. 3 of Patent Document 1, the concentration gradient can be estimated as 8 × 10 ³ cm ⁻¹ . Moreover, the n-type buffer layer of Patent Document 2 has the configuration described in Non-Patent Document 10, and the concentration gradient is 1 × 10 ⁵ cm ⁻¹ .

JP 2007-158320 A JP 2010-283132 A

W. T. READ, JR, “A Proposed High-Frequency, Negative-Resistance Diode,” The Bell system technical journal, pp. 401-446 (March 1958) H. Egawa, “Avalanche Characteristics and Failure Mechanism of High Voltage Diodes,” IEEE Trans. Electron Devices, vol. ED-13, No. 11, pp. 754-758 (1966) R. Siemieniec, P. Mourick, J. Lutz, M. Netzel, “Analysis of Plasma Extraction Transit Time Oscillations in Bipolar Power Devices,” Proc. ISPSD'04, pp. 249-252, Kitakyushu, Japan (2004) K. Satoh, K. Morishita, Y. Yamaguchi, N. Hirano, H. Iwamoto and A. Kawakami, “A Newly Structured High Voltage Diode Highlighting Oscillation Free Function in Recovery Process,” Proc. ISPSD'2000, pp. 249-252, Toulouse, France (2000) M.T. Rahimo and N. Y. A. Shammas, “Optimization of the Reverse Recovery Behavior of Fast Power Diodes Using Injection Efficiency And Lifetime Control Techniques,” Proc. EPE'97, pp. 2.099-2.104, Trondheim, Norway (1997) M. Nemoto, T. Naito, A. Nishihara, K. Ueno, “MBBL diode: a novel soft recovery diode,” Proc. ISPSD'04, pp. 433-436, Kitakyushu, Japan H. Fujii, M. Inoue, K. Hatade and Y. Tomomatsu, “A Novel Buffer Structure and lifetime control Technique with Poly-Si for Thin Wafer Diode,” Proc. ISPSD'09, pp. 140-143, Barcelona, Spain (2009) A. Kopta and M. Rahimo, “The Field Charge Extraction (FCE) Diode A Novel Technology for Soft Recovery High Voltage Diodes,” Proc. ISPSD'05, pp. 83-86, Santa Barbara, California, USA (2005) HP Felsl, M. Pfaffenlehner, H. Schulze, J. Biermann, Th. Gutt, H. -J. Schulze, M. Chen and J. Luts, “The CIBH Diode-Great Improvement for Ruggedness and Softness of High Voltage Diodes, ”Proc. ISPSD'08, pp. 173-176, Orlando, Florida, USA (2008) K. Nakamura, Y. Hisamoto, T. Matsumura, T. Minato and J. Moritani, “The Second Stage of a Thin Wafer IGBT Low Loss 1200V LPT-CSTBTTM with a Backside Doping Optimization Process,” Proc. ISPSD'06, pp 133-136, Naples, Italy (2006) K. Nakamura, H. Iwanaga, H. Okabe, S. Saito and K. Hatade, “Evaluation of Oscillatory Phenomena in Reverse Operation for High Voltage Diodes,” Proc. ISPSD'09, pp. 156-159, Barcelona, Spain ( 2009) K. Nakamura, F. Masuoka, A. Nishii, K. Sadamatsu, S. Kitajima and K. Hatade, “Advanced RFC Technology with New Cathode Structure of Field Limiting Rings for High Voltage Planar Diode,” Proc. ISPSD'10, pp 133-136, Hiroshima, Japan (2010) A. Nishii, K. Nakamura, F. Masuoka and T. Terashima, “Relaxation of Current Filament due to RFC Technology and Ballast Resistor for Robust FWD Operation,” Proc. ISPSD'11, pp. 96-99, San Diego, California , USA (2011) F. Masuoka, K. Nakamura, A. Nishii and T. Terashima, “Great Impact of RFC Technology on Fast Recovery Diode towards 600 V for Low Loss and High Dynamic Ruggedness,” Proc. ISPSD'12, pp. 373-376, Bruges, Belgium (2012)

In the conventional semiconductor device, since the slope of the carrier concentration in the connection portion between the n ⁻ type drift layer and the n type buffer layer is steep as 8 × 10 ³ cm ⁻¹ or 1 × 10 ⁵ cm ⁻¹ , the electric field in the connection portion is Increased strength causes snap-off. Furthermore, there has been a problem that high-frequency oscillation occurs using snap-off as a trigger.

  Further, the trade-off characteristics between VF and recovery loss EREC of a conventional diode have been adjusted by a lifetime control method using heavy metal diffusion or electron or ion irradiation. However, variations in VF and EREC are large depending on the irradiation angle and temperature with the irradiated object during electron or ion irradiation. Further, the lattice characteristics change due to self-heating during the chip energization operation, and the electrical characteristics fluctuate. Furthermore, a large amount of leakage current due to lattice defects causes thermal runaway during high temperature operation. For this reason, establishment of the control method of the VF-EREC trade-off characteristic which does not depend on a lifetime control method has been desired.

Power devices have been used for various purposes, and avalanche resistance has been required for IGBTs, diodes, and the like. However, in a semiconductor device having a parasitic bipolar transistor structure, the avalanche resistance is reduced as compared with a semiconductor device without such a structure. Further, when the thickness of the n ⁻ -type drift layer is reduced in order to improve the VF-EREC characteristics, the avalanche resistance is remarkably lowered. Further, in a semiconductor device having a parasitic bipolar transistor structure, the maximum controllable current density is lower than that of a semiconductor device without such a structure.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of realizing a high oscillation tolerance.

A semiconductor device according to the present invention includes an n-type drift layer, a p-type base layer provided on an upper surface of the n-type drift layer, an n-type emitter layer partially provided on the p-type base layer, A trench gate provided so as to penetrate the n-type emitter layer and the p-type base layer; a p-type collector layer provided on a lower surface of the n-type drift layer; the n-type drift layer and the p-type collector; An n-type buffer layer provided between the layers, and the carrier concentration peak of the n-type buffer layer is higher than that of the n-type drift layer and lower than that of the p-type collector layer. The concentration is the same as the carrier concentration of the n-type drift layer at the interface with the n-type drift layer, and increases from the n-type drift layer side to the p-type collector layer side. And p Wherein the natural logarithm of the slope of the carrier concentration across the n-type buffer layer when the natural logarithm of the carrier concentration was expressed in correspondence to the distance toward the p-type collector layer from the n-type drift layer between the collector layer characterized in that it is a 20～2000Cm ^-1 in.

  According to the present invention, a high oscillation tolerance can be realized.

It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. 1 is a bottom view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing in alignment with I-II of FIG.1 and FIG.2. It is a figure which shows the carrier concentration with respect to the depth. _{V F,} E _REC on the natural logarithm of the slope ∇n _buffer carrier _density, V _snap-off, is a diagram showing a _{J A (break).} It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device which concerns on a comparative example. It is a figure which shows the peak density | concentration and diffusion depth of the n-type buffer layer used for simulation. It is a figure which shows the simulation result of the thickness dependence of the buffer layer of the pressure | voltage resistant waveform in a comparative example and Embodiment 3. FIG. It is a figure which shows the simulation result of the Vcc dependence of the snappy recovery waveform in a comparative example and Embodiment 3. FIG. It is a figure which shows the simulation result of the Vcc dependence of the snappy recovery waveform in a comparative example and Embodiment 3. FIG. It is a back view which shows the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing in alignment with I-II of FIG. It is sectional drawing in alignment with III-IV of FIG. It is a bottom view which shows the modification 1 of the semiconductor device which concerns on Embodiment 4 of this invention. It is a bottom view which shows the modification 2 of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 7 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 8 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 9 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 10 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 11 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 12 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 13 of this invention.

  A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
1 and 2 are a top view and a bottom view, respectively, showing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line I-II in FIGS. 1 and 2. A p-type anode layer 2 is provided on the upper surface of the n ⁻ -type drift layer 1. An n-type cathode layer 3 is provided on the lower surface of the n ⁻ -type drift layer 1.

An n-type buffer layer 4 is provided between the n ⁻ -type drift layer 1 and the n-type cathode layer 3. The peak concentration of impurities in the n-type buffer layer 4 is higher than that of the n ⁻ -type drift layer 1 and lower than that of the n-type cathode layer 3. The anode electrode 5 is in ohmic contact with the p-type anode layer 2, and the cathode electrode 6 is in ohmic contact with the n-type cathode layer 3.

FIG. 4 is a diagram showing the carrier concentration with respect to the depth. The depth of the n-type buffer layer 4 is D _buffer , the slope of the natural logarithm of the carrier concentration at the connection portion of the n-type drift layer and the n-type buffer layer is the concentration gradient ∇ n _buffer [cm ⁻¹ ], and the n-type buffer layer 4 Is an effective dose amount of φ _eff [cm ⁻² ], and the carrier concentration of the n ⁻ -type drift layer 1 is n ₀ [cm ⁻³ ]. These relationships are expressed by the following mathematical formula.

FIG. 5 is a diagram showing V _F , E _REC , V _snap-off , and J _{A (break)} with respect to the natural logarithmic slope ∇ n _buffer of the carrier concentration. V _F is the voltage drop in the ON state, E _REC is the recovery loss, V _snap-off is the overshoot voltage at the time of recovery, and J _{A (break)} is the maximum controllable current density. Based on this data, in order to lower V _F , E _REC , and V _snap-off and to increase J _{A (break)} , the concentration gradient n _{buffer is set} to 20 to 2000 cm ⁻¹ . In the prior art, the concentration gradient is about 10 ⁵ cm ^−1, which is steep compared to the present embodiment.

A deep buffer structure in which the carrier concentration at the connection portion between the n ⁻ type drift layer 1 and the n type buffer layer 4 is loose and broadly distributed as in the present embodiment is referred to as a CPL (Controlling Plasma Layer) buffer structure. With this CPL buffer structure, it is possible to suppress an increase in electric field strength at the same boundary during recovery. As a result, snap-off caused by an increase in the electric field intensity on the cathode side and high-frequency oscillation generated using the snap-off as a trigger can be prevented, so that a high oscillation tolerance can be realized.

Further, the effective dose φ _eff of the n-type buffer layer 4 is set to 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² higher than the effective dose of the n ⁻ -type drift layer 1. As a result, the total dose amount of the n-type buffer layer 4 is approximately the same as the total dose amount of the n ⁻ -type drift layer 1, so that the breakdown voltage can be maintained in both the n ⁻ -type drift layer 1 and the n-type buffer layer 4. Therefore, the thickness of the n ⁻ type drift layer 1 necessary for maintaining the equivalent breakdown voltage can be reduced as compared with the case where the n type buffer layer 4 is not provided, and the total loss can be reduced.

The carrier concentration n ₀ of the n ⁻ type drift layer 1 is determined depending on the breakdown voltage class. As an example, in the case of the 600 to 6500 V class, the carrier concentration n ₀ is 1 × 10 ¹² to 1 × 10 ¹⁵ cm ⁻³ . The surface concentration of the n-type cathode layer 3 is 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ³ , and the diffusion depth is 0.5 to 2 μm. The thickness D _buffer of the n-type buffer layer 4 is a function of n ₀ , ∇n _buffer , and φ _eff as shown in the above formula.

The ratio of the peak concentration of the n-type buffer layer 4 to the peak concentration of the n ⁻ -type drift layer 1 is 1 × 10 ⁻⁴ to 1 × 10 ⁻¹ . The depth ratio between the n-type buffer layer 4 and the n ⁻ -type drift layer 1 is 0.1 to 10.

Embodiment 2. FIG.
FIG. 6 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. Although the first embodiment is a diode, this embodiment is an IGBT (Insulated Gate Bipolar Transistor).

The p-type anode layer 2 is a p-type base layer, and its peak concentration is 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ cm ⁻³ . A p ⁺ type diffusion layer 7 and an n ⁺ type emitter layer 8 are partially formed on the surface of the wafer on the p type anode layer 2. The n ⁺ type emitter layer 8 has a peak concentration of 1.0 × 10 ^{18 to} 1.0 × 10 ²¹ cm ⁻³ and a depth of 0.2 to 1.0 μm.

An n ⁺ type layer 9 is formed between the p type anode layer 2 and the n ⁻ type drift layer 1. The n ⁺ -type layer 9 has a peak concentration of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ cm ⁻³ and a depth 0.5 to 1.0 μm deeper than the p-type anode layer 2.

A trench gate 10 is provided so as to penetrate the n ⁺ -type emitter layer 8, the p-type anode layer 2 and the n ⁺ -type layer 9. An interlayer insulating film 11 is provided on the trench gate 10. The anode electrode 5 is an emitter electrode and is connected to the p ⁺ type diffusion layer 7. A p-type collector layer 12 is provided in place of the n-type cathode layer 3. The cathode electrode 6 is a collector electrode and is in ohmic contact with the p-type collector layer 12.

The n-type buffer layer 4 has a peak concentration higher than that of the n ⁻ -type drift layer 1 and lower than that of the p-type collector layer 12. As in the first embodiment, the slope of the natural logarithm of the carrier concentration at the connection portion between the n ⁻ type drift layer 1 and the n type buffer layer 4 is set to 20 to 2000 cm ⁻¹ . Then, the effective dose φ _eff of the n-type buffer layer 4 is set to 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² which is higher than the effective dose of the n ⁻ -type drift layer 1. Thereby, even if it is a case of IGBT, the effect similar to Embodiment 1 can be acquired.

Embodiment 3 FIG.
FIG. 7 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention. Instead of the single-layer n-type cathode layer 3 of the first embodiment, the n-type cathode layer 3 and the p-type cathode layer 13 are alternately arranged side by side. The cathode electrode 6 is in ohmic contact with the n-type cathode layer 3 and the p-type cathode layer 13. Therefore, the p-type cathode layer 13 is short-circuited with the n-type cathode layer 3 through the cathode electrode 6. The peak concentration of the n-type cathode layer 3 is higher than that of the p-type cathode layer 13.

The following relationship holds among the depth tn ^{− of the} n ⁻ type drift layer 1, the width Wn of the n type cathode layer 3, and the width Wp of the p type cathode layer 13.
2 · tn ⁻ ≧ (Wn + Wp) ≧ tn ⁻ / 10

  The effect of this embodiment will be described in comparison with a comparative example. Specifically, the dependence of the peak concentration and diffusion depth of the n-type buffer layer 4 on Vrrm, snap-off resistance and recovery resistance in the diodes of the present embodiment and the comparative example designed to withstand voltage 1700 V will be described. FIG. 8 is a cross-sectional view showing a semiconductor device according to a comparative example. In the comparative example, the n-type buffer layer 4 is not provided, and the n-type cathode layer 3 is a single layer.

Here, the tolerance of the recovery condition with respect to the peak voltage V _{snap-off in} FIG. The higher the snap-off tolerance, the higher the allowable operation under so-called hard recovery conditions such as high applied voltage, low current, low temperature, and high-speed current interruption. In addition, a safe operation region composed of the applied voltage Vcc and the maximum cut-off current density _{JA (break)} shown in FIG. The higher the recovery tolerance, the more acceptable the recovery operation under high applied voltage and large current density conditions.

FIG. 9 is a diagram showing the peak concentration and diffusion depth of the n-type buffer layer used in the simulation. As shown in this figure, the dose amount was fixed at 3.75 × 10 ¹² cm ⁻² , and the peak concentration and diffusion depth set by triangular approximation were set to simulate the n-type buffer layer 4 having a Gaussian distribution. Regardless of the thickness of the n-type buffer layer 4, the thickness of the n ⁻ -type drift layer 1 is constant.

FIG. 10 is a diagram illustrating simulation results of the buffer layer thickness dependency of the withstand voltage waveform in the comparative example and the third embodiment. Both diodes are designed to withstand voltage 1700V. 11 and 12 are diagrams illustrating simulation results of Vcc dependency of the snappy recovery waveform in the comparative example and the third embodiment. The peak concentration of the n-type buffer layer 4 is 5 × 10 ¹⁶ cm ⁻³ , and the thickness of the n-type buffer layer 4 is 1.5 μm in FIG. 11 and 50 μm in FIG.

In the comparative example, electrons generated by impact ionization due to an increase in electric field strength at the main junction travel to the cathode side due to a high electric field in the n ⁻ type drift layer 1. As a result, when the electron concentration exceeds the carrier concentration in the buffer layer, the gradient of the electric field in the n-type buffer layer 4 is reversed from the relationship of the Poisson equation, and the electric field strength increases on the cathode side in addition to the main junction. . Therefore, in the comparative example, as the n-type buffer layer 4 is thicker, the characteristic of the negative differential resistance NDR appears more remarkably from about JR = 10 A / cm ² . In the vicinity of JR = 100 to 1000 A / cm ² , impact ionization occurs on both the main junction and the cathode side, and electrons and holes are supplied into the n ⁻ -type drift layer 1 from both the main junction side and the cathode side, It leads to secondary surrender.

On the other hand, in the present embodiment, NDR characteristics do not appear in the breakdown voltage waveform, and when the n-type buffer layer 4 is thin, secondary breakdown appears around JR = 1 A / cm ² of the breakdown voltage waveform. Since this secondary breakdown in the small current region causes a decrease in the maximum breaking current density and avalanche resistance in the diode recovery SOA, it is required to increase the generation point of the secondary breakdown. On the other hand, a diode structure exhibiting NDR characteristics generates a voltage surge and snap-off due to the rise of the electric field on the cathode side during recovery, and high frequency oscillation is likely to occur using this as a trigger (see FIGS. 11 and 12). ). For this reason, the breakdown voltage waveform of the diode does not show an S-curve due to NDR characteristics or secondary breakdown, and needs to be close to a linear line. From FIG. 10, it is better that the n-type buffer layer 4 is thicker.

However, if the thickness of the n ⁻ type drift layer 1 is kept constant and the n type buffer layer 4 is simply made thick, the resistance component in the ON state increases, leading to an increase (deterioration) in VF. Therefore, in the present embodiment, the slope of the natural logarithm of the carrier concentration at the connection portion between the n ⁻ type drift layer 1 and the n type buffer layer 4 is set to 20 to 2000 cm ⁻¹ . By relaxing the concentration change in the connection portion in this way, secondary breakdown and NDR of the withstand voltage waveform can be prevented, and an increase in electric field strength at the connection portion during recovery can be suppressed while suppressing an increase in VF. As a result, snap-off caused by an increase in the electric field intensity on the cathode side and high-frequency oscillation generated using the snap-off as a trigger can be prevented, so that a high oscillation tolerance can be realized.

  The width represented by (Wn + Wp) is referred to as an RFC cell pitch. If the RFC cell pitch is made finer, VF increases and EREC decreases. That is, the VF-EREC trade-off curve shifts to the high speed side. Therefore, when this embodiment is applied to a free wheel diode incorporated in an inverter, the VF-EREC trade-off characteristic can be adjusted by adjusting the RFC cell pitch according to the application. However, if the RFC cell pitch is set too fine, the snap-off resistance is reduced, and conversely if the setting is too coarse, the recovery resistance is reduced.

  Further, a ratio represented by (Wp / (Wn + Wp)) is called an RFC cell short-circuit rate. When the RFC cell short-circuit rate is reduced, VF increases and EREC decreases. That is, the VF-EREC trade-off curve shifts to the high speed side. Therefore, when this embodiment is applied to a freewheel diode incorporated in an inverter, the VF-EREC trade-off characteristic can be adjusted by adjusting the RFC cell short-circuit rate according to the application. However, if the RFC cell short-circuit rate is set too small, the snap-off resistance decreases, the cross point increases, and conversely if it is set too large, the recovery resistance decreases.

  Thus, in the present embodiment, the VF-EREC trade-off characteristic can be controlled without depending on the lifetime control method by adjusting the RFC cell pitch or the RFC cell short-circuit rate.

  Further, when the dose amount of the p-type cathode layer 13 is reduced, the snap-off resistance is reduced, but EREC and leakage current can be suppressed. Increasing the dose of the P-type cathode layer 13 gives the opposite result. On the other hand, in this embodiment, the snap-off resistance and the recovery resistance can be secured, and the allowable range for setting the dose amount of the p-type cathode layer 13 can be expanded.

  In a simple pn junction, the temperature dependence of VF is basically positive, and current easily flows as the temperature rises. In a large-capacity power module in which power chips are connected in parallel, if the temperature distribution of the chip is biased, a positive feedback occurs in which more current flows through the chip that generates a large amount of heat and heat is generated, which may cause module destruction. There is sex. Therefore, it is desirable that the current value (cross point) at which the room temperature VF curve intersects the high temperature VF curve is low. In this embodiment, since the effective dose amount of the anode and the cathode can be lowered and the carrier injection efficiency from both can be lowered, a cross point at a low current value can be realized.

  Further, the cathode electrode 6 may be in ohmic contact with the n-type cathode layer 3 and may be in Schottky contact with the p-type cathode layer 13. Since the Schottky barrier difference between the cathode electrode 6 and the p-type cathode layer 13 is large, a state similar to that in which a resistance component is added to the parasitic pnp transistor is obtained, and device vertical operation due to the operation of the parasitic pnp transistor is performed. Directional current can be suppressed. As a result, a high recovery SOA and a high avalanche resistance can be realized.

Embodiment 4 FIG.
FIG. 13 is a back view showing the semiconductor device according to the fourth embodiment of the present invention. FIG. 14 is a cross-sectional view taken along the line I-II in FIG. Instead of the single-layer n-type buffer layer 4 of the third embodiment, the n-type buffer layers 4 and the n-type buffer layers 14 are alternately arranged side by side. The n-type buffer layer 4 is provided between the n ⁻ -type drift layer 1 and the n-type cathode layer 3, and the n-type buffer layer 14 is provided between the n ⁻ -type drift layer 1 and the p-type cathode layer 13. The n-type buffer layers 4 and 14 have a peak concentration higher than that of the n ⁻ -type drift layer 1 and lower than that of the n-type cathode layer 3. The peak concentration of the n-type buffer layer 4 is higher than that of the n-type buffer layer 14. Other configurations are the same as those of the third embodiment.

FIG. 15 is a cross-sectional view taken along line III-IV in FIG. The region where the p-type anode layer 2 is provided is an active region, and the region outside it is a termination region. A general p-type guard ring layer 15 is provided on the anode side of the termination region, and an n-type channel stopper layer 16 is provided on the outermost periphery of the termination region. The peak concentration of the p-type guard ring layer 15 is higher than that of the p-type anode layer 2, and the peak concentration of the n-type channel stopper layer 16 is higher than that of the n ⁻ -type drift layer 1.

  The cathode structure of the termination region starts from a position away from the outermost periphery of the p-type anode layer 2 by a distance WGR: 10 to 500 μm from the active region side. The cathode structure of the termination region is a two-layer structure of an n-type layer 17 and a p-type layer 18.

  In the present embodiment, by increasing the dose amount of the n-type buffer layer 4 on the n-type cathode layer 3, the electron injection efficiency from the cathode side in the ON state is increased. In addition, when an induced electromotive force in the L load circuit is applied to bring the device into an avalanche state, the depletion layer does not easily reach the p-type cathode layer 13, and NDR (secondary breakdown) of the breakdown voltage waveform is suppressed. The As a result, a low VF and a high avalanche resistance can be realized. The tolerance of the avalanche state is called avalanche resistance.

  The n-type cathode layer 3 and the p-type cathode layer 13 have a stripe pattern. Thereby, a pattern reflecting the assumed ratio of the n-type cathode layer 3 and the p-type cathode layer 13 can be easily designed.

  FIG. 16 is a bottom view showing a first modification of the semiconductor device according to the fourth embodiment of the present invention. As described above, the same effect as described above can be obtained even if the cathode of the termination region is n-type.

  FIG. 17 is a bottom view showing a second modification of the semiconductor device according to the fourth embodiment of the present invention. The n-type cathode layer 3 is a dot pattern. As a result, it is possible to design a pattern in consideration of the corner portion, and to realize uniform device operation. As a result, a high recovery SOA can be realized. The same effect can be obtained even if the p-type cathode layer 13 is a dot pattern.

Embodiment 5. FIG.
FIG. 18 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. The n-type buffer layer 4 is deeper than the n-type buffer layer 14. Other configurations are the same as those of the fourth embodiment. Even in this case, the same effect as in the fourth embodiment can be obtained.

Embodiment 6 FIG.
FIG. 19 is a sectional view showing a semiconductor device according to the sixth embodiment of the present invention. Instead of the single-layer p-type anode layer 2 of the fourth embodiment, the p-type anode layer 2 and the p-type anode layer 19 are alternately arranged side by side. The anode electrode 5 is in ohmic contact with the p-type anode layers 2 and 19. Therefore, the p-type anode layer 19 is short-circuited with the p-type anode layer 2 through the anode electrode 5. The peak concentration of the p-type anode layer 19 is lower than that of the p-type anode layer 2. The peak concentration ratio between the p-type anode layer 2 and the p-type anode layer 19 is 0.5 to 500.

By providing the low-concentration p-type anode layer 19, the anode-side injection efficiency in the on-state is suppressed, so the carrier concentration on the anode-side in the on-state decreases, and the electric field strength on the cathode side that is the trigger for oscillation is reduced. Lifting can be suppressed. In addition, since the number of carriers in the n ⁻ type drift layer 1 is small in the ON state, it is possible to suppress a phenomenon in which carriers are concentrated at the boundary portion between the termination region and the active region during the recovery and cause destruction. As a result, high recovery SOA, high oscillation tolerance, low VF, low crosspoint, and high surge current tolerance can be realized.

Embodiment 7 FIG.
FIG. 20 is a sectional view showing a semiconductor device according to the seventh embodiment of the present invention. The p-type anode layer 19 is provided only on a part of the upper surface of the p-type anode layer 2. The ratio of the depth of the p-type anode layer 19 to the depth of the p-type anode layer 2 is 0.1 to 0.9. Even in this case, the same effect as in the sixth embodiment can be obtained.

Embodiment 8 FIG.
FIG. 21 is a sectional view showing a semiconductor device according to the eighth embodiment of the present invention. Only a single n-type layer 17 is provided on the lower surface of the n ⁻ -type drift layer 1 in the termination region. The cathode electrode 6 is in contact with and electrically connected to the n-type layer 17. The n-type layer 17 has a peak concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ . Thereby, the contact resistance of the n-type buffer layer 14 with respect to the cathode electrode 6 increases. Therefore, in the ON state, injection of electrons from the cathode side of the termination region can be suppressed, and the recovery SOA can be increased.

Embodiment 9 FIG.
FIG. 22 is a sectional view showing a semiconductor device according to the ninth embodiment of the present invention. The n-type buffer layer 4 is a single layer, and the cathode structure of the termination region is also a single layer of the n-type layer 17. Thereby, the configuration can be further simplified as compared with the eighth embodiment.

Embodiment 10 FIG.
FIG. 23 is a sectional view showing a semiconductor device according to the tenth embodiment of the present invention. An n-type channel stopper buffer layer 20 is provided on the outermost periphery of the termination region. An n-type channel stopper layer 21 and a p-type channel stopper layer 22 are provided in the n-type channel stopper buffer layer 20. The peak concentration of the n-type channel stopper buffer layer 20 is higher than that of the n ⁻ -type drift layer 1. The peak concentration of the n-type channel stopper layer 21 is higher than that of the n-type channel stopper buffer layer 20 and the p-type channel stopper layer 22. Thereby, a high recovery SOA can be realized.

Embodiment 11 FIG.
FIG. 24 is a sectional view showing a semiconductor device according to the eleventh embodiment of the present invention. Instead of a general p-type guard ring layer 15, an LNFLR (Linearly-Narrowed Field Limiting Ring) structure 23 is provided. The LNFLR structure 23 is a plurality of p-type layers that are periodically arranged in parallel from the active region toward the termination region. The plurality of p-type layers have a linear concentration gradient toward the termination region.

A RESURF (Reduced Surface Field) structure 24 is provided between the p-type anode layer 2 in the active region and the LNFLR structure 23. The RESURF structure 24 has a deep p layer formed at the end of the active region and a p layer having the same diffusion depth as the diffusion layer of the LNFLR structure 23. The dose of the RESURF structure 24 is 2 × 10 ¹² / m ² and the width is 5 to 100 μm. By providing the RESURF structure 24, the electric field peak at the time of recovery can be reduced.

Embodiment 12 FIG.
FIG. 25 is a cross-sectional view showing a semiconductor device according to Embodiment 12 of the present invention. Instead of the RESURF structure 24 of the eleventh embodiment, a VLD (Variation of Lateral Doping) structure 25 is provided in the present embodiment. The VLD structure 25 has a deep p layer formed at the end of the active region, and a p layer having a gradient so as to connect the deep p layer and the depth of the LNFLR diffusion layer.

Embodiment 13 FIG.
FIG. 26 is a sectional view showing a semiconductor device according to the thirteenth embodiment of the present invention. An IGBT is provided in the active region, and an LNFLR structure 23 is provided in the termination region. Even in this case, an effect similar to that of the eleventh embodiment can be obtained.

  Note that the semiconductor device of the present application is not limited to one formed of silicon, and may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A semiconductor device formed of such a wide band gap semiconductor has high voltage resistance and high allowable current density, and thus can be miniaturized. By using this miniaturized device, a semiconductor module incorporating this device can also be miniaturized. Further, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized and the water cooling part can be air cooled, so that the semiconductor module can be further miniaturized. In addition, since the power loss of the element is low and the efficiency is high, the efficiency of the semiconductor module can be increased.

  In the above embodiment, the low / medium withstand voltage class of 1200V or 1700V class has been described as an example. However, the above effects can be obtained regardless of the breakdown voltage class.

1 n ⁻ type drift layer, 2, 19 p type anode layer, 3 n type cathode layer, 4, 14 n type buffer layer, 6 cathode electrode, 12 p type collector layer, 13 p type cathode layer, 17 n type layer, 20 n-type channel stopper buffer layer, 21 n-type channel stopper layer, 22 p-type channel stopper layer, 23 LNFLR structure, 24 RESURF structure, 25 VLD structure

Claims (3)

an n-type drift layer;
A p-type base layer provided on an upper surface of the n-type drift layer;
An n-type emitter layer partially provided on the p-type base layer;
A trench gate provided so as to penetrate the n-type emitter layer and the p-type base layer;
A p-type collector layer provided on the lower surface of the n-type drift layer;
An n-type buffer layer provided between the n-type drift layer and the p-type collector layer;
The peak of the carrier concentration of the n-type buffer layer is higher than the n-type drift layer and lower than the p-type collector layer,
The carrier concentration of the n-type buffer layer is the same as the carrier concentration of the n-type drift layer at the interface with the n-type drift layer, and increases from the n-type drift layer side toward the p-type collector layer side. And
The natural logarithm of the carrier concentration when the natural logarithm of the carrier concentration between the n-type drift layer and the p-type collector layer is expressed in correspondence with the distance from the n-type drift layer to the p-type collector layer. The inclination of the semiconductor device is 20 to 2000 cm ⁻¹ in the entire n-type buffer layer . 2. The semiconductor device according to claim 1, wherein an effective dose amount of the n-type buffer layer is 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² and is higher than the n-type drift layer. An LNFLR (Linearly-Narrowed Field Limiting Ring) structure in which a plurality of p-type layers have a linear concentration gradient from the active region toward the termination region;
The semiconductor device according to claim 1, further comprising a RESURF (Reduced Surface Field) structure provided at an outer end portion of the p-type base layer.

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