CN117525157A - Double-channel groove device and manufacturing method thereof - Google Patents
Double-channel groove device and manufacturing method thereof Download PDFInfo
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Abstract
The application provides a double-channel groove device and a manufacturing method thereof, and relates to the technical field of semiconductors. The double-channel trench device comprises a first doping type substrate, a first doping type epitaxial layer, a second doping type shielding layer, a first doping region and a first doping type expanding layer, wherein the second doping region is positioned on the surface of the second doping type shielding layer, the third doping region is positioned on the surface of the first doping type expanding layer, and the fourth doping region is positioned on the surface of the third doping region, the third doping region is of a second doping type, and the fourth doping region is of a first doping type; the gate oxide layer, the second doped region wraps the bottom corner of the gate oxide layer, and the first doped region wraps the corner of the second doped region; gate polysilicon in contact with the gate oxide layer; source metal and drain metal. The method has the advantage of improving the electrical performance and reliability of the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a double-channel groove device and a manufacturing method thereof.
Background
The trench gate structure of the SiC MOSFET has advantages mainly from the longitudinal trench, not only can improve carrier mobility, but also can reduce the structure size and increase the cell density, thereby having lower specific on-resistance (specific on-resistance) and faster switching speed than a planar MOSFET, but the problem of gate oxide reliability in the trench gate SiC MOSFET design is more serious than that of the planar SiC MOSFET because the internal working electric field intensity is very high when the device works in a high blocking voltage state, especially the bottom corner of the trench gate close to 90 degrees further aggravates the concentration of electric lines, and the maximum critical electric field intensity is extremely easy to exceed at the position, thereby causing the gate oxide layer at the position to be broken down, causing the problem of gate oxide failure and affecting the reliability of the device.
In summary, in the prior art, the problem that the gate oxide layer of the SiC MOSFET trench device is easily broken down at the trench corner position and the device reliability is low exists.
Disclosure of Invention
The purpose of the application is to provide a double-channel groove device and a manufacturing method thereof, so as to solve the problems that a gate oxide layer of a SiC MOSFET groove device in the prior art is easy to break down at a groove corner position and the reliability of the device is low.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, embodiments of the present application provide a dual channel trench device, the dual channel trench device comprising:
a first doping type substrate;
a first doping type epitaxial layer on the surface of the substrate;
the first doping region is respectively in contact with the second doping type shielding layer and the first doping type expansion layer, the first doping region is of a second doping type, and the doping concentration of the first doping region is smaller than that of the second doping type shielding layer;
the second doping region is positioned on the surface of the second doping type shielding layer, is of a first doping type and is in contact with the first doping region;
the third doping region is positioned on the surface of the first doping type expansion layer, the fourth doping region is positioned on the surface of the third doping region, the third doping region is of a second doping type, and the fourth doping region is of a first doping type;
the gate oxide layer is respectively contacted with the second doped region, the first doping type expansion layer and the third doped region; the widths of the first doping region, the third doping region and the gate oxide layer contact region are equal, and the doping concentrations of the first doping region and the third doping region are equal;
the second doped region wraps the bottom corner of the gate oxide layer, and the first doped region wraps the corner of the second doped region;
gate polysilicon in contact with the gate oxide layer;
source metal in contact with the fourth doped region, the second doped region and the second doping type shielding layer;
and the drain electrode metal is positioned on the back surface of the substrate.
Optionally, the first doping type expansion layer includes a plurality of fifth doping regions, and doping concentrations of the plurality of fifth doping regions gradually increase along the epitaxial growth direction.
Optionally, the dual-channel trench device further includes a first contact metal layer and a sixth doped region, the sixth doped region is respectively in contact with the first contact metal layer on a side of the second doping type shielding layer away from the first doped region, and the sixth doped region forms schottky contact with the source metal through the first contact metal layer.
Optionally, the dual-channel trench device further includes a second contact metal layer, and the fourth doped region, the second doped region, and the second doping type shielding layer are in contact with the source metal through the second contact metal layer.
Optionally, the first doping type is N-type doping, and the second doping type is P-type doping.
Optionally, a side of the top of the gate polysilicon and away from the gate oxide layer is provided in an arc shape.
Optionally, the dual channel trench device includes a cell structure composed of two MOSFET device cells and a schottky diode located between the two MOSFET device cells, and wherein the second doping type shielding layer of the MOSFET device cells that do not need to be operated is grounded.
Optionally, the dual-channel trench device further includes a first dielectric layer, the side edge of the gate polysilicon is in contact with the gate oxide layer, the bottom of the gate polysilicon is in contact with the first dielectric layer, and the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the gate oxide layer.
Optionally, the dual-channel trench device further includes a second dielectric layer, the second dielectric layer is located on a side of the gate polysilicon and away from a side of the gate oxide layer, an ILD layer is disposed on a surface of the gate polysilicon, and a thermal expansion coefficient of the second dielectric layer is smaller than a thermal expansion coefficient of the ILD layer.
On the other hand, the embodiment of the application also provides a manufacturing method of the double-channel groove device, which is used for manufacturing the double-channel groove device, and the manufacturing method of the double-channel groove device comprises the following steps:
providing a first doping type substrate;
manufacturing a first doping type epitaxial layer based on the surface of the substrate;
a second doping type shielding layer, a first doping region, a first doping type expanding layer, a second doping region, a third doping region and a fourth doping region are manufactured on the basis of one side of the epitaxial layer, wherein the first doping region is respectively contacted with the second doping type shielding layer and the first doping type expanding layer, the first doping region is of a second doping type, and the doping concentration of the first doping region is smaller than that of the second doping type shielding layer; the second doping region is positioned on the surface of the second doping type shielding layer, the second doping region is of a first doping type, and the second doping region is in contact with the first doping region; the third doped region is positioned on the surface of the first doping type expansion layer, the fourth doped region is positioned on the surface of the third doped region, the third doped region is of a second doping type, and the fourth doped region is of a first doping type;
etching the device and forming a groove, and growing a gate oxide layer based on the groove, wherein the gate oxide layer is respectively contacted with the second doped region, the first doping type expansion layer and the third doped region; the widths of the first doping region, the third doping region and the gate oxide layer contact region are equal, and the doping concentrations of the first doping region and the third doping region are equal; the second doped region wraps the bottom corner of the gate oxide layer, and the first doped region wraps the corner of the second doped region;
manufacturing grid polycrystalline silicon contacted with the grid oxide layer;
manufacturing a source metal in contact with the fourth doped region, the second doped region and the second doping type shielding layer;
and manufacturing drain electrode metal positioned on the back surface of the substrate.
Compared with the prior art, the application has the following beneficial effects:
the application provides a double-channel groove device and a manufacturing method thereof, and through the structure of the double-channel groove device, in the first aspect, a single-side double-longitudinal inversion channel can be realized, so that the on-resistance of the device is reduced, and the switching speed is improved. In the second aspect, through the second doping type shielding layer and the first doping area, the effects of electric field shielding and electric field buffering can be simultaneously achieved at the bottom of the grid groove, particularly at the corner position of the grid oxide layer, the width and the depth of the second doping type shielding layer and the first doping area can be flexibly adjusted, and the grid oxide reliability and the device robustness are better due to common modulation. At the same time, the equivalent base region resistance R of the parasitic transistor can be reduced b The parasitic transistor is bypassed as far as possible by enabling the abnormally large current to be far away from the base region position nearby the channel, so that the risk of starting the parasitic transistor is avoided, and the reliability of the device is improved. In the third aspect, the second doping type shielding layer is directly connected with the source electrode, so that the switching speed of the device can be further improved, and the switching speed of the device can be reducedLoss, the risk of trench leakage is avoided, and the electrical performance and reliability of the device are improved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a prior art trench device.
Fig. 2 is a schematic cross-sectional view of a dual-channel trench device according to an embodiment of the present application.
Fig. 3 is a simplified schematic diagram corresponding to fig. 2.
Fig. 4 is another simplified schematic diagram corresponding to a dual channel trench device according to an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a second doping type shielding layer according to an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of a first doped region according to an embodiment of the present application.
Fig. 7 is a schematic cross-sectional view of a second type of dual-channel trench device according to an embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of a third type of dual-channel trench device according to an embodiment of the present application.
Fig. 9 is a schematic cross-sectional view of a corresponding fourth dual-channel trench device according to an embodiment of the present application.
Fig. 10 is a schematic cross-sectional view of a dual-channel trench device according to a fifth embodiment of the present disclosure.
Fig. 11 to fig. 28 are schematic cross-sectional views corresponding to steps in a method for manufacturing a dual-channel trench device according to an embodiment of the present application.
Icon:
101-a substrate; 102-an epitaxial layer; 103-a second doping type shielding layer; 104-a first doped region; 105-a first doping type expansion layer; 1051-fifth doped region; 106-a second doped region; 107-a third doped region; 108-a fourth doped region; 109-PP layer; 110-a gate oxide layer; 111-gate polysilicon; 112-ILD layer; 113-a second contact metal layer; 114-a sixth doped region; 115-a first contact metal; 116-source metal; 117-drain metal; 118-a first dielectric layer; 119-a second dielectric layer.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The trench gate structure of SiC MOSFETs is widely used at present, but as described in the background art, the gate oxide layer of the trench device of the SiC MOSFET in the prior art is easily broken down at the trench corner position, resulting in lower reliability of the device.
For example, referring to fig. 1, a schematic cross-sectional view of a trench gate structure of a SiC MOSFET in the prior art is shown, in which 1 represents an n+ substrate, 2 represents an N-epi layer, 3 represents a P-type well region, 4 represents a source region, 5 represents a gate oxide layer, 6 represents gate polysilicon, and when a gate source voltage exceeds a turn-on threshold, a region of the P-type well region 3 adjacent to the gate oxide layer forms a conductive channel and forms a current path shown by an arrow a in the figure.
For the trench gate structure device, the condition of power line concentration can occur at the bottom corner (at the point B in the figure) of the trench gate close to 90 degrees, so that a gate oxide layer at the point B is easy to break down, the problem of gate oxide failure is caused, and the reliability of the device is reduced.
Therefore, the adoption of the internal structure with the optimized design, and the reduction of the working electric field intensity of the oxide layer at the bottom of the groove are the problems which must be solved firstly in the current groove gate SiC MOSFET structure design. However, the gate oxide breakdown generally and the on-resistance R ds,on Is a compromise, and according to the current existing technical route in the industry, the device structure design reduces the electrical stress born by the oxide layer at the corner position of the trench gate, and simultaneously easily introduces additional JFET resistance, such as making the current path from the drain to the longitudinal channel more complex or sacrificing the number of current channels, which leads to on-resistance R ds,on And increases significantly.
In addition, conventional SiC Trench MOSFETThe capacitance ratio of Crss (Cgd) to Ciss (Cgs+Cgd) is too large, the switching speed is reduced, the switching loss is increased, and the HFFOM is increasedThe high-frequency quality factor is larger, and meanwhile, the risk of self-opening and false opening of the device is larger.
In view of the above, in order to solve the above problems, the present application provides a dual channel trench device, and the dual channel trench device provided in the present application is exemplified as follows:
as an alternative implementation, referring to fig. 2, the dual channel trench device includes:
a first doping type substrate 101; a first doping type epitaxial layer 102 on the surface of the substrate 101; the second doping type shielding layer 103, the first doping region 104 and the first doping type expansion layer 105 are positioned on one side of the epitaxial layer 102, wherein the first doping region 104 is respectively in contact with the second doping type shielding layer 103 and the first doping type expansion layer 105, the first doping region 104 is of a second doping type, and the doping concentration of the first doping region 104 is smaller than that of the second doping type shielding layer 103; the second doped region 106 is located on the surface of the second doping type shielding layer 103, the second doped region 106 is of the first doping type, and the second doped region 106 is in contact with the first doped region 104; a third doped region 107 located on the surface of the first doping type expansion layer 105 and a fourth doped region 108 located on the surface of the third doped region 107, wherein the third doped region 107 is of the second doping type, and the fourth doped region 108 is of the first doping type; the gate oxide layer 110, the gate oxide layer 110 is respectively contacted with the second doped region 106, the first doped region 104, the first doping type expansion layer 105 and the third doped region 107; the widths of the contact areas of the first doped region 104, the third doped region 107 and the gate oxide layer 110 are equal, and the doping concentrations of the first doped region 104 and the third doped region 107 are equal; the second doped region 106 wraps around the bottom corner of the gate oxide layer 110, and the first doped region 104 wraps around the corner of the second doped region 106; gate polysilicon 111 in contact with the gate oxide layer 110; a source metal 116 in contact with the fourth doped region 108, the second doped region 106, and the second doping type shielding layer 103; a drain metal 117 located on the back side of the substrate 101.
The first doping type and the second doping type are opposite doping types, and the application does not limit the first doping type and the second doping type. As one implementation, the first doping type is N-type doping and the second doping type is P-type doping.
Referring to fig. 3, a simplified schematic diagram corresponding to fig. 2 is shown, and it can be seen that the device provided in the present application may implement a single-sided dual-longitudinal inversion channel, for example, in fig. 3, when the gate-source voltage is greater than the threshold value, the current channels include two channels C1 and C2 (arrows C1 and C2 respectively indicate two current paths). It can be appreciated that the channel region widths and doping concentrations corresponding to the two current channels are equal. On the basis, compared with a traditional single-side single-longitudinal inversion channel groove device (only one current channel exists at one side), the double-channel groove device provided by the application increases the number of parallel current channels, and two current channels are formed on the single-side longitudinal direction, so that the on-resistance of the device is reduced, the switching speed is improved, and the switching loss is reduced.
Meanwhile, through the second doping type shielding layer 103 and the first doping region 104, the effects of electric field shielding and electric field buffering can be achieved at the bottom of the gate groove, particularly at the corner position of the gate oxide layer 110, the width and the depth of the second doping type shielding layer and the first doping type shielding layer can be flexibly adjusted, and the gate oxide reliability and the device robustness are better due to common modulation. At the same time, the equivalent base region resistance R of the parasitic transistor can be reduced b The parasitic transistor is bypassed as far as possible by enabling the abnormally large current to be far away from the base region position nearby the channel, so that the risk of starting the parasitic transistor is avoided, and the reliability of the device is improved. In addition, since the second doping type shielding layer 103 is directly connected with the source electrode, the switching speed of the device can be further improved, the switching loss of the device can be reduced, the risk of trench leakage can be avoided, and the electrical performance and reliability of the device can be improved.
It should be noted that each structure described in the present application may be formed by a plurality of steps in a specific manufacturing process, which is not limited herein. In addition, in practical application, the dual-channel trench device is in a form of a cell structure, for example, each cell structure includes two MOSFET device units and a schottky diode, and the schottky diode is located between the two MOSFET device units. As shown in fig. 3, the cell structure includes two MOSFET device units D1 and D2 and a schottky diode therebetween, and the device structures between the two MOSFET device units D1 and D2 may be identical or slightly different, which is not limited in this application, and in the cell structure shown in fig. 3, the two MOSFET device units are identical. In addition, when the device is practically applied, a plurality of cell structures can be arranged in an array manner. In addition, the cell structure may not include a schottky diode, for example, in the dual-channel trench device provided in fig. 4 and fig. 4, only two MOSFET device cells D1 and D2 are included. On the basis of this, it will be understood that the single-sided dual longitudinal channel described herein refers to two longitudinal conductive channels in any MOSFET device cell of a cellular structure, for example, as shown in connection with fig. 3. In the MOSFET device cell D1, two longitudinal conduction channels are included, C1 and C2, and in the same way, two longitudinal conduction channels are also included in the MOSFET device cell D2.
By arranging the cell structure, independent arrangement of the grid electrode can be realized, the effective overlapping area between the grid electrode and the drain electrode can be reduced, and the capacitive coupling between the grid electrode and the drain electrode is partially shielded, so that the grid drain capacitance (miller capacitance) Cgd and the grid drain charge Qgd are greatly reduced, lower switching loss is obtained, the switching speed is higher, the high-frequency quality factor HFFOM is remarkably reduced, and the dynamic characteristic is greatly improved; meanwhile, the capacitance ratio of Crss/Ciss is improved, the risks of self-opening and false opening are effectively restrained, the switching characteristic is greatly improved, and the reliability of the device is improved; further reduce the chip area and the specific on-resistance R on,sp (R on* A, A is chip area).
The following describes the structures of the present application in detail with reference to fig. 2:
the second doping type shielding layer 103 may be configured as an L-shaped structure, referring to fig. 5, and includes a lateral shielding region P1 (shown in 11) and a longitudinal connecting region P2 (shown in 12), which are in contact with each other, and are both heavily doped with P-type, and may be sequentially prepared in a specific preparation process. And, the top of the vertical connection region P2 is connected to the source electrode through the second contact metal layer 113. And, the second doping layer is located above the lateral shielding region P1, and the second doping layer is also in contact with the second contact metal layer 113, and in order to achieve good ohmic contact with the source electrode, the second contact metal layer 113 may be made of Ni metal.
By arranging the second doping type shielding layer 103, a PN junction depletion layer (a depletion layer is formed between the epitaxial layer 102 and the second doping type shielding layer) can be formed below the gate trench in the reverse blocking state of the device, an electric field shielding effect can be achieved on the gate oxide layer, the maximum electric field in the gate oxide layer is transferred to the PN junction, the electric field intensity at the corner position of the trench gate is reduced, the electric stress born by the gate corner oxide layer is reduced, the gate oxide withstand voltage capability is improved, and the reliability of the device is improved.
Also, referring to fig. 6, the first doped region 104 may include an electric field buffer region P3 (shown as 13) and a channel region P4 (shown as 14), both of which are lightly doped with P-type, and the electric field buffer region P3 is disposed and L-type, as can be seen from fig. 6, the second doped layer wraps the corner region of the trench gate oxide, and the electric field buffer region P3 wraps the corner of the second doped layer. The electric field buffer region P3 is used to realize electric field buffering, and the channel region P4 is used to provide an on channel. Referring to fig. 3, the right side of the electric field buffer region P3 is in contact with the lateral shield region P1 of the second doping type shield layer 103.
Meanwhile, by introducing the first doped region 104 beside the second doping type shielding layer 103, an electric field buffering effect, particularly the corner position of the gate groove, can be achieved, the width and the depth of the first doped region and the second doped region can be flexibly adjusted, and the gate oxide reliability and the device robustness are better due to common modulation. In addition, the second doping type shielding layer 103 is contacted with the side first doping region 104, so that the equivalent base resistance R of the parasitic NPN transistor can be reduced b Simultaneously, the abnormal heavy current is far away from the base region position near the channel, and the parasitic NPN transistor is bypassed as far as possible, thereby avoiding the risk of starting the parasitic NPN transistor and effectively preventing dV/dt failure, avalanche failure and short circuit failure, and improves the reliability of the device.
In practical application, the on-resistance R ds,on With reference to fig. 6, in this application, the masking degree and thus the on-resistance R can be flexibly adjusted by adjusting the projection distance L of the edge of the second doping type shielding layer 103 from the edge of the gate angle and the depth H of the lateral shielding region P1 ds,on And the magnitude of the gate oxide withstand voltage can also relieve R onsp Contradiction with SCWT. Also, when the depth of the second doping type shielding layer 103 is large, a half super junction/super effect may be formed.
Referring to fig. 5 again, the second doping type shielding layer 103 is directly connected to the source electrode through the longitudinal connection region P2, so that the original Cgd can be converted into Cds, further improving the switching speed and reducing the switching loss. Meanwhile, after the source electrode is directly connected through the longitudinal connection region P2, floating of the second doping type shielding layer 103 can be avoided, so that when the device is converted from a blocking state to a conducting state, sufficient minority carriers (holes) are supplied to a charge region, dynamic depletion is better realized, the starting time of the device is reduced, the switching loss of the device is reduced, meanwhile, the leakage risk of a groove is avoided, and the electrical performance and reliability of the device are greatly improved.
In addition, by arranging the second doping type shielding layer 103, the first doping region 104 and the first doping type expanding layer 105, a special JFET structure can be formed, which is equivalent to introducing PN junction depletion region equivalent resistance capacitors with an automatic buffer inhibition function on a current path, when abnormal working conditions occur, the device can automatically and flexibly expand PN depletion regions at different positions, further, depletion layer equivalent resistance capacitors with different sizes can be automatically generated, the problems of EMI electromagnetic interference, oscillation, surge and the like are automatically restrained, and finally, the device has better electromagnetic interference, oscillation, surge, voltage and current overshoot resistance, stronger short circuit tolerance capability SCWT and high device reliability. In addition, the second doping type shielding layer 103 can effectively shield the electric field aggregation effect of the schottky contact, so that the problem of potential barrier reduction caused by overlarge electric field of the schottky contact area is solved, leakage current is reduced, and breakdown voltage is improved.
Referring to fig. 3 again, the first doping type expansion layer 105 may include a plurality of fifth doping regions 1051, where the fifth doping regions 1051 are disposed layer by layer, and the fifth doping regions 1051 are heavily doped with N-type. In this application, the first doping type expansion layer 105 includes 4 fifth doping regions, however, in other implementations, the first doping type expansion layer 105 may also include other numbers of fifth doping regions, which is not limited herein.
By introducing the first doping type expanding layer 105 with higher doping, the on-resistance of the current path can be further reduced, the switching speed is improved, and the switching loss is reduced.
Also, in one implementation, the doping concentrations of the plurality of fifth doping regions gradually increase along the epitaxial growth direction, that is, the concentrations from n+csl1 to n+csl4 in the figure may be set gradually from bottom to top. Through this arrangement mode, the concentration of n+csl1 at the bottom is the lowest, and then the first doped region 104 is matched to form transverse PN junctions with different depletion widths, so that the electric field buffering and electric field shielding effects are further improved, and the reliability of the device is improved.
It should be noted that, the concentration of n+csl1 is the lowest, and n+csl1 is connected to the corner of the first doped region, so that the peak value of the electric field near the corner of the first doped region can be further reduced, the breakdown capability of the region is improved, and the reliability of the gate oxide is further improved. That is, in the present application, the second doped region 106 wraps the trench gate oxide corner, so that breakdown is easily caused at the corner of the second doped region 106; by providing the connection between the corner of the first doped region 104 and the n+csl1 with low doping concentration, the electric field peak is easily far away from the gate corner and transferred to the corner, thereby improving the gate-oxide voltage withstand capability of the whole device.
The dual-channel trench device further includes a first contact metal 115 layer and a sixth doped region 114, the sixth doped region 114 is respectively in contact with the first contact metal 115 layer on a side of the second doping type shielding layer 103 away from the first doped region 104, and the sixth doped region 114 forms a schottky contact with the source metal through the first contact metal 115 layer. Wherein the first contact metal 115 layer may be a Ti/TiN layer.
By integrating the Schottky diode in the SiC MOSFET, the performance of the traditional PN junction body diode is improved, on one hand, the starting voltage of the diode device is reduced at normal temperature, on-state loss is reduced, the starting voltage of the third quadrant is earlier, the surge processing capacity of the MOSFET is improved, meanwhile, the Schottky diode is a multi-sub device, the minority carrier lifetime problem is not required to be considered, and the reverse recovery charge Q is reduced at high temperature rr Shortens the reverse recovery time t rr Switching power loss is reduced; on the other hand, the bipolar degradation problem is avoided, the power loss is reduced, the leakage current of the device is reduced, and the breakdown voltage of the device is improved.
And the Schottky diode is integrated in the SiC MOSFET, so that the performance of the external parallel SiC diode is improved, the cost of an additional SiC chip and the cost brought by a passive element and a cooling element are reduced on the basis of realizing better dynamic performance and reliability, the circuit topology structure and the packaging structure are simplified, the switching loss is reduced, and the power density and the efficiency of the system are improved.
By adjusting the width and depth of the longitudinal connection region P2 in the second doping type shielding layer 103, on one hand, the current channel structure of the schottky diode can be flexibly adjusted to adjust a proper forward current specification, on the other hand, the shielding depth can be flexibly adjusted, the surface electric field of the schottky diode can be better shielded, the leakage current can be reduced, the breakdown voltage can be improved, and better comprehensive performance and reliability of the MOSFET device can be realized.
With continued reference to fig. 3, in order to improve the reliability of the device, PP regions are further disposed at the sides of the third doped region 107 and the fourth doped region 108, the PP regions are heavily doped with P-type, and the PP regions and the fourth doped region 108 are both in contact with the second metal contact layer.
Naturally, the above description is only an example, and in practical application, the device structure may be adaptively adjusted. For example, in one implementation, referring to fig. 7, a side of the top of the gate polysilicon 111 away from the gate oxide layer 110 is configured as an arc (the X-mark is configured as an arc in the figure), and the arc angle can form a stress buffer with the interlayer dielectric ILD layer 112 layer, so as to reduce the thermal failure problem and further improve the device short circuit and surge reliability.
Alternatively, in the cell structure of the dual channel trench device, the structures of the two MOSFET device cells may be different, and referring to fig. 8, the schottky diode is located between the two MOSFET device cells, and the second doping type shielding layer of the MOSFET device cell that does not need to be operated is grounded.
It should be noted that, the second doping type shielding layer is grounded, which means that the entire grounded region is doped with P-type with high concentration, so that the MOSFET device unit which does not need to work cannot form an effective inversion layer at the position of the channel, and therefore, only one MOSFET device unit works and the other MOSFET device unit does not work in the same cell structure under the same gate-source voltage. For example, in fig. 8, after the high-concentration P-type doping is performed in the grounded region, the minority carriers are holes, the minority carriers are electrons, and the high-concentration doping is performed, so that the minority carrier concentration is low, and when the gate is given a specified gate-source voltage Vgs, the left MOSFET device cell already forms an inversion layer and operates, but the right MOSFET device cell cannot form an effective channel due to the low minority carrier concentration, so that the right MOSFET device cell does not operate.
Therefore, by adopting a single-side grounding mode, the effect that one MOSFET device unit works normally and the other MOSFET device unit does not work can be achieved. On the one hand, better gate oxide reliability can be realized, on the other hand, the width of the sixth doped region 114 of the integrated schottky diode device can be moderately increased, so that the size of the sixth doped region 114 is increased (for example, the width of the sixth doped region 114 in fig. 8 is obviously larger than that of the sixth doped region 114 in fig. 7), and meanwhile, the doping concentration of the sixth doped region 114 can be adjusted to more flexibly reduce forward on-resistance and on-voltage drop and reduce power loss.
In another implementation, referring to fig. 9, the dual-channel trench device further includes a first dielectric layer 118, the side edge of the gate polysilicon 111 is in contact with the gate oxide layer 110, the bottom of the gate polysilicon 111 is in contact with the first dielectric layer 118, and the dielectric constant of the first dielectric layer 118 is smaller than the dielectric constant of the gate oxide layer 110. For example, the first dielectric layer 118 may be a PI dielectric, and when the low dielectric constant dielectric is filled, it is inferred by gaussian theorem that the bottom of the trench can bear a peak electric field as large as possible, so that the gate oxide reliability of the trench device can be greatly improved.
Optionally, referring to fig. 10, the dual-channel trench device further includes a second dielectric layer 119, where the second dielectric layer 119 is located on a side of the gate polysilicon 111 away from the gate oxide layer 110, and an ILD layer 112 is disposed on a surface of the gate polysilicon 111, and a thermal expansion coefficient of the second dielectric layer 119 is smaller than a thermal expansion coefficient of the ILD layer 112.
Under the abnormal working conditions such as short circuit or surge high current, high temperature thermal mismatch easily occurs to generate huge stress so as to lead the ILD layer 112 to generate cracks, liquid Al at high temperature corrodes and penetrates the ILD layer 112 to cause device failure, heat in the groove is more easily gathered, and the failure probability is larger and the influence is more serious. And when the PI material is adopted to replace the interlayer dielectric ILD layer 112 on the side edge of the grid polysilicon 111, the PI thermal expansion coefficient is small, the internal stress of the film is small, and meanwhile, the compactness is good, the pinhole density is small, and the blocking performance is strong, so that the thermal failure problem can be greatly reduced, and the short circuit and surge reliability of the device can be improved.
Based on the implementation manner, the embodiment of the application also provides a method for manufacturing a double-channel trench device, which is used for manufacturing the double-channel trench device, and the method for manufacturing the double-channel trench device comprises the following steps:
s102, providing a first doping type substrate 101;
s104, manufacturing a first doping type epitaxial layer 102 on the basis of the surface of the substrate 101;
s106, a second doping type shielding layer 103, a first doping region 104, a first doping type expansion layer 105, a second doping region 106, a third doping region 107 and a fourth doping region 108 are manufactured on the basis of one side of the epitaxial layer 102, wherein the first doping region 104 is respectively contacted with the second doping type shielding layer 103 and the first doping type expansion layer 105, the first doping region 104 is of a second doping type, and the doping concentration of the first doping region 104 is smaller than that of the second doping type shielding layer 103; the second doped region 106 is located on the surface of the second doping type shielding layer 103, the second doped region 106 is of the first doping type, and the second doped region 106 is in contact with the first doped region 104; the third doped region 107 is located on the surface of the first doping type expansion layer 105, the fourth doped region 108 is located on the surface of the third doped region 107, the third doped region 107 is of the second doping type, and the fourth doped region 108 is of the first doping type;
s106, etching the device, forming a groove, and growing a gate oxide layer 110 based on the groove, wherein the gate oxide layer 110 is respectively contacted with the second doped region 106, the first doped region 104, the first doping type expansion layer 105 and the third doped region 107; the widths of the contact areas of the first doped region 104, the third doped region 107 and the gate oxide layer 110 are equal, and the doping concentrations of the first doped region 104 and the third doped region 107 are equal; the second doped region 106 wraps around the bottom corner of the gate oxide layer 110, and the first doped region 104 wraps around the corner of the second doped region 106;
s108, manufacturing gate polysilicon 111 in contact with the gate oxide layer 110;
forming a source metal 116 in contact with the fourth doped region 108, the second doped region 106 and the second doping type shielding layer 103;
and S110, manufacturing a drain metal 117 positioned on the back surface of the substrate 101.
The substrate 101 provided by the application can adopt a SiC substrate 101, the epitaxial layer 102 adopts homoepitaxy, the substrate 101 adopts an n+ substrate 101, and the epitaxial layer 102 adopts N-epitaxy.
In performing the step of S106, the following steps may be included:
first, referring to fig. 11, a first N-type layer is grown. Next, referring to fig. 12, a p+ implantation region is formed by ion implantation, and the implantation region is a part of the second doping type shielding layer 103.
Next, referring to fig. 13, a second N-type layer is grown, and ion implantation is performed beside the p+ implantation region to form a P-implantation region, where the P-implantation region is adjacent to the p+ implantation region, and it should be noted that the depth of the P-implantation region is not limited in this application, for example, the depth of the P-implantation region may be less than, equal to, or greater than the sum of the thicknesses of the first N-type layer and the second N-type layer.
Referring to fig. 14, an NP layer is formed by ion implantation. Referring to fig. 15, the third N-type layer is grown. Referring to fig. 16, P-type ion implantation is continued to form a channel layer, which is in contact with the P-implant region.
Referring to fig. 17, a fourth N-type layer is grown. Referring to fig. 18, ion implantation is performed on the surface of the fourth N-type layer to form a P-region, wherein the P-region is located in the fourth N-type layer.
Referring to fig. 19, N-type ion implantation is performed on the surface of the P-region. As shown in fig. 20, PP layer 109 is fabricated. As shown in fig. 21, the device is etched, the etching depth extends into the second N-type layer, and the etching width is within the P-implantation regions on both sides.
As shown in fig. 22, ion implantation is continued to form a vertical connection region at the side of the p+ implant region. As shown in fig. 23, a gate oxide layer 110 is fabricated; as shown in fig. 24, gate polysilicon 111 is filled; as shown in fig. 25, the gate polysilicon 111 is etched to form two separate gate polysilicon 111 regions; as shown in fig. 26, ILD layer 112 is filled and the ILD at the source opening location is etched. As shown in fig. 27, ild layer 112 is etched in the middle region and simultaneously etches bottom gate oxide layer 110 and exposes the middle schottky diode region. As shown in fig. 28, the first metal contact layer and the second metal contact layer are fabricated. And finally, manufacturing a source metal.
In summary, the present application provides a dual-channel trench device and a method for manufacturing the same, by using the dual-channel trench device structure provided in the first aspect, a single-sided dual-longitudinal inversion channel can be realized, thereby reducing the on-resistance of the device and improving the switching speed. In the second aspect, through the second doping type shielding layer and the first doping area, the effects of electric field shielding and electric field buffering can be simultaneously achieved at the bottom of the grid groove, particularly at the corner position of the grid oxide layer, the width and the depth of the second doping type shielding layer and the first doping area can be flexibly adjusted, and the grid oxide reliability and the device robustness are better due to common modulation. At the same time, the equivalent base region resistance R of the parasitic transistor can be reduced b The parasitic transistor is bypassed as far as possible by keeping the abnormal heavy current away from the base region position near the channel, thereby avoiding the parasitic transistor from being openedAnd the starting risk is increased, and the reliability of the device is improved. In the third aspect, the second doping type shielding layer is directly connected with the source electrode, so that the switching speed of the device can be further improved, the switching loss of the device is reduced, the risk of trench leakage is avoided, and the electrical performance and reliability of the device are improved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A dual channel trench device, the dual channel trench device comprising:
a first doping type substrate;
a first doping type epitaxial layer on the surface of the substrate;
the first doping region is respectively in contact with the second doping type shielding layer and the first doping type expansion layer, the first doping region is of a second doping type, and the doping concentration of the first doping region is smaller than that of the second doping type shielding layer;
the second doping region is positioned on the surface of the second doping type shielding layer, is of a first doping type and is in contact with the first doping region;
the third doping region is positioned on the surface of the first doping type expansion layer, the fourth doping region is positioned on the surface of the third doping region, the third doping region is of a second doping type, and the fourth doping region is of a first doping type;
the gate oxide layer is respectively contacted with the second doped region, the first doping type expansion layer and the third doped region; the widths of the first doping region, the third doping region and the gate oxide layer contact region are equal, and the doping concentrations of the first doping region and the third doping region are equal;
the second doped region wraps the bottom corner of the gate oxide layer, and the first doped region wraps the corner of the second doped region;
gate polysilicon in contact with the gate oxide layer;
source metal in contact with the fourth doped region, the second doped region and the second doping type shielding layer;
and the drain electrode metal is positioned on the back surface of the substrate.
2. The dual channel trench device of claim 1 wherein said first dopant type expansion layer comprises a plurality of fifth dopant regions having a dopant concentration that increases progressively in the direction of epitaxial growth.
3. The dual-channel trench device of claim 1, further comprising a first contact metal layer and a sixth doped region, the sixth doped region being in contact with a side of the second doping type shielding layer remote from the first doped region, the first contact metal layer, respectively, and the sixth doped region forming a schottky contact with the source metal through the first contact metal layer.
4. The dual-channel trench device of claim 1, further comprising a second contact metal layer through which the fourth doped region, second doped region, and second doping type shielding layer are in contact with the source metal.
5. The dual channel trench device of claim 1 wherein the first doping type is N-type doping and the second doping type is P-type doping.
6. The dual channel trench device of claim 1 wherein a side of the gate polysilicon top and away from the gate oxide layer is provided in an arc shape.
7. The dual channel trench device of claim 1 wherein the dual channel trench device comprises a cell structure of two MOSFET device cells and a schottky diode located between the two MOSFET device cells, and wherein the second doping type shielding layer of the MOSFET device cells that do not require operation is grounded.
8. The dual channel trench device of claim 1 further comprising a first dielectric layer, wherein a side of the gate polysilicon is in contact with the gate oxide layer, wherein a bottom of the gate polysilicon is in contact with the first dielectric layer, wherein a dielectric constant of the first dielectric layer is less than a dielectric constant of the gate oxide layer.
9. The dual channel trench device of claim 1 further comprising a second dielectric layer on a side of the gate polysilicon that is remote from the gate oxide layer, the surface of the gate polysilicon being provided with an ILD layer, the second dielectric layer having a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the ILD layer.
10. A method for fabricating a dual channel trench device according to any one of claims 1 to 9, the method comprising:
providing a first doping type substrate;
manufacturing a first doping type epitaxial layer based on the surface of the substrate;
a second doping type shielding layer, a first doping region, a first doping type expanding layer, a second doping region, a third doping region and a fourth doping region are manufactured on the basis of one side of the epitaxial layer, wherein the first doping region is respectively contacted with the second doping type shielding layer and the first doping type expanding layer, the first doping region is of a second doping type, and the doping concentration of the first doping region is smaller than that of the second doping type shielding layer; the second doping region is positioned on the surface of the second doping type shielding layer, the second doping region is of a first doping type, and the second doping region is in contact with the first doping region; the third doped region is positioned on the surface of the first doping type expansion layer, the fourth doped region is positioned on the surface of the third doped region, the third doped region is of a second doping type, and the fourth doped region is of a first doping type;
etching the device and forming a groove, and growing a gate oxide layer based on the groove, wherein the gate oxide layer is respectively contacted with the second doped region, the first doping type expansion layer and the third doped region; the widths of the first doping region, the third doping region and the gate oxide layer contact region are equal, and the doping concentrations of the first doping region and the third doping region are equal; the second doped region wraps the bottom corner of the gate oxide layer, and the first doped region wraps the corner of the second doped region;
manufacturing grid polycrystalline silicon contacted with the grid oxide layer;
manufacturing a source metal in contact with the fourth doped region, the second doped region and the second doping type shielding layer;
and manufacturing drain electrode metal positioned on the back surface of the substrate.
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