CN114709255B - Heterojunction-based high-power-density tunneling semiconductor device and manufacturing process thereof - Google Patents
Heterojunction-based high-power-density tunneling semiconductor device and manufacturing process thereof Download PDFInfo
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- CN114709255B CN114709255B CN202210349844.1A CN202210349844A CN114709255B CN 114709255 B CN114709255 B CN 114709255B CN 202210349844 A CN202210349844 A CN 202210349844A CN 114709255 B CN114709255 B CN 114709255B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 230000005641 tunneling Effects 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- 229910021389 graphene Inorganic materials 0.000 claims abstract description 139
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 35
- 230000008569 process Effects 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 30
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 23
- 238000005137 deposition process Methods 0.000 claims description 21
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- 238000000151 deposition Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 2
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 11
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 description 17
- 229910002804 graphite Inorganic materials 0.000 description 12
- 239000010439 graphite Substances 0.000 description 12
- -1 graphite alkene Chemical class 0.000 description 12
- 238000009825 accumulation Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
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- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
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Abstract
The invention discloses a heterojunction-based high-power density tunneling semiconductor device and a manufacturing process thereof, wherein a device cell structure comprises: an N+ substrate with drain metal arranged below and an N-drift region arranged above; a pair of grooves are symmetrically arranged in the N-drift region, a P+ region is arranged at the bottom of the groove, a graphene source region is arranged in the groove, source metal is arranged on the graphene source region, a gate dielectric layer which is partially overlapped with the graphene source region is arranged on the N-drift region, a polysilicon gate is arranged on the gate dielectric layer, a passivation layer is arranged on the polysilicon gate, and a heterojunction is formed between the graphene source region and the N-drift region. The device structure has low requirement on the injection process, small cell size and large cell number in unit area, greatly improves the power density of the device, effectively reduces the specific on-resistance and subthreshold swing of the device, simplifies the manufacturing process and reduces the cost of the device. When the device is reversely biased to withstand voltage, the P+ region enables an electric field peak value to be transferred from a heterojunction boundary to a PN junction boundary, so that avalanche capacity of the device is improved, and breakdown voltage is increased.
Description
Technical Field
The invention mainly relates to the field of high-voltage power semiconductor devices, in particular to a heterojunction-based high-power density tunneling semiconductor device and a manufacturing process thereof, which are suitable for application fields of coexistence of extreme environments such as automobile electronics, rail transit, photovoltaic inversion, aerospace, aviation, petroleum exploration, nuclear energy, radar and communication and the like, and high-temperature, high-frequency, high-power, strong radiation and the like.
Background
The power semiconductor device plays a role in the power electronics industry and has wide application in automobiles, household appliances, high-speed rails and power grids. However, conventional power devices have a number of disadvantages, such as: the cell size is large, the on-resistance is large, the interface state density is high, the manufacturing process is complex, the doping process can damage the semiconductor surface, and the like.
The conduction band and the valence band of the graphene material are symmetrical, and only intersect at the vertex of the Brillouin zone, namely, intersect at a point on the Fermi surface, so that the graphene material has an obvious controllable electronic band gap. According to the characteristic of energy band symmetry of the graphene material, doping or external field application can destroy the energy band symmetry, so that the band gap is opened, and the size of the band gap can be controlled. The graphene material has the characteristics of a semiconductor energy band and has the characteristic of high metal conductivity. The graphene material has the characteristics of high mobility, high heat conductivity, high-temperature stability, capability of being manufactured in a large area and the like, and meets the requirements of power semiconductor devices.
Shown in fig. 1 is a conventional silicon carbide power semiconductor device comprising: the N+ type substrate 1, one side of the N+ type substrate 1 is connected with drain metal 10, the other side of the N+ type substrate 1 is provided with an N-type drift region 2, a pair of P-type base regions 3, an N+ type source region 5 and a P+ type body contact region 4 are symmetrically arranged in the N-type drift region 2, a gate oxide layer 8 is arranged on the surface of the N-type drift region 2, a polysilicon gate 9 is arranged on the surface of the gate oxide layer 8, a passivation layer 6 is arranged above the polysilicon gate 9, and source metal 7 is connected with the N+ type source region 5 and the P+ type body contact region 4. The conventional silicon carbide power semiconductor device operates on the principle that when a positive voltage is applied to the polysilicon gate sufficiently large, an inversion channel is generated at the interface between the P-type base region 3 and the gate oxide layer 8, and electrons can be injected from the n+ type source region 5 to the N-type drift region 2 through the channel. The P-type base region 3 and the n+ type source region 5 need to be doped to form, however, the cell size of the silicon carbide device is limited by the doping process and the JFET region width, so that the cell width limit is 4-6um, and the cell density and the forward current capability of the device are affected. In addition, the ion implantation process of the silicon carbide material also causes surface damage of the N-type drift region 2, so that a large number of interface state traps exist on the surface of the N-type drift region 2, and the effective mobility of inversion channel carriers is smaller, and the on-resistance is higher. Meanwhile, the traditional semiconductor device is based on a carrier thermal injection working mechanism, and the subthreshold swing can only reach 60mV/decade at the minimum at normal temperature. There is an urgent need to provide a novel power device with high channel electron mobility and high power density.
Disclosure of Invention
The invention aims at the problems and provides a heterojunction-based high-power-density tunneling semiconductor device and a manufacturing process thereof, wherein the structure forms a heterojunction by using graphene and a silicon carbide substrate on the basis of keeping the breakdown voltage unchanged. When positive pressure is applied to the grid electrode, the fermi level of the graphene moves upwards to enter the conduction band, meanwhile, the electron concentration of the N-type drift region rises to form an accumulation layer, the width of the heterojunction barrier is narrowed, band tunneling effect occurs, and electrons in the valence band of the graphene tunnel through the heterojunction barrier to enter the conduction band of the N-type drift region.
Meanwhile, the cell size of the device is smaller than that of a conventional silicon carbide power device, the number of cells is greatly increased in unit area, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
The invention adopts the following technical scheme: a heterojunction-based high-power-density tunneling semiconductor device and a manufacturing process thereof, wherein the heterojunction-based high-power-density tunneling semiconductor device has an axisymmetric structure,
The device comprises an N+ substrate, wherein drain electrode metal is arranged below the N+ substrate, and an N-drift region is arranged on the N+ substrate; the N-drift region is provided with a pair of graphene source regions arranged at intervals, source metal is arranged on the graphene source regions, a gate dielectric layer which is partially overlapped with the graphene source regions is arranged on the N-drift region, a polysilicon gate is arranged on the gate dielectric layer, a passivation layer is arranged on the polysilicon gate, the polysilicon gate is flush with the gate dielectric layer, the polysilicon gate is arranged at intervals with the source metal, a heterojunction is formed at the contact position of the graphene source regions and the N-drift region, a triple contact surface is formed among the graphene source regions, the N-type region drift regions and the gate dielectric layer, and tunneling effect occurs at the triple contact surface.
Further, two spaced grooves are formed in the upper surface of the N-type drift region, a graphene source region is arranged in the grooves, and a P+ type region is arranged in the N-type drift region below the graphene source region.
Further, the graphene source region is arranged on the upper surface of the N-type drift region, and the P+ type region is arranged in the N-type drift region below the graphene source region.
Further, the graphene source region is arranged on the upper surface of the N-type drift region.
Further, two spaced grooves are formed in the upper surface of the N-type drift region, and the graphene source region is arranged in the grooves.
Further, a P+ type region is arranged in the N-type drift region below the graphene source region, a second P+ type region is arranged in the N-type drift region below the gate dielectric layer, and a certain distance is reserved between the second P+ type region and the graphene source region.
Further, the n+ type substrate and the N-type drift region are not limited by materials, and silicon carbide, gallium oxide, silicon, diamond or other materials capable of forming heterojunction tunneling power semiconductor device substrates and drift regions can be used, and the doping concentrations of the n+ type substrate and the N-type drift region are not limited.
Further, the graphene source region is not limited by the material, and graphene, molybdenum disulfide, polysilicon, metal or other materials capable of forming heterojunction tunneling power semiconductor device source regions can be used.
Further, the thickness of the gate dielectric layer is not limited, and the gate dielectric layer is not limited by materials, and silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or other materials capable of forming a heterojunction tunneling power semiconductor device gate dielectric layer can be used.
A manufacturing method of a heterojunction-based high-power-density tunneling semiconductor device comprises the following steps:
step 1: attaching silicon carbide on the surface of the N+ type substrate to form an N-type drift region;
Step 2: forming a groove on the surface of the N-type drift region by using an etching process;
step 3: forming a P+ type shielding layer at the bottom of the groove by using a doping process;
step 4: forming a layer of graphene source region on the bottom of the groove;
step 5: forming a gate dielectric layer on the upper surface of the N-type drift region by using a deposition process;
Step 6: depositing polysilicon on the upper surface of the gate dielectric layer by using a deposition process and forming a polysilicon gate;
step 7: forming an isolation passivation layer above the polysilicon gate by a deposition process;
Step 8: and finally, forming source electrode metal on the upper surface of the graphene source region, and manufacturing drain electrode metal on the other surface of the N+ type substrate.
The source electrode of the device is made of graphene material, and voltage is applied to the gate electrode, so that the device has lower subthreshold swing and higher on-state current characteristic.
Principle of: when a sufficiently large positive voltage is applied to the gate electrode, a large amount of electrons can be accumulated at the interface of the N-type drift region and the gate oxide layer, the resistance of the channel region and the energy band of the N-type drift region below the gate electrode can be reduced, the width of a heterojunction barrier is narrowed due to the reduction of the energy band of the N-type drift region, and a band tunneling mechanism that valence band electrons of a graphene source region pass through a forbidden band to reach a conduction band of the N-type drift region is easier to occur, so that the power semiconductor device generates I-V characteristics shown in fig. 3 in an on state, wherein a current path is 11, and depletion layer distribution is shown by a dotted line 10.
When a negative voltage is applied to the gate, electrons in the channel region are repelled, the electron concentration decreases, and the energy band of the N-drift region under the gate is increased. And the conduction band and valence band gaps of the graphene are opened, the heterojunction barrier width is increased, the occurrence of tunneling effect and bipolar effect is greatly restrained, and the power semiconductor device has smaller leakage current in the off state. At this time, the device is in a reverse withstand voltage state, and a homogeneous PN junction formed by the P+ type region and the N-type drift region is in a reverse withstand voltage state as shown in FIG. 4, wherein the depletion layer distribution is shown by a broken line 10.
Compared with the prior art, the invention has the following advantages:
(1) The source electrode of the device adopts the graphene material, the conduction band and the valence band of the graphene material are symmetrical, and the conduction band and the valence band are intersected only at the vertex of the Brillouin zone, namely at one point on the Fermi surface, so that the device has obvious controllable electronic band gap. According to the characteristic of the symmetry of the graphene energy bands, the energy band symmetry can be destroyed by doping or applying an external electric field, so that the band gap is opened, and the work function of the graphene is adjustable. Thus, graphene has semiconductor band characteristics. When the grid electrode is subjected to zero voltage, the device is in a closed state, the graphene intrinsic carrier concentration is low, and the high-resistance state is presented. When positive pressure is applied to the grid electrode, the fermi level of the graphene moves upwards, enters into a conduction band, the height of a heterojunction barrier is reduced, the width of the heterojunction barrier is narrowed, band tunneling effect occurs, and forward tunneling current is generated.
(2) The graphene material adopted by the source electrode of the device is low in doping concentration and almost in an intrinsic state, and the graphene material is in a high-resistance state when the intrinsic carrier concentration of the graphene is low, and the leakage current is small when the device is in reverse withstand voltage.
(3) The graphene material adopted by the source electrode of the device has the thermal conductivity which is six times that of silicon carbide and the thickness is extremely thin, so that the device has better heat dissipation characteristic compared with the traditional power device.
(4) When a large positive voltage is applied to the grid electrode, a large amount of electrons can be accumulated at the interface between the N-type drift region and the grid oxide layer, so that the resistance of a channel region is reduced, and the channel resistance is extremely low because the mobility of graphene channel carriers is 20 0000cm 2/(V.s) in an ideal state, so that the device has excellent forward I-V characteristics in an on state.
(5) In the follow current state, the heterojunction formed by the graphene material and the N-drift region is adopted to replace a PN homojunction formed by doping an ion implantation doping process of a conventional silicon carbide power semiconductor device, and the heterojunction diode with the adjustable heterojunction barrier can be obtained by changing the graphene work function through doping and other means due to lower heterojunction barrier and larger follow current, so that the advantage of the device in the follow current state is further exerted.
(6) According to the device, a source electrode is made of a graphene material, a heterojunction is formed by the graphene material and an N-drift region, a tunneling effect occurs under the control of gate voltage, and a channel is a triple contact surface of the graphene source electrode, an N-type drift region contact surface and a gate insulating layer. In the conventional silicon carbide MOS, due to the limitation of the characteristics of silicon carbide materials, a P-type base region and an N+ type source electrode can be formed only through an ion implantation doping process, and then an inversion layer conductive channel is formed through gate control. But the ion implantation doping process damages the surface of the N-type drift region, resulting in low electron mobility. Compared with a conventional power semiconductor device, the channel of the device is formed by graphene and the high-concentration electron accumulation region, an electron inversion layer conduction channel is not required to be formed through an ion implantation process, the surface of an N-drift region of the channel region is not damaged, the manufacturing process is greatly simplified, the device cost is reduced, and the cell number is greatly increased in a unit area.
(7) The graphene source region, the N-type drift region and the gate dielectric layer are in contact to form a triple contact surface, and a tunneling effect occurs at the triple contact surface, so that the channel density is high and the current capability is high.
(8) The device disclosed by the invention is compatible with the traditional device process, and the graphene can be manufactured in a large area, so that the process difficulty is low.
(9) The device is provided with a P+ type region below a graphene source region, wherein the P+ type region and an N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. When the device is reversely biased and voltage-resistant, no electric field peak value of the P+ type region is at a heterojunction boundary formed by the graphene source region and the N-type drift region, reverse leakage current is large, and breakdown voltage of the device is small. When the P+ type region exists, the electric field peak value is at the PN junction boundary formed by the P+ type region and the N-type drift region, so that the avalanche capacity of the device is improved, the reverse bias leakage current is reduced, and the breakdown voltage of the device is increased.
Drawings
FIG. 1 is a front view of a conventional silicon carbide power semiconductor device structure;
Fig. 2 is a front view of a semiconductor device cell according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a forward current path according to a first embodiment of the present invention;
fig. 4 is a diagram showing a reverse state depletion layer distribution according to the first embodiment of the present invention;
fig. 5 is a front view of a semiconductor device cell according to a second embodiment of the present invention;
fig. 6 is a front view of a semiconductor device cell according to a third embodiment of the present invention;
Fig. 7 is a front view of a semiconductor device cell according to a fourth embodiment of the present invention;
fig. 8 is a front view of a semiconductor device cell according to a fifth embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
Example 1:
Referring to fig. 2, a heterojunction-based high-power-density tunneling semiconductor device is an axisymmetric structure, and includes: the N+ type substrate 1, the lower surface at N+ type substrate 1 is connected with drain metal 8, be equipped with N-type drift region 2 at the upper surface of N+ type substrate 1, set up a pair of P+ type district 9 in the N-type drift region 2, set up a pair of graphite alkene source region 3 at N-type drift region 2 upper surface, the upper surface symmetry of graphite alkene source region 3 sets up source metal 4, N-type drift region 2 and graphite alkene source region 3 upper surface is equipped with gate dielectric layer 5, gate dielectric layer 5 upper surface is equipped with polycrystalline silicon gate 6, polycrystalline silicon gate 6 upper surface is equipped with passivation layer 7. The upper surface of the N-type drift region 2 is grooved to divide the N-type drift region 2 into two parts, namely an N-type drift region 2.1 and an N-type drift region 2.2, a pair of P+ type regions 9 are arranged in the groove bottom, namely the upper surface of the N-type drift region 2.1, a pair of graphene source regions 3 are symmetrically arranged in the groove on the upper surface of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 which is partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2.2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and source metal 4, and a heterojunction is formed at the contact surface of the graphene source regions 3 and the N-type drift region 2.
The invention is prepared by the following method:
step 1: taking an N+ type substrate 1, and attaching silicon carbide on one surface of the N+ type substrate 1 to form an N-type drift region 2;
step 2: forming a groove on the surface of the N-type drift region 2 by using an etching process;
Step 3: forming a P+ type shielding layer 9 at the bottom of the groove by using a doping process;
Step 4: forming a layer of graphene source region 3 on the bottom of the groove;
step 5: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 6: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
Step 7: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is fabricated on the other surface of the n+ type substrate 1.
The P+ type region and the N-type drift region of the structure form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. On the basis of keeping the breakdown voltage unchanged, the area of the heterojunction is increased through a grooving process. When positive pressure is applied to the grid electrode, the fermi level of the graphene moves upwards to enter a conduction band, meanwhile, the electron concentration of the N-type drift region rises to form an accumulation layer, the heterojunction barrier width is narrowed, a band-band tunneling effect occurs at the triple contact surface of the graphene source region, the N-type drift region and the grid dielectric layer, and electrons of a graphene valence band tunnel through the heterojunction barrier to enter the conduction band of the N-type drift region to form current. As shown in fig. 3, the current path 11 is not affected by the depletion layer 10 under the graphene. When the device is reversely biased and voltage-resistant, no electric field peak value in the P+ type region is positioned at a heterojunction boundary formed by the graphene source region and the N-type drift region, reverse leakage current is large, and breakdown voltage of the device is small. Referring to fig. 4, when there is a p+ type region, the depletion layer 10 completely covers the graphene source region 3, shields the electric field of the heterojunction interface, and the peak value of the electric field is transferred to the PN junction boundary formed by the p+ type region and the N-type drift region, thereby reducing reverse bias leakage current, improving avalanche capability of the device, and increasing breakdown voltage of the device. Meanwhile, as the doping process of the device is simple and the doping area is small, the cell size of the device is not limited by the doping process and the JFET region, so that the cell size of the device is far smaller than that of a conventional silicon carbide power device, the cell number is greatly increased in a unit area, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 2:
Referring to fig. 5, a heterojunction-based high-power-density tunneling semiconductor device is an axisymmetric structure, and includes: the N+ type substrate 1, the lower surface at N+ type substrate 1 is connected with drain metal 8, be equipped with N type drift region 2 at the upper surface of N+ type substrate 1, set up a pair of P+ type district 9 in the upper surface of N type drift region 2, the upper surface symmetry at N type drift region 2 sets up a pair of graphite alkene source region 3, the upper surface symmetry of graphite alkene source region 3 sets up source metal 4, N type drift region 2 and graphite alkene source region 3 upper surface are equipped with gate dielectric layer 5, gate dielectric layer 5 upper surface is equipped with polycrystalline silicon gate 6, polycrystalline silicon gate 6 top is equipped with passivation layer 7. A pair of P+ type regions 9 are arranged in the upper surface of the N-type drift region 2, a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate medium 5 which is partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate medium layer 5, a certain distance is reserved between the polysilicon gate 6 and source metal 4, and a heterojunction is formed at the contact surface of the graphene source regions 3 and the N-type drift region 2.
The invention is prepared by the following method:
Step 1: taking an N+ type substrate 1, and attaching silicon carbide on the other surface of the N+ type substrate 1 to form an N-type drift region 2;
step 2: forming a p+ type shielding layer 9 in the N-type drift region 2 by using a doping process;
step 3: forming a layer of graphene source region 3 on the N-type drift region 2;
step 4: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 5: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
Step 6: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is fabricated on the other surface of the n+ type substrate 1.
According to the structure, on the basis of keeping breakdown voltage unchanged, a heterojunction is formed by using graphene and a silicon carbide substrate, when positive pressure is applied to a grid electrode, the fermi level of the graphene moves upwards and enters a conduction band, meanwhile, the electron concentration of an N-type drift region rises to form an accumulation layer, the width of a heterojunction barrier is narrowed, tunneling effect occurs at triple contact points of a graphene source region, an N-type drift region and a grid dielectric layer, and electrons of a graphene valence band tunnel through the heterojunction barrier and enter the conduction band of the N-type drift region. The P+ type region and the N-type drift region form PN junctions, the graphene source region and the N-type drift region form heterojunctions, when the device is reversely biased and voltage-resistant, no electric field peak value of the P+ type region is positioned at the heterojunctions boundary formed by the graphene source region and the N-type drift region, the reverse leakage current is large, and the breakdown voltage of the device is small. When the P+ type region exists, the electric field peak value is transferred to the PN junction boundary formed by the P+ type region and the N-type drift region, so that the avalanche capacity of the device is improved, the reverse bias leakage current is reduced, and the breakdown voltage of the device is increased. Meanwhile, the cell size of the device is smaller than that of a conventional silicon carbide power device, the number of cells is greatly increased in a unit area, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 3:
Referring to fig. 6, a heterojunction-based high-power-density tunneling semiconductor device is an axisymmetric structure, and includes: the N+ type substrate 1, be connected with drain electrode metal 8 at the lower surface of N+ type substrate 1, upper surface at N+ type substrate 1 is equipped with N type drift region 2, upper surface symmetry at N type drift region 2 sets up a pair of graphite alkene source region 3, the upper surface symmetry of graphite alkene source region 3 sets up source metal 4, N type drift region 2 and graphite alkene source region 3 upper surface are equipped with gate dielectric layer 5, gate dielectric layer 5 upper surface is equipped with polycrystalline silicon gate 6, polycrystalline silicon gate 6 top is equipped with passivation layer 7. A pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 which is partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and source metal 4, and a heterojunction is formed at the contact surface of the graphene source regions 3 and part of the N-type drift region 2.
The invention is prepared by the following method:
Step 1: taking an N+ type substrate 1, and attaching silicon carbide on the other surface of the N+ type substrate 1 to form an N-type drift region 2;
step 2: forming a layer of graphene source region 3 on the N-type drift region 2;
step 3: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 4: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
step 5: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is fabricated on the other surface of the n+ type substrate 1.
And forming a heterojunction by using graphene and a silicon carbide substrate, wherein when positive pressure is applied to a grid electrode, the fermi level of the graphene moves upwards to enter a conduction band, meanwhile, the electron concentration of an N-type drift region rises to form an accumulation layer, the width of a heterojunction barrier is narrowed, a band tunneling effect occurs at a triple contact point of a graphene source region, an N-type drift region and a grid dielectric layer, and electrons of a graphene valence band tunnel through the heterojunction barrier to enter the conduction band of the N-type drift region.
Meanwhile, the three-port power device can be formed without an implantation doping process, and the cell size of the device is not limited by the doping process and the JFET region, so that the cell of the device is smaller than that of a conventional silicon carbide power device, the cell density of the device is greatly improved, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 4:
Referring to fig. 7, a heterojunction-based high-power-density tunneling semiconductor device is an axisymmetric structure, and includes: the N+ type substrate 1, be connected with drain electrode metal 8 at the lower surface of N+ type substrate 1, upper surface at N+ type substrate 1 is equipped with N type drift region 2, upper surface symmetry at N type drift region 2 sets up a pair of graphite alkene source region 3, the upper surface symmetry of graphite alkene source region 3 sets up source metal 4, N type drift region 2 and graphite alkene source region 3 upper surface are equipped with gate dielectric layer 5, gate dielectric layer 5 upper surface is equipped with polycrystalline silicon gate 6, polycrystalline silicon gate 6 top is equipped with passivation layer 7. The upper surface of the N-type drift region 2 is grooved, a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 which partially overlaps with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and source metal 4, and a heterojunction in a power device is formed at the contact surface of the graphene source regions 3 and part of the N-type drift region 2.
The invention is prepared by the following method:
Step 1: taking an N+ type substrate 1, and attaching silicon carbide on the other surface of the N+ type substrate 1 to form an N-type drift region 2;
step 2: forming a groove on the surface of the N-type drift region 2 by using an etching process;
step 3: forming a layer of graphene source region 3 on the bottom of the groove;
step 4: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 5: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
Step 6: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is fabricated on the other surface of the n+ type substrate 1.
The heterojunction is formed by using graphene and a silicon carbide substrate, the area of the heterojunction is increased through a grooving process, the fermi level of the graphene moves to enter a conduction band when positive pressure is applied to a grid electrode, meanwhile, the electron concentration of an N-type drift region rises to form an accumulation layer, the width of a heterojunction barrier is narrowed, band-band tunneling effect occurs at triple contact surfaces of a graphene source region, an N-type region drift region and a grid dielectric layer, and electrons of a graphene valence band enter the conduction band of the N-type drift region through the heterojunction barrier. The structure has larger area for generating band-to-band tunneling effect and larger current density.
Meanwhile, the three-port power device can be formed without an implantation doping process, and the cell size of the device is not limited by the doping process and the JFET region, so that the cell of the device is smaller than that of a conventional silicon carbide power device, the cell density of the device is greatly improved, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 5:
Referring to fig. 8, a heterojunction-based high-power-density tunneling semiconductor device and a manufacturing process thereof, the heterojunction-based high-power-density tunneling semiconductor device having an axisymmetric structure, comprising: the N+ type silicon carbide substrate 1, the drain metal 8 is connected to the lower surface of the N+ type silicon carbide substrate 1, the N-type drift region 2 is arranged on the upper surface of the N+ type substrate 1, a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, and the source metal 4 is symmetrically arranged on the upper surface of the graphene source regions 3. The upper surfaces of the N-type drift region 2 and the graphene source region 3 are provided with a gate dielectric layer 5, the upper surface of the gate dielectric layer 5 is provided with a polysilicon gate 6, a passivation layer 7 is arranged above the polysilicon gate 6, the N-type drift region 2 is provided with a pair of P+ type regions 9, and a P+ type region 10 is arranged in the N-type drift region 2 below the gate dielectric layer 5. The upper surface of the N-type drift region 2 is grooved, a pair of P+ type regions 9 are arranged at the bottom of the groove, a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 which is partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and source metal 4, a heterojunction is formed at the contact surface of the graphene source region 3 and the N-type drift region 2, the graphene source regions 3, the N-type drift region 2 and the gate dielectric layer 5 are contacted, and a triple contact point is formed, and is wrapped by a depletion layer of the P+ type region 10 and the N-type drift region 2. The p+ type region 10 and the graphene source region 3 have a certain distance, the distance is smaller than the width of the depletion layer of the p+ type region 10 and the depletion layer of the N-drift region 2 when negative pressure or zero pressure is applied to the polysilicon gate 6, the depletion layer wraps the triple contact surface, and meanwhile, the distance is larger than the width of the depletion layer of the p+ type region 9 and the depletion layer of the N-drift region 2 when positive pressure is applied to the polysilicon gate 6, and the depletion layer does not wrap the triple contact point.
The invention is prepared by the following method:
Step 1: taking an N+ type substrate 1, and attaching silicon carbide on the other surface of the N+ type substrate 1 to form an N-type drift region 2;
step 2: forming a groove on the surface of the N-type drift region 2 by using an etching process;
Step 3: forming a P+ type shielding layer 9 at the bottom of the groove by using a doping process, and doping a III-group element on the upper surface of the N-type drift region 2 to form a P+ type shielding layer 10;
Step 4: forming a layer of graphene source region 3 on the bottom of the groove;
step 5: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 6: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
Step 7: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is fabricated on the other surface of the n+ type substrate 1.
And forming a heterojunction by using graphene and a silicon carbide substrate, applying positive pressure to enable the fermi energy level of the graphene to move upwards through a grid electrode, and enabling the graphene to enter a conduction band, and meanwhile, increasing the electron concentration of an N-type drift region to form an accumulation layer. The electron accumulation region narrows the depletion layer between the P+ type region and the N-drift region below the gate dielectric layer, and triple contact points are not covered. At the moment, sufficient positive pressure is applied to the grid electrode, a band-to-band tunneling effect is generated at the triple contact surfaces of the graphene source region, the N-type region drift region and the grid dielectric layer, and electrons in a graphene valence band tunnel through the heterojunction barrier and enter the conduction band of the N-type drift region. The triple contact is covered by a depletion layer between the N-drift region and the P+ region under the gate dielectric layer when negative or zero voltage is applied to the gate. When the device is reversely biased, the P+ region 9 enables an electric field peak value to be transferred from a heterojunction boundary to a PN junction boundary, so that the avalanche capacity of the device is improved, reverse bias leakage current is reduced, breakdown voltage is increased, the P+ region 10 shields the electric field of the gate dielectric layer 5, and the gate oxide reliability of the device is improved.
The structure improves the reliability of the gate oxide of the device, reduces the gate-drain capacitance and improves the switching characteristic under the condition of not sacrificing the forward conduction capability of the high-power-density tunneling power semiconductor device based on the heterojunction.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. The high-power-density tunneling semiconductor device based on the heterojunction is of an axisymmetric structure and comprises an N+ type substrate (1), drain metal (8) is arranged below the N+ type substrate, and an N-type drift region (2) is arranged on the N+ type substrate; the method is characterized in that a pair of graphene source regions (3) are arranged above an N-type drift region (2) at intervals, source metal (4) is arranged on the graphene source regions (3), a gate dielectric layer (5) which is partially overlapped with the graphene source regions (3) is arranged on the N-type drift region (2), a polysilicon gate (6) is arranged on the gate dielectric layer (5), a passivation layer (7) is arranged on the polysilicon gate (6), the polysilicon gate (6) and the source metal (4) are arranged at intervals, a heterojunction is formed at the contact position of the graphene source regions (3) and the N-type drift region (2), a triple contact surface is formed among the graphene source regions (3), the N-type drift region (2) and the gate dielectric layer (5), and a tunneling effect occurs at the triple contact surface; the N-type drift region (2) below the graphene source region (3) is internally provided with a P+ type region (9), the edge of one side of the graphene source region (3) close to the gate dielectric layer (5) protrudes out of the edge of one side of the P+ type region (9) below the graphene source region close to the gate dielectric layer (5), the protruding distance is greater than 0, the P+ type region (9) and the N-type drift region (2) form a PN junction, and the graphene source region (3) and the N-type drift region (2) form a heterojunction.
2. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, wherein two spaced grooves are formed in the upper surface of the N-type drift region (2), the graphene source region (3) is disposed in the grooves, and the p+ type region (9) is disposed in the N-type drift region (2) below the graphene source region (3).
3. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is disposed on the upper surface of the N-type drift region (2), and the p+ type region (9) is disposed in the N-type drift region (2) below the graphene source region (3).
4. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, characterized in that the graphene source region (3) is disposed on the upper surface of the N-type drift region (2).
5. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, wherein two spaced grooves are formed on the upper surface of the N-type drift region (2), and the graphene source region (3) is disposed in the grooves.
6. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, wherein the p+ type region (9) is disposed in the N-type drift region (2) below the graphene source region (3), a second p+ type region (10) is disposed in the N-type drift region (2) below the gate dielectric layer (5), and a certain distance is provided between the second p+ type region (10) and the graphene source region (3).
7. A heterojunction-based high power density tunneling semiconductor device according to claim 1, characterized in that the n+ -type substrate (1) and N-type drift region (2) use silicon carbide, gallium oxide, silicon or diamond.
8. A heterojunction-based high-power-density tunneling semiconductor device according to claim 1, characterized in that the graphene source region (3) uses graphene material.
9. A heterojunction-based high power density tunneling semiconductor device according to claim 1, characterized in that the gate dielectric layer (5) uses silicon oxide, aluminum oxide, hafnium oxide or zirconium oxide.
10. A method for fabricating a heterojunction-based high-power density tunneling semiconductor device, comprising the steps of:
step 1: attaching silicon carbide on the surface of an N+ type substrate (1) to form an N-type drift region (2);
Step 2: forming a groove on the surface of the N-type drift region (2) by using an etching process;
step 3: forming a P+ type shielding layer (9) at the bottom of the groove by using a doping process;
Step 4: forming a layer of graphene source region (3) on the bottom of the groove;
step 5: forming a gate dielectric layer (5) on the upper surface of the N-type drift region (2) by using a deposition process;
Step 6: depositing polysilicon on the upper surface of the gate dielectric layer (5) by using a deposition process and forming a polysilicon gate (6);
Step 7: forming an isolation passivation layer (7) above the polysilicon gate (6) by a deposition process;
Step 8: finally, forming source metal (4) on the upper surface of the graphene source region (3), and manufacturing drain metal (8) on the other surface of the N+ type substrate (1);
Heterojunction is formed at the contact position of the graphene source region (3) and the N-type drift region (2), a triple contact surface is formed among the graphene source region (3), the N-type drift region (2) and the gate dielectric layer (5), and tunneling effect occurs at the triple contact surface.
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