JPH08264772A - Field-effect type semiconductor element - Google Patents

Field-effect type semiconductor element

Info

Publication number
JPH08264772A
JPH08264772A JP7064545A JP6454595A JPH08264772A JP H08264772 A JPH08264772 A JP H08264772A JP 7064545 A JP7064545 A JP 7064545A JP 6454595 A JP6454595 A JP 6454595A JP H08264772 A JPH08264772 A JP H08264772A
Authority
JP
Japan
Prior art keywords
layer
type region
conductivity type
formed
low concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7064545A
Other languages
Japanese (ja)
Inventor
Fumiaki Kawai
Tomoyoshi Kushida
文彰 川井
知義 櫛田
Original Assignee
Toyota Motor Corp
トヨタ自動車株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp, トヨタ自動車株式会社 filed Critical Toyota Motor Corp
Priority to JP7064545A priority Critical patent/JPH08264772A/en
Publication of JPH08264772A publication Critical patent/JPH08264772A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41741Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

PURPOSE: To make decrease of threshold voltage compatible with decrease of on-resistance, and improve punchthrough breakdown voltage, in an MOSFET.
CONSTITUTION: A gate oxide film 45 is formed surrounding a gate electrode 46. A diffusion layer 49 as a low concentration layer is formed on the side part of the gate electrode 46. Diffusion layers 53a, 53b-are formed on the side part of the diffusion layer 49, sufficiently deeper in the drain direction than the gate electrode 46 and the diffusion layer 49. Since the distance between the lower end portions of P+ body layers (diffusion layers (53a, 53b) is short, depletion layers 56 between the P+ body layers are easy to be linked together.
COPYRIGHT: (C)1996,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】この発明はMOSFET等の電界効果型半導体素子の構造に関するものである。 BACKGROUND OF THE INVENTION This invention relates to structure of a field effect semiconductor device of the MOSFET or the like.

【0002】 [0002]

【従来の技術】電界効果型半導体の構造として、従来のパワーMOSFETトランジスタ(以下、パワーMOS The structure of the Related Art The field effect type semiconductor, the conventional power MOSFET transistors (hereinafter, a power MOS
という)の構造を図3に示す。 Figure 3 shows the structure of) called. 1はN +基板、2はN - 1 N + substrate, 2 N -
エピタキシャル層、3はPボディ層、4はP +ボディ層、5はN +ソース層、6はゲート酸化膜、7はゲート・多結晶シリコン電極、8は層間絶縁膜、9はソース・ Epitaxial layer, 3 P body layer, 4 P + body layer, 5 is N + source layer, 6 denotes a gate oxide film, the gate polysilicon electrode 7, 8 interlayer insulating film, 9 Source
アルミニウム電極、10はドレイン電極、11は空乏層である。 Aluminum electrode, 10 drain electrode, 11 is a depletion layer.

【0003】このパワーMOSは、4V程度のゲート電圧の印加で十分駆動できるように低いしきい値電圧(1 [0003] The power MOS is low threshold voltage can be sufficiently driven by applying approximately 4V of the gate voltage (1
〜2V)が要求されている。 ~2V) is required. このため、Pボディ層3の濃度は10 17 cm -3程度の低濃度とする必要がある。 Therefore, the concentration of the P body layer 3 is required to be low concentration of about 10 17 cm -3. 一方、Pボディ層3のパンチスルーを防止し、耐圧60V On the other hand, to prevent a punch-through of the P body layer 3, the withstand voltage 60V
程度を実現する必要から、Pボディ層3の深さを2〜3 The need to achieve a degree, 2-3 the depth of the P body layer 3
μm程度としている。 It is set to μm about.

【0004】次に、トレンチゲート構造を有するMOS [0004] Next, MOS having a trench gate structure
FET(UMOS)の従来の構成を図7に示す。 The conventional configuration of the FET (UMOS) shown in FIG. 15はN +基板、16はN -エピタキシャル層、17はPボディ層18はゲート酸化膜、19はゲート酸化膜18にて囲まれたポリシリコンからなるトレンチゲート、20はN +ソース層、21はアルミニウムからなるソース電極、22は空乏層、25はドレイン電極である。 15 N + substrate, 16 N - epitaxial layer 17 is P body layer 18 is a gate oxide film, the trench gate 19 made of polysilicon surrounded by the gate oxide film 18, 20 is N + source layer, 21 the source electrode made of aluminum, 22 depletion, 25 is a drain electrode.

【0005】 [0005]

【発明が解決しようとする課題】ところで、図3(b) The object of the invention is to be Solved by the way, and FIG. 3 (b)
に示すパワーMOSのオン抵抗r ds(on) (全体のオン抵抗:)は、次の式で表される。 On-resistance of the power MOS r ds (on) (total on-resistance :) shown in is expressed by the following equation.

【0006】 r ds(on) =r ch +r acc +r JFET +r bulk +r subなお、図3(b)に示すようにr chはチャネル抵抗成分、r accはアキュミレーション抵抗成分、r JFETはJ [0006] r ds (on) = r ch + r acc + r JFET + r bulk + r sub Incidentally, r ch is the channel resistance component as shown in FIG. 3 (b), r acc Accu Mi Configuration resistance component, r JFET is J
FET抵抗成分、r riftはドリフト抵抗成分、r FET resistance component, r rift drift resistance component, r subは基板抵抗成分である。 sub denotes a substrate resistance component.

【0007】このうち、オン抵抗r ds(on)に占めるJF [0007] Of these, JF occupied in the on-resistance r ds (on)
ET抵抗成分r JFETの割合は、比較的大きい(この抵抗成分のうち、チャネル抵抗成分r chが最も大きい)。 Ratio of ET resistance component r JFET is relatively large (of the resistive component, the largest channel resistance component r ch). 従って、Pボディ層3が深くなると、JFET抵抗成分r Therefore, when the P body layer 3 becomes deep, JFET resistance component r
JFETが大きくなり、このため、オン抵抗が増大してしまう問題がある。 JFET is increased, Therefore, there is a problem that the on-resistance increases.

【0008】又、パワーMOSには、図3(b)に示すように、寄生抵抗r1,r2、寄生トランジスタTr及び寄生ダイオードDiが存在している。 [0008] In addition, the power MOS, as shown in FIG. 3 (b), the parasitic resistance r1, r2, parasitic transistor Tr and the parasitic diode Di is present. ソース・アルミニウム電極9とドレイン電極10との間に電圧を印加し、Pボディ層3とN -エピタキシャル層2とにより形成される寄生ダイオードDiの降伏電圧に達すると、降伏電流が寄生ダイオードDiに流れる。 Applying a voltage between the source and the aluminum electrode 9 and the drain electrode 10, P body layer 3 and the N - reaches the breakdown voltage of the parasitic diode Di formed by the epitaxial layer 2, the breakdown current is the parasitic diode Di It flows. この降伏は、P This surrender, P
ボディ層3とN -エピタキシャル層2との接合部分の境界に拡がる空乏層11において、曲率半径の小さい部分、すなわち、Pボディ層3のコーナ部Aで発生する。 Body layer 3 and the N - in the depletion layer 11 extending to the boundary of the junction between the epitaxial layer 2, a small portion of the radius of curvature, i.e., occurring at the corner portion A of the P body layer 3.

【0009】低濃度のPボディ層3に形成される寄生抵抗r2は、比較的大きいため、降伏電流により、寄生トランジスタTrのベース電流が上昇し、この結果、大量の降伏電流が流れ、ベース電位が0.6Vを越えると、 [0009] parasitic resistance r2 is formed in the low concentration of the P body layer 3 is relatively large, the breakdown current, the parasitic transistor base current of Tr is increased, as a result, a large amount of breakdown current flows, the base potential There is more than 0.6V,
寄生トランジスタTrが導通し、大電流が流れて、パワーMOSが破壊する問題がある。 Parasitic transistor Tr is turned on, a large current flows, the power MOS there is a problem of destruction.

【0010】又、図7に示す従来のトレンチゲート構造を有するMOSFET(UMOS)は、次のような問題点があった。 [0010] Also, MOSFET (UMOS) having a conventional trench gate structure shown in FIG. 7, there are the following problems. すなわち、後述の理由からトレンチゲート19がPボディ層17より深く形成されている。 That is, the trench gate 19 is deeper than the P-body layer 17 for the reasons described below. この結果、トレンチゲート19の下端部に電界集中が生じるため、耐圧が低下する。 As a result, the electric field concentration occurs at the lower end portion of the trench gate 19, the breakdown voltage is lowered. この問題を解消するために、トレンチゲート19の下端部のコーナの曲率半径を大きくする丸め行程が必要となる。 To solve this problem, the rounding process is necessary to increase the curvature radius of the corner of the lower end of the trench gate 19. しかし、トレンチは本来エッチングの異方性を利用して形成しているため、コーナの曲率半径を大きくすることは難しい。 However, since the trench is formed using an anisotropic originally etching, it is difficult to increase the curvature radius of the corner.

【0011】又、Pボディ層17は、低いしきい値電圧を実現するために、低濃度である必要がある。 [0011] Further, P body layer 17, in order to achieve a low threshold voltage, it is necessary that at low concentrations. 従って、 Therefore,
高耐圧を実現するためには、Pボディ層17のパンチスルーを防止する必要から、Pボディ層7を深くしなければならなかった。 To achieve a high breakdown voltage, the need to prevent the punch-through the P body layer 17, had to deep P body layer 7. この結果、低しきい値電圧と高耐圧性を両立させるためにはトレンチゲート19を深くする必要があった。 As a result, in order to achieve both low threshold voltage and a high pressure resistance it was necessary to deepen the trench gate 19.

【0012】この発明の目的は上記従来技術の問題点を解消するためになされたものであって、しきい値電圧の低下と、オン抵抗の低下を両立させ、さらにパンチスルー耐圧の向上を図ることができるを提供することにある。 An object of this invention was made in order to solve the problems of the prior art, the reduction in the threshold voltage, is both a reduction in on-resistance, further improve the punch-through breakdown voltage it is to provide a can.

【0013】 [0013]

【課題を解決するための手段】上記問題点を解決するために請求項1の発明は、ドレインとなる第1導電型半導体基体の表面に第2導電型領域と、ソースとなる第1導電型領域を有し、基体表面上のゲート電極への電圧印加によって基体と第1導電型領域に挟まれた第2導電型領域表面でソース・ドレイン電流を制御するようにした電界効果型半導体素子であって、前記第2導電型領域はゲート電極直下に形成された低濃度層と、、該低濃度層に接続して形成され、第1導電型領域から第1導電型半導体基体方向へ延びる高濃度層とを含み、前記高濃度層を前記低濃度層より深さ方向に幅厚に形成したことを特徴とする電界効果型半導体素子をその要旨としている。 The invention of claim 1 to solve the above problems, there is provided a means for solving] includes a second conductive type region in a surface of the first conductivity type semiconductor substrate serving as a drain, a first conductivity type serving as a source It has a region, a field effect type semiconductor device which is adapted to control the source-drain current in the second conductivity type region surface sandwiched substrate a first conductivity type region by applying a voltage to the gate electrode on the substrate surface there are the second conductivity type region is formed by connecting a low concentration layer and ,, low concentration layer formed immediately below the gate electrode, high extending from the first conductivity type region to the first conductivity type semiconductor substrate direction and a doped layer, and its gist the field effect semiconductor device, characterized in that the high concentration layer was formed above the width-thickness in the depth direction than the low concentration layer.

【0014】請求項2の発明は、低濃度層の濃度ピーク位置が、第1導電型領域より深い位置にあることを特徴とする請求項1に記載の電界効果型半導体素子をその要旨としている。 The invention of claim 2 is the concentration peak position of the low concentration layer has a field effect type semiconductor device according to claim 1, characterized in that in deeper than the first conductivity type region located as its gist .

【0015】請求項3の発明は、ドレインとなる第1導電型半導体基体の表面に第2導電型領域と、ソースとなる第1導電型領域を有し、前記基体表面上のトレンチゲートへの電圧印加によって基体と前記第1導電型領域に挟まれた前記第2導電型領域表面でソース・ドレイン電流を制御するようにした電界効果型半導体素子であって、前記第2導電型領域はトレンチゲート直近に形成された低濃度層と、該低濃度層に接続して形成され、第1 [0015] The invention according to claim 3, and a second conductive type region in a surface of the first conductivity type semiconductor substrate serving as a drain, a first conductive type region serving as the source, to the trench gate on the substrate surface a field effect semiconductor device which is adapted to control the source-drain current in the second conductivity type region surface sandwiched substrate and the first conductive region by applying a voltage, the second conductive type region is trench a lightly doped layer formed on the gate recently, formed by connecting the low concentration layer, the first
導電型領域から第1導電型半導体基体方向へ延びる高濃度層とを含み、前記高濃度層を前記低濃度層より深さ方向に幅厚に形成したことを特徴とする電界効果型半導体素子をその要旨としている。 Includes a conductive type region and the high concentration layer extending into the first conductivity type semiconductor substrate direction, the field effect type semiconductor device, characterized in that the high concentration layer was formed above the width-thickness in the depth direction from the low-density layer It has as its gist.

【0016】 [0016]

【作用】請求項1の発明によれば、低濃度層が幅狭くゲート電極直下に形成されているため、しきい値電圧は低く、さらに、オン抵抗も小さい(オン抵抗のうちのrch SUMMARY OF] According to the present invention, since the low concentration layer is formed immediately below the width narrow gate electrode, the threshold voltage is low, furthermore, rch of the on-resistance is small (on resistance
(チャネル抵抗)とr JFETとが小さくなる。 (Channel resistance) and r JFET is reduced. )。 ). さらに、高濃度層が深く形成されているため、ドレイン・ソース間の逆バイアス時にも高濃度層からドレイン方向に深く空乏層が形成されるため、空乏層の電界Eの強度が全体に弱まり、すなわち、第1導電型領域側への低濃度層内の空乏層が広がりにくく抑えられる。 Furthermore, since the high concentration layer is formed deeper, because even when a reverse bias between the drain and source deep depletion drain direction from the high concentration layer is formed, the strength of the depletion layer of the electric field E is weakened throughout, that is, the depletion layer of the low concentration layer of the first conductivity type region side is suppressed hardly spread. この結果、パンチスルー防止耐圧は維持される。 As a result, punch-through prevention breakdown voltage is maintained.

【0017】請求項2の発明によれば、電界効果型半導体素子のしきい値を決定する低濃度層の表面濃度よりも第1導電領域直下の低濃度層の濃度が濃くなる。 According to the invention of claim 2, the concentration of the low concentration layer immediately below the first conductive region than the surface concentration of the low concentration layer which determines the threshold of the field effect semiconductor device becomes darker. このため、より浅い低濃度層で、パンチスルーが防止でき、オン抵抗が低減される。 Therefore, a more shallow low concentration layer, the punch-through is prevented, on-resistance is reduced. 又、寄生抵抗成分を小さくできることから、ベース電位が上昇しにくくなって寄生トランジスタが導通しにくくなり、かつ寄生トランジスタの電流増幅率hFEを小さくできるため、破壊耐量が向上する。 Moreover, because it can reduce a parasitic resistance component, the parasitic transistor does not easily conduct becomes the base potential hardly increases, and since it is possible to reduce the current amplification factor hFE of the parasitic transistor, breakdown resistance is improved.

【0018】請求項3の発明によれば、トレンチが形成される分だけr JFETの抵抗が無くなり、オン抵抗の低下ができる。 According to the invention of claim 3, there is no resistance in an amount corresponding r JFET which trenches are formed, can decrease on-resistance. 又、第2導電型領域から第1導電型領域へは、電界強度が弱められ、かつ空乏層が拡がるのも抑えられるため、従来と異なり空乏層が拡がってパンチスルーが生じるのを抑止するための深いトレンチゲートの製造の必要がなくなり、製造しやすい浅いトレンチゲートでも可能となる。 Also, the first conductivity type region from the second conductivity type region, weakened electric field strength, and since the suppressed depletion layer expands, the conventional unlike for suppressing the punch-through occurs depletion layer spread eliminates the need for deep production of the trench gate, it is possible in the manufacturing easy to shallow trench gate. 又、電界強度も弱くなることから、トレンチゲート端部の丸め工程も不要となる。 Furthermore, since the even field intensity becomes weak, the process of rounding the trench gate edge becomes unnecessary.

【0019】 [0019]

【実施例】以下、請求項1の発明をNチャネルタイプのパワーMOSFETに具体化した実施例を図1に従って説明する。 EXAMPLES Hereinafter, an embodiment of the invention of claim 1 embodying the N-channel type power MOSFET according to FIG. 図1は、本実施例の模式的な1つのセルの断面図である。 Figure 1 is a cross-sectional view of a schematic single cell of this embodiment. なお、図3の従来例と同一構成又は相当する構成については同一符合を付して説明を省略する。 Incidentally, the description thereof is omitted are denoted by the same reference numerals for the conventional example having the same configuration or equivalent arrangement of Figure 3.

【0020】このパワーMOSFETは、複数個のセルからなり、図1に示すように、各セルはドレインとなるN +基板1、N -エピタキシャル層2、Pボディ層3、 [0020] The power MOSFET is composed of a plurality of cells, as shown in FIG. 1, N + substrate 1 each cell to be a drain, N - epitaxial layer 2, P body layer 3,
+ボディ層4、ソースとなるN +ソース層5を有し、 P + body layer 4 has a N + source layer 5 serving as the source,
-エピタキシャル層2に設けたゲート・多結晶シリコン電極7への印加電圧により、ソース・ドレイン電流を制御するものである。 N - the voltage applied to the gate polysilicon electrode 7 provided in the epitaxial layer 2, and controls the source-drain current. この実施例では前記N -エピタキシャル層2が第1導電型半導体基体を構成する。 In this embodiment the N - constituting the epitaxial layer 2 is the first conductivity type semiconductor substrate. Pボディ層3が第2導電型領域の低濃度層を構成し、P +ボディ層4が第2導電型領域の高濃度層を構成する。 P body layer 3 constitute the low concentration layer of the second conductivity type region, P + body layer 4 constitutes a high-concentration layer of the second conductivity type region. 又、N In addition, N
+ソース層5が第1導電領域を構成する。 + Source layer 5 constituting the first conductive region.

【0021】そして、Pボディ層3に対して、十分深いP +ボディ層4が形成されている。 [0021] Then, the P body layer 3, sufficiently deep P + body layer 4 is formed. 又、この実施例では、N +ソース層5、Pボディ層3、N -エピタキシャル層2に含まれる不純物濃度は図2に示すようになっている。 Further, in this embodiment, N + source layer 5, P body layer 3, N - impurity concentration in the epitaxial layer 2 is as shown in FIG. そして、図2において、実線にて示すようにPボディ層3の不純物濃度ピークの位置xp ( P) は、N + Then, in FIG. 2, the position of the impurity concentration peak of the P body layer 3 as shown by the solid line xp (P) is, N +
ソース層5の拡散深さxj ( N + ) よりも深い位置とされている(xp ( P) >xj ( N + ) )。 The diffusion depth xj of the source layer 5 (N +) is a position deeper than the (xp (P)> xj ( N +)). なお、図2は図1のY−Y線におけるこの実施例におけるパワーMO The power in this embodiment the line Y-Y in FIG. 2 FIG. 1 MO
SFETの不純物濃度を示し、縦軸は不純物濃度、横軸はN -エピタキシャル層2の最上面からの深さを表している。 Shows the impurity concentration of the SFET, the vertical axis represents the impurity concentration, and the horizontal axis N - represents the depth from the top surface of the epitaxial layer 2. そして、Cs はPボディ層3の表面不純物濃度、 Then, Cs is the surface impurity concentration of the P body layer 3,
CP はPボディ層3のピーク不純物濃度を示し、上記のことから、CP >Cs となっている。 CP represents the peak impurity concentration of the P body layer 3, from the above, and has a CP> Cs.

【0022】上記のように構成されたパワーMOSFE [0022] The power is configured as described above MOSFE
Tは、P +ボディ層4から拡がる空乏層11が、隣接するセルからの空乏層11とつながることにより、Pボディ層3の周辺及びゲート・シリコン電極7直下のN -エピタキシャル層2をピンチオフする。 T is the depletion layer 11 extending from the P + body layer 4, by connecting with the depletion layer 11 from adjacent cells, N directly under and around the gate silicon electrode 7 of the P body layer 3 - pinching off the epitaxial layer 2 .

【0023】この結果、Pボディ層3からN -エピタキシャル層2接合近傍の電界集中が緩和される。 [0023] As a result, N from P body layer 3 - field concentration of the epitaxial layer 2 bonded vicinity is relaxed. 従って、 Therefore,
この実施例では、従来より浅いPボディ層3に対してパンチスルーを防止でき、さらに、オン抵抗のうちのrch In this embodiment, it is possible to prevent a punch-through with respect to the shallow P body layer 3 conventionally, further, rch of the on-resistance
とr JFETの低減を図り、すなわち、オン抵抗の低減を図ることができる。 And achieving a reduction in r JFET, i.e., it is possible to reduce the on-resistance.

【0024】又、P +ボディ層4及びPボディ層3と、 [0024] Further, a P + body layer 4 and the P body layer 3,
-エピタキシャル層2とにより形成されるPN接合の境界に拡がる空乏層11の曲率半径は、P +ボディ層4 N - radius of curvature of the depletion layer 11 spreading in the boundary of the PN junction formed by the epitaxial layer 2, P + body layer 4
の底部で、最も小さくなる。 In the bottom, the smallest. すなわち、降伏電流は低濃度のPボディ層3ではなく比較的高濃度のP +ボディ層4を通るため、従来と異なり、大きな降伏電流まで、寄生トランジスタが導通せず、破壊耐量が向上する。 That is, the breakdown current for passing through the low-concentration P body layer 3 rather than relatively high concentrations of P + body layer 4, unlike the conventional, to a large breakdown current, the parasitic transistor does not conduct, breakdown resistance is improved.

【0025】さらに、P +ボディ層4が深く形成されているため、ドレイン・ソース間の逆バイアス時にもP + Furthermore, since the P + body layer 4 is formed deeper, even when a reverse bias between the drain and source P +
ボディ層4からドレイン方向に深く空乏層11が形成されることから、空乏層11の電界Eの強度が全体に弱まることになる。 Deeply since the depletion layer 11 is formed in the drain direction from the body layer 4, the intensity of the electric field E of the depletion layer 11 so that the weakened throughout. すなわち、N In other words, N +ソース層5側へのPボディ(低濃度層)3内の空乏層が広がりにくく抑えられる。 Depletion of + P body (low concentration layer) to the source layer 5 side 3 is suppressed hardly spread. この結果、パンチスルーの防止ができる。 As a result, it is the prevention of punch-through.

【0026】次にトレンチゲートを有するMOSFET [0026] The next MOSFET having a trench gate
(UMOS)に具体化した第2実施例を図4に従って説明する。 It is described with reference to FIG. 4 of a second embodiment embodying the (UMOS). なお、前記図7の従来例と異なるところのみを説明し、同従来例に相当する構成については同一符合を付す。 Incidentally, it describes only differs from the conventional example of FIG. 7 are denoted by the same reference numerals for components corresponding to the conventional example.

【0027】図4は本実施例の模式的な1つのセルの断面図である。 [0027] FIG. 4 is a sectional view of a schematic single cell of this embodiment. この実施例では、トレンチゲート19を囲むようにゲート酸化膜18が形成され、ゲート酸化膜1 In this embodiment, the gate oxide film 18 is formed so as to surround the trench gate 19, a gate oxide film 1
8の側部には低濃度層であるPボディ層23が形成されている。 The 8 side of which is formed the P body layer 23 is a low concentration layer. 又、Pボディ層23の側部には前記トレンチゲート19及びPボディ層23よりもドレイン方向へ十分に深く形成されたP +ボディ層24a,24bが設けられている。 Also, P is on the side of the body layer 23 are sufficiently deep-formed P + body layer 24a, 24b is provided to the drain direction than the trench gate 19 and the P-body layer 23. 図7において、N -エピタキシャル層16が請求項3の発明の第1導電型半導体基体を構成し、N + In FIG. 7, N - epitaxial layer 16 constitutes a first conductivity type semiconductor substrate of the invention of claim 3, N +
ソース層20が第1導電型領域を構成し、Pボディ層2 Source layer 20 constitute a first conductive type region, P body layer 2
3が第2導電領域の低濃度層を構成し、P +ボディ層2 3 constitutes a low concentration layer of the second conductive region, P + body layer 2
4a,24bが第2導電領域の高濃度層を構成する。 4a, 24b constitute the high concentration layer of the second conductive region.

【0028】上記の構成により、P +ボディ層24a, [0028] According to the above-described configuration, P + body layer 24a,
24bから拡がる空乏層22によって、Pボディ層23 Depletion layers 22 extending from 24b, P body layer 23
及びトレンチゲート19直下のN -エピタキシャル層1 And N immediately below the trench gate 19 - epitaxial layer 1
6をピンチオフするようになっている。 It is adapted to pinch off the 6. 従って、この構成により、Pボディ・N -エピタキシャル層接合及びトレンチゲート19下端部(特にエッジ部)の最大電界強度を下げ、すなわち、浅いPボディ層23でもパンチスルーを防止できる。 Therefore, this configuration, the P-body · N - lowering the maximum electric field intensity of the epitaxial layer junction and the trench gate 19 the lower end (in particular edge), i.e., can prevent the punch-through even shallow P body layer 23. 従って、浅いトレンチゲート19により高耐圧が実現できる。 Thus, high breakdown voltage can be realized by shallow trench gate 19.

【0029】又、従来のトレンチゲート19下端部エッジでの高電界が緩和されるため、従来では必要であったエッジの丸め工程を省略することができる。 [0029] Also, since a high electric field at the conventional trench gate 19 lower edge is relieved, conventionally it is possible to omit a process of rounding the edge was required. さらに、ドレイン方向へ深く形成されたP +ボディ層24a,24 Furthermore, P + body layer 24a which is formed deeper into the drain direction, 24
bにより、寄生NPNトランジスタのベース抵抗が小さくなるため、従来構造に比較し、高温時でも寄生NPN The b, since the base resistance of the parasitic NPN transistor is reduced, as compared with the conventional structure, a parasitic NPN even at high temperatures
が動作せず、破壊耐量を向上することができる。 There does not operate, it is possible to improve the breakdown resistance. 従来構造では、パワーMOSFETをインダクタンス負荷で使用した場合、パワーMOSFETをオフするときに、短時間ではあるが、高電圧と大電流が同時にパワーMOS In the conventional structure, when using the power MOSFET in the inductive load, when turning off the power MOSFET, but briefly it is a high voltage and high current at the same time the power MOS
FETに加わる。 It applied to the FET. そのため、急激に温度上昇して寄生N Therefore, rapidly increase in temperature parasitic N
PNトランジスタが動作し、寄生NPNトランジスタが熱暴走して破壊する。 PN transistor operates, the parasitic NPN transistor is destroyed by thermal runaway. しかし、この実施例ではそのようなことは生じない。 However, in this embodiment no such thing.

【0030】次に第3実施例を図5、図6、図8及び図9に従って説明する。 [0030] Next, FIG. 5 a third embodiment, FIG. 6 will be described with reference to FIGS. この実施例では、図5に示すように第2導電型領域の高濃度層としての拡散層(P +ボディ層)53a,53bをトレンチの周辺に形成することにより、図4の第2実施例の1セルの寸法をLとしたとき、L/2となるように形成し、図4の第2実施例と同等の性能をより小さな面積で実現している。 In this embodiment, by forming around a diffusion layer as a high concentration layer of the second conductivity type region (P + body layer) 53a, and 53b of the trench as shown in FIG. 5, a second embodiment of FIG. 4 1 when the cell size is L, and is formed such that the L / 2, realizes the second embodiment and the same performance in Figure 4 in a smaller area.

【0031】この実施例におけるパワーMOSFETの製造工程を図8及び図9に従って以下に詳細に説明する。 [0031] described in detail below in accordance with FIGS. 8 and 9 the process of manufacturing the power MOSFET in this embodiment. なお、図5は左右対象とされているため、説明の便宜上、図8及び図9においては、図5における左半分のみを示し、右半分は省略している。 Since Figure 5 is a symmetrical, for convenience of explanation, in FIGS. 8 and 9 show only the left half in FIG. 5, the right half is omitted. 従って、図5において、左半分に相当する構成については同一符合もしくは同一符合にサフィクスを付している。 Thus, in FIG. 5 are denoted by the suffix to the same reference numerals or the same numerals for the configuration corresponding to the left half.

【0032】図8(a)に示すように高濃度N +型シリコン基板41上に第1導電型半導体基体としての低濃度N型シリコン層42をエピタキシャル成長させ、表面に熱酸化法により酸化膜43を形成する。 [0032] The low concentration N-type silicon layer 42 as a high concentration N + first conductivity type semiconductor substrate on the type silicon substrate 41 as shown in FIG. 8 (a) is epitaxially grown, the oxide film by thermal oxidation on the surface 43 to form. その後、フォトリソグラフィ法とエッチング法を用いて酸化膜43を所定の形状にパターニングする。 Thereafter, patterning of the oxide film 43 into a predetermined shape by a photolithography method and an etching method.

【0033】図8(b)に示すようにRIE(リアクティブ イオンエッチング)法により、酸化膜43をエッチングマスクとしてトレンチ(凹溝)44を形成し、熱酸化法により酸化膜45を形成する。 [0033] By RIE (reactive ion etching) as shown in FIG. 8 (b), the oxide film 43 to form a trench (groove) 44 as an etching mask to form an oxide film 45 by thermal oxidation. 次に、図8(c) Next, and FIG. 8 (c)
に示すようにCVD(ケミカルベーパデポジション)法により、リンPを含んだ多結晶シリコン膜46を堆積する。 By CVD (Chemical base Pade position) method as shown in, depositing a polycrystalline silicon film 46 containing phosphorus P. 図8(d)に示すように多結晶シリコン膜46の表面をRIE法によりエッチバックする。 The surface of the polycrystalline silicon film 46 as shown in FIG. 8 (d) is etched back by RIE. この多結晶シリコン膜46がゲート電極(トレンチゲート)となる。 The polycrystalline silicon film 46 becomes the gate electrode (trench gate). 次に図8(e)に示すように酸化膜45の表面に露出した部分をエッチングし、再び酸化する。 Then etching the exposed portions on the surface of the oxide film 45 as shown in FIG. 8 (e), oxidized again. この時、多結晶シリコン膜46も酸化し、酸化膜47を形成する。 At this time, the polycrystalline silicon film 46 is also oxidized to form an oxide film 47. その後、イオン注入法により、ヒ素Asと、ホウ素Bを注入して、熱処理により、拡散層48,49を形成する。 Thereafter, by ion implantation, arsenic As, by implanting boron B, by heat treatment to form a diffusion layer 48, 49. この拡散層48が第1導電型領域としてのN +ソース層となり、拡散層49が第2導電型領域の低濃度層としてのPボディ層となる。 The diffusion layer 48 is the N + source layer of the first conductivity type region, the diffusion layer 49 becomes P body layer as a low concentration layer of the second conductivity type region.

【0034】図8(f)に示すように表面にCVD法により厚い酸化膜50を堆積し、フォトリソグラフィ法とエッチング法を用いて酸化膜50を所定の形状にパターンニングする。 [0034] Figure 8 is deposited a thick oxide film 50 by the CVD method on the surface (f), the patterned oxide film 50 into a predetermined shape by a photolithography method and an etching method. 続いて、図9(a)に示すようにRIE Subsequently, as shown in FIG. 9 (a) RIE
法により酸化膜50をエッチングマスクとしてトレンチ(凹溝)51を形成する。 By law to form a trench (groove) 51 of the oxide film 50 as an etching mask.

【0035】次に、CVD法により、ホウ素Bを含んだ多結晶シリコン膜52a(52b)を堆積し、熱処理により多結晶シリコン膜52内のホウ素Bを拡散させ、拡散層53a(53b)を形成する(図9(b)参照)。 Next, by CVD, is deposited containing boron B polycrystalline silicon film 52a (52 b), boron B polycrystalline silicon film 52 is diffused by heat treatment, forming a diffusion layer 53a (53b) (refer to FIG. 9 (b)).
この拡散層53a(53b)がP +ボディ層となる。 The diffusion layer 53a (53b) is P + body layer. その後、多結晶シリコン膜52a(52b)をRIE法により酸化膜とシリコンの界面までエッチバックする。 Thereafter, etching back the polycrystalline silicon film 52a (52 b) to the interface of the oxide film and the silicon by RIE. 前記多結晶シリコン膜52a(52b)が充填層を構成している。 The polycrystalline silicon film 52a (52 b) constitute a packed bed.

【0036】次にフォトリソグラフィ法とエッチング法を用いて酸化膜50,47の開口部をより大きくする。 The next larger opening of the oxide film 50,47 by a photolithography method and an etching method.
その後、アルミニウム等の金属をスパッタ法により、堆積し、ソース電極54を形成する。 Thereafter, a metal such as aluminum by sputtering, is deposited to form the source electrode 54. さらに、シリコン基板41の裏面に金属を蒸着し、ドレイン電極55を形成する。 Furthermore, metal is deposited on the back surface of the silicon substrate 41, a drain electrode 55.

【0037】さて、図6(a)に示すように、第2実施例の構造では5L×5Lの面積においてはゲートの総延長は5L×10=50Lとなる。 [0037] Now, as shown in FIG. 6 (a), in the structure of the second embodiment the total length of the gate in the area of ​​5L × 5L becomes 5L × 10 = 50L. それに対して、この実施例では同じ5L×5Lの面積においては、ゲートの総延長は5L×20=100Lとなる。 In contrast, in the area of ​​the same 5L × 5L In this embodiment, the total length of the gate becomes 5L × 20 = 100L. 従って、この実施例では、第2の実施例に比較して同一面積においては、 Thus, in this embodiment, in the same area compared with the second embodiment,
ゲートの総延長が2倍、すなわち、オン抵抗が半分となる。 Twice the total length of the gate, i.e., the on-resistance is half.

【0038】なお、上記の実施例ではセルサイズが第2 It should be noted, the cell size in the above embodiment the second
実施例の1/2の場合について説明したが、セルサイズの縮小率は、P +ボディ層の深さによって一般的に異なる。 Has been described for the case of 1/2 of the embodiment, the reduction ratio of the cell size, generally different depending on the depth of the P + body layer. なお、P +ボディ層用のトレンチ51は、トレンチ側面がP +ボディ層(拡散層53a,53b)内にあるため、パワーMOSの主電流通路からトレンチ側面がはずれることになる。 Incidentally, the trench 51 for the P + body layer, since the trench side is in the P + body layer (diffusion layer 53a, 53b) in composed of a main current path of the power MOS that trench sides deviate. すなわち、トレンチ側面のドライエッチングダメージが残っていても、オン抵抗を高くすることはない。 That is, even if there are still dry etching damage of the trench sides, is not possible to increase the on-resistance. 従って、P +ボディ層用トレンチはゲート用トレンチとは異なって、ダメージ除去工程が不要となるので、製作は容易となる。 Accordingly, P + body layer trench is different from the gate trenches, so the damage removing step is not required, manufacture is facilitated.

【0039】又、この実施例は第2実施例に比較して、 [0039] Further, this embodiment is compared with the second embodiment,
+ボディ層(拡散層53a,53b)の下端部間の距離が短いため、P +ボディ層間の空乏層56がつながり易くなる。 For P + body layer (diffusion layer 53a, 53b) the distance between the lower ends of the short, easily P + body layers of the depletion layer 56 ties. このため、この実施例では、第2実施例に比較してより浅いP +ボディ層(拡散層53a,53b) Therefore, in this embodiment, the shallower P + body layer as compared to the second embodiment (diffusion layer 53a, 53b)
で同等のピンチオフ効果が期待できる。 In can be expected equivalent of pinch-off effect.

【0040】なお、この発明は下記のように具体化してもよい。 [0040] Note that the present invention may be embodied as follows. (イ)前記第1実施例の構成中、N +基板1をP +基板1とすれば、IGBTにも適用可能である。 (B) during the configuration of the first embodiment, if the N + substrate 1 and the P + substrate 1 is also applicable to IGBT.

【0041】(ロ)第1乃至第3実施例の構成中、N [0041] (b) in the configuration of the first to third exemplary e.g., N
層、P層をすべて反対に入れ換えても各実施例と同様の効果を得ることができる。 Layer can be switched to the opposite all the P layer achieve the same effect as each embodiment. (ハ)前記第3実施例では、トレンチ51に充填層として多結晶シリコン膜52a. (C) In the third embodiment, the polycrystalline silicon film 52a as a filling layer in the trench 51. 52bを形成したが、充填層としてトレンチ51に対しチタンシリサイド等のシリサイド、タングステン等の金属を充填してもよい。 Were formed 52 b, silicide such as titanium silicide to the trench 51 as a filler layer, the metal may be a filling, such as tungsten.

【0042】(ハ)前記第2及び第3実施例の構成中、 [0042] (iii) in configurations of the second and third embodiments,
+基板15、N +型基板41をP N + substrate 15, an N + -type substrate 41 P +基板、P +基板とすれば、IGBTにも適用可能である。 + Substrate, if P + substrate, is also applicable to IGBT. この明細書中に記載された事項から特許請求の範囲に記載された請求項以外に把握される技術的思想についてその効果とともに記載する。 Technical ideas grasped in addition claim that is claimed from the entries of in this specification described in conjunction with its effects.

【0043】(1)請求項3において、高濃度層はトレンチ51の周辺に形成し、トレンチ51に充填した充填層から不純物が拡散されて形成されたものである電界効果型半導体素子。 [0043] (1) according to claim 3, the high concentration layer is formed around the trench 51, the field effect type semiconductor device in which impurities are formed by diffusion from the filling layer filled in the trench 51. この構成によれば、隣接する高濃度層間の距離が短くなるため、高濃度層間の空乏層がつながり易く、トレンチ51を形成しない場合に比較して、より浅い高濃度層にてピンチオフ効果が期待できる。 According to this arrangement, since the distance between adjacent high density layers becomes shorter, easier depletion of high concentration layers ties, compared with the case of not forming a trench 51, the pinch-off effect at a shallower high concentration layer expected it can.

【0044】又、隣接する高濃度層間距離が短くなるため、高濃度層間の空乏層がつながり易い。 [0044] Further, since the high concentration layer distance adjacent shorter easily depletion of high concentration layers ties. 従って、トレンチを形成しないものに比較してより浅い高濃度層にてピンンチオフ効果が期待できる。 Therefore, it is expected Pin'nchiofu effect at a shallower high concentration layer as compared with those not forming a trench.

【0045】又、本構造(図5)の形成には、高温長時間の熱処理を必要としないため、微細CMOSと同一基板上に混載することが容易にできるようになる。 [0045] Further, the formation of the structure (FIG. 5) does not require a high-temperature long-time heat treatment, so can easily be embedded in a fine CMOS on the same substrate.

【0046】 [0046]

【発明の効果】以上詳述したように、請求項1の発明によれば、低濃度層が幅狭くゲート電極直下に形成されているため、しきい値電圧は低く、さらに、オン抵抗も小さくすることができる。 As described above in detail, according to the first aspect of the invention, since the low concentration layer is formed immediately below the width narrow gate electrode, the threshold voltage is low, furthermore, also on-resistance smaller can do. さらに、高濃度層が深く形成されているため、ドレイン・ソース間の逆バイアス時にも高濃度層からドレイン方向に深く空乏層が形成されるため、空乏層の電界Eの強度が全体に弱まり、すなわち、 Furthermore, since the high concentration layer is formed deeper, because even when a reverse bias between the drain and source deep depletion drain direction from the high concentration layer is formed, the strength of the depletion layer of the electric field E is weakened throughout, That is,
低濃度層から第1導電型領域への空乏層も広がりにくく抑えられる。 Depletion from the low density layer into the first conductivity type region can be suppressed hardly spread. この結果、パンチスルー防止耐圧を維持することができる。 As a result, it is possible to maintain the punch-through prevention breakdown voltage.

【0047】請求項2の発明によれば、電界効果型半導体素子のしきい値を決定する低濃度層の表面濃度よりも第1導電領域直下の低濃度層の濃度が濃くなる。 [0047] According to the invention of claim 2, the concentration of the low concentration layer immediately below the first conductive region than the surface concentration of the low concentration layer which determines the threshold of the field effect semiconductor device becomes darker. このため、より浅い低濃度層で、パンチスルーが防止でき、オン抵抗が低減される。 Therefore, a more shallow low concentration layer, the punch-through is prevented, on-resistance is reduced. 又、寄生抵抗成分を小さくできることから、ベース電位が上昇しにくくなって寄生トランジスタが導通しにくくなり、かつ寄生トランジスタの電流増幅率hFEを小さくできるため、破壊耐量が向上する。 Moreover, because it can reduce a parasitic resistance component, the parasitic transistor does not easily conduct becomes the base potential hardly increases, and since it is possible to reduce the current amplification factor hFE of the parasitic transistor, breakdown resistance is improved.

【0048】請求項3の発明によれば、オン抵抗の低下ができ、第2導電型領域から第1導電型領域へは、電界強度が弱められ、かつ空乏層が拡がるのも抑えられるため、従来と異なり空乏層が拡がってパンチスルーが生じるのを抑止するための深いトレンチゲートの製造の必要がなくなり、製造しやすい浅いトレンチゲートでも可能となる。 [0048] According to the invention of claim 3 can decrease the on-resistance, a second conductivity type region to the first conductivity type region, the electric field strength is weakened, and since also suppressed depletion layer expands, conventional unlike the depletion layer is necessary to eliminate the production of a deep trench gate for suppressing the punch-through occurs spread, it is possible in the manufacturing easy to shallow trench gate. 又、電界強度も弱くなることから、トレンチゲート端部の丸め工程も不要となる。 Furthermore, since the even field intensity becomes weak, the process of rounding the trench gate edge becomes unnecessary.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 第1実施例の1つのセルの模式的な断面図。 Figure 1 is a schematic cross-sectional view of one cell of the first embodiment.

【図2】 図1のY−Y線で切断したときの、表面からの深さにおける不純物濃度を示すグラフ。 [Figure 2] in Figure 1 when cut at the line Y-Y, the graph showing the impurity concentration in the depth from the surface.

【図3】 従来のMOSFETを示し、(a)は平断面面図、(b)は断面図。 Figure 3 shows a conventional MOSFET, (a) is plan sectional view, (b) is a cross-sectional view.

【図4】 第2実施例の1つのセルの模式的な断面図。 Figure 4 is a schematic cross-sectional view of one cell of the second embodiment.

【図5】 第3実施例の1つのセルの模式的な断面図。 Figure 5 is a schematic cross-sectional view of one cell of the third embodiment.

【図6】 (a)は第2実施例のMOSFETの平面図、(b)は第3実施例のMOSFETの平面図。 6 (a) is a plan view of the MOSFET of the second embodiment, (b) is a plan view of the MOSFET of the third embodiment.

【図7】 従来のMOSFETの断面図。 7 is a cross-sectional view of a conventional MOSFET.

【図8】 (a)〜(f)は第3実施例の製造工程を示す説明図。 8 (a) ~ (f) are explanatory views showing manufacturing steps of the third embodiment.

【図9】 (a)〜(c)は同じく第3実施例の製造工程を示す説明図。 9 (a) ~ (c) are also explanatory views showing a manufacturing process of the third embodiment.

【符号の説明】 DESCRIPTION OF SYMBOLS

1はN +基板、2はN -エピタキシャル層(第1導電型半導体基体)、3はPボディ層(第2導電領域の低濃度層)、4はP +ボディ層(第2導電領域の高濃度層)、 1 N + substrate, 2 is N - epitaxial layer (first conductive semiconductor substrate) 3 P body layer (low concentration layer of the second conductive region) 4 P + body layer (high of the second conductive region concentration layer),
5はN +ソース層、6はゲート酸化膜、7はゲート・シリコン電極、8は層間絶縁膜、9はソース・アルミニウム電極、10はドレイン電極、11は空乏層、15はN 5 N + source layer, the gate oxide film 6, 7 gate silicon electrode, the interlayer insulating film 8, the source aluminum electrode 9, the drain electrodes 10, 11 the depletion layer, 15 N
+ドレイン層、16はNドレイン層(第1導電型半導体基体)、17はPボディ層、18は酸化絶縁膜、19はトレンチゲート、20はN +ソース層、21はソース電極、22は空乏層、23はPボディ層(第2導電領域の低濃度層)、24a,24bはP +ボディ層(第2導電領域の高濃度層)、41はN +型リコン基板、42は低濃度N型シリコン層(第1導電型半導体基体)、43は酸化膜、44はトレンチ、46は多結晶シリコン膜(ゲート電極)、48は拡散層(N +ソース層)、49は拡散層(Pボディ層:第2導電領域の低濃度層)、53 + Drain layer, 16 N drain layer (first conductivity type semiconductor substrate) 17 P body layer 18 is an oxide insulating film, 19 is a trench gate, 20 an N + source layer, 21 is a source electrode, 22 is depleted layer, 23 P body layer (low concentration layer of the second conductive region) 24a, 24b is P + body layer (high concentration layer of the second conductive region) 41 N + -type silicon substrate, 42 is a low concentration N -type silicon layer (first conductivity type semiconductor substrate), 43 denotes an oxide film, 44 is the trench, 46 a polysilicon film (gate electrode), 48 is a diffusion layer (N + source layer), 49 diffusion layer (P body layer: low-density layer of the second conductive region), 53
a,53bは拡散層(P +ボディ層:第2導電領域の高濃度層)、56は空乏層。 a, 53b are diffusion layer (P + body layer: high-concentration layer of the second conductive region), 56 depletion.

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 ドレインとなる第1導電型半導体基体(2)の表面に第2導電型領域(3,4)と、ソースとなる第1導電型領域(5)を有し、前記基体(2)表面上のゲート電極(7)への電圧印加によって基体(2) 1. A second conductive type region in a surface of the drain to become the first conductive type semiconductor substrate (2) (3, 4) have a first conductivity type region serving as a source (5), said substrate ( 2) substrate by applying a voltage to the gate electrode on the surface (7) (2)
    と前記第1導電型領域(5)に挟まれた前記第2導電型領域表面(3,4)でソース・ドレイン電流を制御するようにした電界効果型半導体素子であって、 前記第2導電型領域はゲート電極(7)直下に形成された低濃度層(3)と、、 該低濃度層(3)に接続して形成され、第1導電型領域(5)から第1導電型半導体基体(2)方向へ延びる高濃度層(4)とを含み、 前記高濃度層(4)を前記低濃度層(3)より深さ方向に幅厚に形成したことを特徴とする電界効果型半導体素子。 A field effect semiconductor device which is adapted to control the source-drain current in the first conductivity type region (5) sandwiched by the second conductivity type region surface (3,4), said second conductive -type region is formed by connecting a low concentration layer formed on the gate electrode (7) just below (3) and ,, low concentration layer (3), the first conductive type semiconductor of a first conductivity type region (5) base (2) and a high-concentration layer extending in the direction (4), wherein the high concentration layer (4) the low concentration layer (3) from forming in the width-thickness depth direction that FET characterized by the semiconductor element.
  2. 【請求項2】 低濃度層(3)の濃度ピーク位置が、第1導電型領域(2)より深い位置にあることを特徴とする請求項1に記載のパワーMOSFET。 Wherein the concentration peak position of the low concentration layer (3) is a power MOSFET according to claim 1, characterized in that in deeper than the first conductivity type region (2) position.
  3. 【請求項3】 ドレインとなる第1導電型半導体基体(16,42)の表面に第2導電型領域(23,24 3. A second conductive type region in a surface of the drain to become the first conductive type semiconductor substrate (16, 42) (23, 24
    a,24b,49,53a,53b)と、ソースとなる第1導電型領域(20,48)を有し、前記基体(1 a, a 24b, 49,53A, and 53b), a first conductive type region serving as the source (20, 48), said base body (1
    6,42)表面上のトレンチゲート(19,46)への電圧印加によって基体(16,42)と前記第1導電型領域(20,48)に挟まれた前記第2導電型領域表面(23,24a,24b,49,53a,53b)でソース・ドレイン電流を制御するようにした電界効果型半導体素子であって、 前記第2導電型領域はトレンチゲート(19,46)直近に形成された低濃度層(23,49)と、 該低濃度層(23,49)に接続して形成され、該低濃度層より第1導電型領域(20,48)から第1導電型半導体基体(16,42)方向へ延びる高濃度層(24 6, 42) substrate by applying a voltage to the trench gate on the surface (19,46) (16, 42) and said first conductivity type region (20, 48) sandwiched by the second conductivity type region surface (23 , 24a, 24b, a field effect type semiconductor device which is adapted to control 49,53A, a source-drain current in 53b), said second conductivity type region is formed in the trench gate (19,46) nearest the low concentration layer (23,49) is formed by connecting the low concentration layer (23,49), the first conductivity type from said low density layer than the first conductivity type region (20, 48) semiconductor body (16 , 42) heavily doped layer extending in a direction (24
    a,24b,53a,53b)とを含み、 該高濃度層(24a,24b,53a,53b)を前記トレンチゲート(19,46)より深さ方向に幅厚に形成したことを特徴とする電界効果型半導体素子。 a, 24b, 53a, 53b) and wherein the high-density layer (24a, 24b, 53a, electric field and 53b), characterized in that formed in the width-thickness than in the depth direction the trench gate (19,46) effect type semiconductor element.
JP7064545A 1995-03-23 1995-03-23 Field-effect type semiconductor element Pending JPH08264772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7064545A JPH08264772A (en) 1995-03-23 1995-03-23 Field-effect type semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7064545A JPH08264772A (en) 1995-03-23 1995-03-23 Field-effect type semiconductor element

Publications (1)

Publication Number Publication Date
JPH08264772A true JPH08264772A (en) 1996-10-11

Family

ID=13261308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7064545A Pending JPH08264772A (en) 1995-03-23 1995-03-23 Field-effect type semiconductor element

Country Status (1)

Country Link
JP (1) JPH08264772A (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001059848A2 (en) * 2000-02-11 2001-08-16 Intersil Corporation Mos-gated semiconductor device having alternating conductivity type semiconductor regions and methods of making the same
WO2001088997A2 (en) * 2000-05-13 2001-11-22 Koninklijke Philips Electronics N.V. Trench-gate semiconductor device and method of making the same
WO2001095385A1 (en) * 2000-06-02 2001-12-13 General Semiconductor, Inc. Method of making a power mosfet
JP2003524291A (en) * 1999-06-03 2003-08-12 ゼネラル セミコンダクター,インク. High voltage power of low on-resistance mosfet
US6627949B2 (en) 2000-06-02 2003-09-30 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US6660571B2 (en) 2000-06-02 2003-12-09 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
JP2004523095A (en) * 2000-03-31 2004-07-29 ゼネラル セミコンダクター,インク. The method of manufacturing a trench double diffused metal oxide semiconductor having a low threshold voltage
US6953968B2 (en) 2001-01-19 2005-10-11 Mitsubishi Denki Kabushiki Kaisha High voltage withstanding semiconductor device
US7037788B2 (en) 2000-05-30 2006-05-02 Denso Corporation Manufacturing method of semiconductor device
JP2006196583A (en) * 2005-01-12 2006-07-27 Shindengen Electric Mfg Co Ltd Method for manufacturing semiconductor device
JP2006351652A (en) * 2005-06-14 2006-12-28 Rohm Co Ltd Semiconductor device
JP2008010627A (en) * 2006-06-29 2008-01-17 Sanyo Electric Co Ltd Semiconductor device, and manufacturing method thereof
US7399677B2 (en) 2003-03-31 2008-07-15 Rohm Co., Ltd. Method for manufacturing semiconductor with low resistance region
JP2008199048A (en) * 2008-03-31 2008-08-28 Siliconix Inc Manufacture of high-density trenched dmos using sidewall spacer
JP2008227514A (en) * 2003-12-30 2008-09-25 Fairchild Semiconductor Corp Power semiconductor device and its production process
WO2009119479A1 (en) * 2008-03-24 2009-10-01 日本電気株式会社 Semiconductor device, and method for manufacturing the same
JP2009238872A (en) * 2008-03-26 2009-10-15 Ricoh Co Ltd Semiconductor device and method of manufacturing the same
JP2010505270A (en) * 2006-09-27 2010-02-18 マックスパワー・セミコンダクター・インコーポレイテッドMaxpower Semiconductor Inc. Power MOSFET with recessed field plate
JP2010283368A (en) * 2010-07-26 2010-12-16 Renesas Electronics Corp Method of manufacturing semiconductor device
JP2011044513A (en) * 2009-08-20 2011-03-03 National Institute Of Advanced Industrial Science & Technology Silicon carbide semiconductor device
US8193564B2 (en) 2008-02-13 2012-06-05 Denso Corporation Silicon carbide semiconductor device including deep layer
US8889511B2 (en) 2003-05-20 2014-11-18 Fairchild Semiconductor Corporation Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor
US10074742B2 (en) 2005-02-11 2018-09-11 Alpha And Omega Semiconductor Limited MOS device with island region

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003524291A (en) * 1999-06-03 2003-08-12 ゼネラル セミコンダクター,インク. High voltage power of low on-resistance mosfet
JP4860858B2 (en) * 1999-06-03 2012-01-25 ゼネラル セミコンダクター,インク. High voltage power MOSFET with low on-resistance
US6689662B2 (en) 1999-06-03 2004-02-10 General Semiconductor, Inc. Method of forming a high voltage power MOSFET having low on-resistance
US8513732B2 (en) 1999-06-03 2013-08-20 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US6992350B2 (en) 1999-06-03 2006-01-31 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
WO2001059848A3 (en) * 2000-02-11 2002-05-02 Intersil Corp Mos-gated semiconductor device having alternating conductivity type semiconductor regions and methods of making the same
WO2001059848A2 (en) * 2000-02-11 2001-08-16 Intersil Corporation Mos-gated semiconductor device having alternating conductivity type semiconductor regions and methods of making the same
JP2003523089A (en) * 2000-02-11 2003-07-29 フェアチャイルド セミコンダクター コーポレーション mos gate device with alternating conductivity zone
JP2004523095A (en) * 2000-03-31 2004-07-29 ゼネラル セミコンダクター,インク. The method of manufacturing a trench double diffused metal oxide semiconductor having a low threshold voltage
WO2001088997A2 (en) * 2000-05-13 2001-11-22 Koninklijke Philips Electronics N.V. Trench-gate semiconductor device and method of making the same
WO2001088997A3 (en) * 2000-05-13 2002-05-16 Koninkl Philips Electronics Nv Trench-gate semiconductor device and method of making the same
US7037788B2 (en) 2000-05-30 2006-05-02 Denso Corporation Manufacturing method of semiconductor device
US6660571B2 (en) 2000-06-02 2003-12-09 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
JP2004509452A (en) * 2000-06-02 2004-03-25 ゼネラル セミコンダクター,インク. Power metal oxide semiconductor field effect transistor and manufacturing method thereof
JP2003536261A (en) * 2000-06-02 2003-12-02 ゼネラル セミコンダクター,インク. Method of manufacturing a power metal oxide semiconductor field effect transistor
US6627949B2 (en) 2000-06-02 2003-09-30 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US7067376B2 (en) 2000-06-02 2006-06-27 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
WO2001095385A1 (en) * 2000-06-02 2001-12-13 General Semiconductor, Inc. Method of making a power mosfet
US7745885B2 (en) * 2000-06-02 2010-06-29 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
KR100732051B1 (en) * 2000-06-02 2007-06-27 제네럴 세미컨덕터, 인코포레이티드 High voltage mosfet and method of forming the same
US6953968B2 (en) 2001-01-19 2005-10-11 Mitsubishi Denki Kabushiki Kaisha High voltage withstanding semiconductor device
US7115944B2 (en) 2001-01-19 2006-10-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US9368587B2 (en) 2001-01-30 2016-06-14 Fairchild Semiconductor Corporation Accumulation-mode field effect transistor with improved current capability
US7399677B2 (en) 2003-03-31 2008-07-15 Rohm Co., Ltd. Method for manufacturing semiconductor with low resistance region
US8936985B2 (en) 2003-05-20 2015-01-20 Fairchild Semiconductor Corporation Methods related to power semiconductor devices with thick bottom oxide layers
US8889511B2 (en) 2003-05-20 2014-11-18 Fairchild Semiconductor Corporation Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor
JP2008227514A (en) * 2003-12-30 2008-09-25 Fairchild Semiconductor Corp Power semiconductor device and its production process
JP2006196583A (en) * 2005-01-12 2006-07-27 Shindengen Electric Mfg Co Ltd Method for manufacturing semiconductor device
JP4694846B2 (en) * 2005-01-12 2011-06-08 新電元工業株式会社 Manufacturing method of semiconductor device
US10074742B2 (en) 2005-02-11 2018-09-11 Alpha And Omega Semiconductor Limited MOS device with island region
JP2006351652A (en) * 2005-06-14 2006-12-28 Rohm Co Ltd Semiconductor device
JP2008010627A (en) * 2006-06-29 2008-01-17 Sanyo Electric Co Ltd Semiconductor device, and manufacturing method thereof
JP2010505270A (en) * 2006-09-27 2010-02-18 マックスパワー・セミコンダクター・インコーポレイテッドMaxpower Semiconductor Inc. Power MOSFET with recessed field plate
US8193564B2 (en) 2008-02-13 2012-06-05 Denso Corporation Silicon carbide semiconductor device including deep layer
US8426895B2 (en) 2008-03-24 2013-04-23 Nec Corporation Semiconductor device and manufacturing method of the same
WO2009119479A1 (en) * 2008-03-24 2009-10-01 日本電気株式会社 Semiconductor device, and method for manufacturing the same
JP2009238872A (en) * 2008-03-26 2009-10-15 Ricoh Co Ltd Semiconductor device and method of manufacturing the same
JP2008199048A (en) * 2008-03-31 2008-08-28 Siliconix Inc Manufacture of high-density trenched dmos using sidewall spacer
JP2011044513A (en) * 2009-08-20 2011-03-03 National Institute Of Advanced Industrial Science & Technology Silicon carbide semiconductor device
JP2010283368A (en) * 2010-07-26 2010-12-16 Renesas Electronics Corp Method of manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
US8148224B2 (en) Insulated gate type semiconductor device and method for fabricating the same
JP4874516B2 (en) Trench double-diffused metal oxide semiconductor transistor incorporating a trench Schottky rectifier
JP4236848B2 (en) Manufacturing method of semiconductor integrated circuit device
US6800897B2 (en) Integrated circuit power devices having junction barrier controlled schottky diodes therein
US7705362B2 (en) Silicon carbide devices with hybrid well regions
JP3216804B2 (en) Method for producing a silicon carbide vertical fet and silicon carbide vertical fet
US6118150A (en) Insulated gate semiconductor device and method of manufacturing the same
US8022414B2 (en) Silicon carbide semiconductor device, and method of manufacturing the same
JP4723698B2 (en) Power switching trench MOSFET having matched source region and method of manufacturing the same
JP4123636B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
US7586148B2 (en) Power semiconductor device having a voltage sustaining region that includes doped columns formed by terraced trenches
CN100342505C (en) Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
JP3395473B2 (en) Lateral trench misfet and a method of manufacturing the same
US7663186B2 (en) Semiconductor device
US6284604B1 (en) Method for producing a field-effect-controllable, vertical semiconductor component
CN1171318C (en) High voltage power MOSFET with low flow resistance
CN1079996C (en) High-voltage metal oxide silicon field effect transistor (MOSFET) structure
CN100334731C (en) Trench DMOS transistor with embedded trench schottky rectifier
JP3202021B2 (en) Punch-through field-effect transistor
US6211552B1 (en) Resurf LDMOS device with deep drain region
US6432775B2 (en) Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface
US20050001268A1 (en) Power semiconductor devices having linear transfer characteristics when regions therein are in velocity saturation modes and methods of forming and operating same
JP2006073740A (en) Semiconductor device and its manufacturing method
JP2008546216A (en) Charge balanced field effect transistor
JP3837178B2 (en) High power mos-type field effect trench transistor device