CN107248533A - A kind of carborundum VDMOS device and preparation method thereof - Google Patents

A kind of carborundum VDMOS device and preparation method thereof Download PDF

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CN107248533A
CN107248533A CN201710432727.0A CN201710432727A CN107248533A CN 107248533 A CN107248533 A CN 107248533A CN 201710432727 A CN201710432727 A CN 201710432727A CN 107248533 A CN107248533 A CN 107248533A
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layer
polysilicon
pbase
gate
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CN107248533B (en
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张金平
邹华
刘竞秀
李泽宏
任敏
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

The invention discloses a kind of carborundum VDMOS device and preparation method thereof, belong to power semiconductor technologies field.The present invention is integrated with a diode by the JFET areas surface direct deposition of polycrystalline silicon floor formation Si/SiC hetero-junctions in carborundum VDMOS device in device inside, optimizes application of the device in the fields such as inverter circuit, chopper circuit.It is of the invention to be more easy to realize forward conduction compared with directly using the parasitic silicon carbide diodes of VDMOS in the prior art, and with relatively low power attenuation, faster operating rate and higher operating efficiency；The present invention reduces device and uses number, reduce the line between device, be conducive to device miniaturization to develop compared with using in the prior art in one FRD of device exterior inverse parallel；In addition, present invention reduces grid width, reducing gate capacitance, device operating rate is further improved.Therefore, VDMOS device proposed by the present invention has broad application prospects in circuit fields such as inverter circuit, chopper circuits.

Description

A kind of carborundum VDMOS device and preparation method thereof
Technical field
The invention belongs to power semiconductor technologies field, and in particular to a kind of carborundum VDMOS device and preparation method thereof.
Background technology
Since the mankind enter 21 century, energy problem becomes increasingly conspicuous.In energy-saving and emission-reduction cry more surging today, It is small to arrive household electrical appliance, electric automobile, it is particularly important to the transformation of electrical energy problem in industrial production, locomotive traction greatly, electric power Optimization and improvement of the scientific research personnel of electronic applications to electric power management system just seem very crucial.
Power device is the core of modern power systems.Because the performance of traditional silicon-based power devices has been sufficiently close to The silicon materials limit, its performance is difficult to have greatly improved.So, some semiconductor material with wide forbidden band such as carborundum (SiC) There are the excellent properties more more attractive than silicon materials with gallium nitride (GaN), so that the research of carborundum, gallium nitride material As the new focus of power device.
Carborundum VDMOS device is the new generation of semiconductor device manufactured using semiconductor material with wide forbidden band carborundum.By There is larger energy gap, high heat conductance, high electronics saturation drift velocity and height compared with silicon materials in carbofrax material Critical breakdown electric field so that carbofrax material has very in HTHP, intense radiation and powerful power application field Wide application prospect.
Because carborundum VDMOS device has above-mentioned excellent characteristic, therefore obtained in the circuits such as inverter circuit, chopper circuit To being widely applied.Carborundum VDMOS device is generally required and one in the application of the circuits such as traditional inverter circuit, chopper circuit Individual anti-paralleled diode plays a role jointly, generally there is following two modes：One is：Directly using device Pbase, N- areas with The parasitic PIN diode of N+ substrates formation.However, big (the carbon of the conduction voltage drop of the parasitic silicon carbide diode obtained under this mode SiClx PN junction conduction voltage drop is about 3V), and reverse recovery characteristic is poor that (drift region conductance modulation injects a large amount of mistakes during forward conduction Surplus carrier), high power loss is result in, this with emphasizing that the application theory of environmental protection is runed counter to instantly；Meanwhile, because of its work speed Degree is low and causes operating efficiency low, this to carborundum VDMOS device in the application such as inverter circuit, chopper circuit extremely not Profit；Secondly being：Device is used with outside fast recovery diode (FRD) inverse parallel.However, this mode can cause system into This rising, the increase of volume and because caused by metal connecting line increase reliability reduce, finally cause carborundum VDMOS devices Popularization of the part in the application of the circuits such as traditional inverter circuit, chopper circuit receives certain obstruction.
In summary, the extensive use in the circuits such as inverter circuit, chopper circuit of carborundum VDMOS device how is realized, And the height of the power attenuation present in existing application, inefficiency are solved, the problems such as system cost is high becomes art technology The problem of personnel's urgent need to resolve.
The content of the invention
In order to solve the problems of prior art, the present invention is direct on the JFET areas surface of carborundum VDMOS device Deposit polycrystalline silicon layer so that the JFET areas surface of polysilicon layer and carborundum forms Si/SiC hetero-junctions, and the present invention is by device The technological means that part is internally integrated diode provides a kind of carbon that can be widely applied for the circuits such as inverter circuit, chopper circuit SiClx VDMOS device.
To achieve the above object, on the one hand, the invention discloses the technical scheme of carborundum VDMOS device, particular technique Scheme is as follows：
Technical scheme 1：
A kind of carborundum VDMOS device, its structure cell includes：The metal leakage pole 10 that sets gradually from bottom to top, N+ Substrate 9 and N-Epitaxial layer 8；The N-The upper strata one end of epitaxial layer 8 has the first Pbase areas 7, the N-The upper strata other end of epitaxial layer 8 With the 2nd Pbase areas 71；There is the first separate N in the first Pbase areas 7+The P of source region 6 and the first+Contact zone 5； There is the 2nd separate N in the 2nd Pbase areas 71+The P of source region 61 and the 2nd+Contact zone 51；First P+Contact zone The 5 and N of part the first+The upper surface of source region 6 has the first metal source 3；2nd P+Contact zone 51 and the N of part the 2nd+Source The upper surface in area 61 has the second metal source 31；It is characterized in that：In the upper surface of the first Pbase areas 7, the first N+ source regions 6 Portion of upper surface and N-The portion of upper surface of epitaxial layer 8 also has the first grid structure contacted therewith；The first grid knot Structure includes the first gate dielectric layer 4, the first polysilicon gate 2 positioned at the upper surface of the first gate dielectric layer 4 and positioned at the first polysilicon gate 2 The first gate electrode 1 of upper surface；In the upper surface of the 2nd Pbase areas 71, the portion of upper surface of the 2nd N+ source regions 61 and N-Epitaxial layer 8 Point upper surface also has the second grid structure contacted therewith；The second grid structure includes the second gate dielectric layer 41, position The second polysilicon gate 21 and the second gate electrode positioned at the upper surface of the second polysilicon gate 21 in the upper surface of the second gate dielectric layer 41 11；JFET areas upper surface between first grid structure and second grid structure also has and N-The formation of epitaxial layer 8 Si/SiC The P of hetero-junctions+Polysilicon layer 12；The P+The upper surface of polysilicon layer 12 has metal electrode 13, the P+Polysilicon layer 12 and gold Category electrode 13 is connected with the first metal source 3 and the second metal source 31 respectively；Between each metal structure and P+ Polysilicon layer 12 and two polysilicon gates 2,21 are mutually isolated by medium.
Technical scheme 2：
A kind of carborundum VDMOS device, its structure cell includes：The metal leakage pole 10 that sets gradually from bottom to top, N+ Substrate 9 and N-Epitaxial layer 8；The N-The upper strata one end of epitaxial layer 8 has the first Pbase areas 7, the N-The upper strata other end of epitaxial layer 8 With the 2nd Pbase areas 71；There is the first separate N in the first Pbase areas 7+The P of source region 6 and the first+Contact zone 5； There is the 2nd separate N in the 2nd Pbase areas 71+The P of source region 61 and the 2nd+Contact zone 51；First P+Contact zone The 5 and N of part the first+The upper surface of source region 6 has the first metal source 3；2nd P+Contact zone 51 and the N of part the 2nd+Source The upper surface in area 61 has the second metal source 31；It is characterized in that：In the upper surface of the first Pbase areas 7, the first N+ source regions 6 Portion of upper surface and N-The portion of upper surface of epitaxial layer 8 also has the first grid structure contacted therewith；The first grid knot Structure includes the first gate dielectric layer 4, the first polysilicon gate 2 positioned at the upper surface of the first gate dielectric layer 4 and positioned at the first polysilicon gate 2 The first gate electrode 1 of upper surface；In the upper surface of the 2nd Pbase areas 71, the portion of upper surface of the 2nd N+ source regions 61 and N-Epitaxial layer 8 Point upper surface also has the second grid structure contacted therewith；The second grid structure includes the second gate dielectric layer 41, position The second polysilicon gate 21 and the second gate electrode positioned at the upper surface of the second polysilicon gate 21 in the upper surface of the second gate dielectric layer 41 11；JFET areas upper surface between first grid structure and second grid structure also has and N-The formation of epitaxial layer 8 Si/SiC The P of hetero-junctions+Polysilicon layer 12；P+Provided with separate first medium layer 14 and second dielectric layer 15 inside polysilicon layer 12, And two dielectric layers 14,15 are and N-Epitaxial layer 8 is in contact；The P+The upper surface of polysilicon layer 12 has metal electrode 13, institute State P+Polysilicon layer 12 and metal electrode 13 are connected with the first metal source 3 and the second metal source 31 respectively；It is described each Between metal structure and P+Polysilicon layer 12 and two polysilicon gates 2,21 are mutually isolated by medium.
The present invention adds technical characteristic on the basis of technical scheme 1, i.e., in P+Phase is additionally provided with inside polysilicon layer 12 It is mutually independent and and N-First medium layer 14 and second dielectric layer 15 that epitaxial layer 8 is in contact；During diode applications, first medium Layer 14 and second dielectric layer 15 are in P+The electron accumulation layer that the lower section of polysilicon layer 12 is formed, can further reduce the drift of device Area's resistance is moved, and then reduces the forward conduction voltage drop of device.
Technical scheme 3：
A kind of carborundum VDMOS device, its structure cell includes：The metal leakage pole 10 that sets gradually from bottom to top, N+ Substrate 9 and N-Epitaxial layer 8；The N-The upper strata one end of epitaxial layer 8 has the first Pbase areas 7, the N-The upper strata other end of epitaxial layer 8 With the 2nd Pbase areas 71；There is the first separate N in the first Pbase areas 7+The P of source region 6 and the first+Contact zone 5； There is the 2nd separate N in the 2nd Pbase areas 71+The P of source region 61 and the 2nd+Contact zone 51；First P+Contact zone The 5 and N of part the first+The upper surface of source region 6 has the first metal source 3；2nd P+Contact zone 51 and the N of part the 2nd+Source The upper surface in area 61 has the second metal source 31；It is characterized in that：In N-In epitaxial layer 8 and under the first Pbase areas 7 Side also has the first p-type silicon carbide region 16 for forming superjunction or half super-junction structure, in N-In epitaxial layer 8 and positioned at second The lower section of Pbase areas 71 also has the second p-type silicon carbide region 161 for forming superjunction or half super-junction structure；In the first Pbase areas 7 Upper surface, the portion of upper surface of the first N+ source regions 6 and N-The portion of upper surface of epitaxial layer 8 also has the first grid knot contacted therewith Structure；The first grid structure includes the first gate dielectric layer 4, the and of the first polysilicon gate 2 positioned at the upper surface of the first gate dielectric layer 4 First gate electrode 1 positioned at the upper surface of the first polysilicon gate 2；On the upper surface of the 2nd Pbase areas 71, the part of the 2nd N+ source regions 61 Surface and N-The portion of upper surface of epitaxial layer 8 also has the second grid structure contacted therewith；The second grid structure includes Second gate dielectric layer 41, the second polysilicon gate 21 positioned at the upper surface of the second gate dielectric layer 41 and on the second polysilicon gate 21 Second gate electrode 11 on surface；JFET areas upper surface between first grid structure and second grid structure also has and N-Outside Prolong the P of the formation Si/SiC hetero-junctions of layer 8+Polysilicon layer 12；The P+The upper surface of polysilicon layer 12 has metal electrode 13, the P+Polysilicon layer 12 and metal electrode 13 are connected with the first metal source 3 and the second metal source 31 respectively；Each metal Between structure and P+Polysilicon layer 12 and two polysilicon gates 2,21 are mutually isolated by medium.
The present invention adds technical characteristic on the basis of technical scheme 1, i.e., in N-In epitaxial layer 8 and positioned at first The lower section of Pbase areas 7 also has the first p-type silicon carbide region 16 for forming superjunction or half super-junction structure, in N-In epitaxial layer 8 and position Also have in the lower section of the 2nd Pbase areas 71 and form superjunction or half the second p-type of super-junction structure silicon carbide region 161；Superjunction is partly super The formation of junction structure, can further reduce diode applications and when MOS is applied device drift zone resistance, and then reduce device Forward conduction voltage drop.
Technical scheme 4：
A kind of carborundum VDMOS device, its structure cell includes：The metal leakage pole 10 that sets gradually from bottom to top, N+ Substrate 9 and N-Epitaxial layer 8；The N-The upper strata one end of epitaxial layer 8 has the first Pbase areas 7, the N-The upper strata other end of epitaxial layer 8 With the 2nd Pbase areas 71；There is the first separate N in the first Pbase areas 7+The P of source region 6 and the first+Contact zone 5； There is the 2nd separate N in the 2nd Pbase areas 71+The P of source region 61 and the 2nd+Contact zone 51；First P+Contact zone The 5 and N of part the first+The upper surface of source region 6 has the first metal source 3；2nd P+Contact zone 51 and the N of part the 2nd+Source The upper surface in area 61 has the second metal source 31；It is characterized in that：In N-In epitaxial layer 8 and under the first Pbase areas 7 Side also has the first p-type silicon carbide region 16 for forming superjunction or half super-junction structure, in N-In epitaxial layer 8 and positioned at second The lower section of Pbase areas 71 also has the second p-type silicon carbide region 161 for forming superjunction or half super-junction structure；In the first Pbase areas 7 Upper surface, the portion of upper surface of the first N+ source regions 6 and N-The portion of upper surface of epitaxial layer 8 also has the first grid knot contacted therewith Structure；The first grid structure includes the first gate dielectric layer 4, the and of the first polysilicon gate 2 positioned at the upper surface of the first gate dielectric layer 4 First gate electrode 1 positioned at the upper surface of the first polysilicon gate 2；On the upper surface of the 2nd Pbase areas 71, the part of the 2nd N+ source regions 61 Surface and N-The portion of upper surface of epitaxial layer 8 also has the second grid structure contacted therewith；The second grid structure includes Second gate dielectric layer 41, the second polysilicon gate 21 positioned at the upper surface of the second gate dielectric layer 41 and on the second polysilicon gate 21 Second gate electrode 11 on surface；JFET areas upper surface between first grid structure and second grid structure also has and N-Outside Prolong the P of the formation Si/SiC hetero-junctions of layer 8+Polysilicon layer 12；P+The inside of polysilicon layer 12 is provided with separate first medium layer 14 With second dielectric layer 15, and two dielectric layers 14,15 are and N-Epitaxial layer 8 is in contact；The P+The upper table mask of polysilicon layer 12 There are metal electrode 13, the P+Polysilicon layer 12 and metal electrode 13 are electric with the first metal source 3 and the second source metal respectively Pole 31 is connected；Between each metal structure and P+Polysilicon layer 12 and two polysilicon gates 2,21 by medium mutually every From.
The present invention adds technical characteristic on the basis of technical scheme 1, i.e., in P+Phase is additionally provided with inside polysilicon layer 12 It is mutually independent and and N-First medium that epitaxial layer 8 is in contact layer 14 and second dielectric layer 15 and in N-In epitaxial layer 8 and respectively Also have positioned at the lower section of Liang Ge Pbase areas 7,71 and form superjunction or half super-junction structure p-type silicon carbide region 16,161；This technology side Case reaches the drift zone resistance for further reducing device, and then reduce the forward conduction voltage drop of device by above-mentioned technological means Purpose.
On the other hand, the invention discloses the technical scheme of above-mentioned technical proposal preparation method, concrete technical scheme is as follows：
Technical scheme 5：
A kind of preparation method of carborundum VDMOS device, it is characterised in that comprise the following steps：
The first step：Using epitaxy technique, in silicon carbide N+N is made in the upper surface of substrate 9-Epitaxial layer 8；
Second step：Using photoetching and ion implantation technology, in N-The upper strata one end implanting p-type semiconductor impurities shape of epitaxial layer 8 Into the first Pbase areas 7, in N-Upper strata the 2nd Pbase areas 71 of other end implanting p-type semiconductor impurities formation of epitaxial layer 8；
3rd step：Using photoetching and ion implantation technology, in the first Pbase areas 7, upper strata implanting p-type semiconductor impurities are formed First P+Contact zone 5, in the 2nd P of upper strata implanting p-type semiconductor impurities formation of the 2nd Pbase areas 71+Contact zone 51；
4th step：Using photoetching and ion implantation technology, on the upper strata of the first Pbase areas 7, injection N-type semiconductor impurity is formed First N+Source region 6, in the upper strata of the 2nd Pbase areas 71 injection N-type semiconductor impurity the 2nd N+ source regions 61 of formation；First P+ connects The tactile N+ source regions 6 of area 5 and the first are separate, and the 2nd P+ contact zones 51 and the 2nd N+ source regions 61 are separate；Then pass through The impurity of high-temperature annealing activation injection；
5th step：Using deposition and etching technics, gate dielectric layer is grown in device upper surface, etching is removed in the middle of JFET areas Part gate dielectric layer formation window above position, then deposits P in device upper surface+Polysilicon layer, etching removes unnecessary many Crystal silicon layer and unnecessary gate dielectric layer, are made the first gate dielectric layer 4, the second gate dielectric layer 41, the first polysilicon gate 2, the second polycrystalline Si-gate 21 and P+Polysilicon layer 12, wherein：First gate dielectric layer 4 is distinguished in the upper surface of the first Pbase areas 7, and the left and right sides With the first N+The portion of upper surface of source region 6 and N-The portion of upper surface of epitaxial layer 8 is in contact, and the first polysilicon gate 2 is in the first gate dielectric layer 4 upper surfaces, the second gate dielectric layer 41 in the upper surface of the 2nd Pbase areas 71, and the left and right sides respectively with the first N+The part of source region 6 Upper surface and N-The portion of upper surface of epitaxial layer 8 is in contact, and the second polysilicon gate 21 is in the upper surface of the second gate dielectric layer 41, P+Polycrystalline Silicon layer 12 is located between the first gate dielectric layer 4 and the second gate dielectric layer 41；
6th step：Using Metal deposition and etching technics, in the first N+The P of source region 6 and the first+The upper surface of contact zone 5 generation the One metal source 3；In the 2nd N+The P of source region 61 and the 2nd+The upper surface of contact zone 51 generates the second metal source 31；First The upper surface of polysilicon gate 2 generates first gate electrode 1；The second gate electrode 11 is generated in the upper surface of the second polysilicon gate 21；By device Thinning back side deposit metal formation drain electrode 10；In P+The upper surface of multi-crystal silicon area 12 forms metal electrode 13；13 points of metal electrode It is not connected with the first metal electrode 3 and the second metal source 31；Carborundum VDMOS device is made.
Further, the present invention also include before the 6th step process：Caused respectively by dielectric deposition and etching technics Isolated between metal structure and P+ multi-crystal silicon areas 12 and two polysilicon gates 2,21 using medium.
Further, the technique of carborundum VDMOS device and technical solution of the present invention 5 as described in technical scheme 2 are made public The technique opened is essentially identical, and the main distinction is：, need not etching away by the change of layout size in the 5th step process Polysilicon layer and its under gate dielectric layer when so that the P of reservation+The size of multi-crystal silicon area 12 is more than etching gate dielectric layer institute shape Into the size of window, i.e., in the P+The lower section both sides of polysilicon layer 12 also have and N respectively-The first medium that epitaxial layer 8 is in contact Layer 14 and second dielectric layer 15.First medium layer and the material of second dielectric layer are not limited to gate dielectric layer material in the present invention, According to those skilled in the art's general knowledge, the dielectric layer of other materials can be made using existing deposition and etching technics.
Further, the technique of carborundum VDMOS device and technical solution of the present invention 5 as described in technical scheme 3 are made public The technique opened is essentially identical, and the main distinction is：By multistep photoetching and ion implantation technology, form super in N- epitaxial layers 8 The manufacture craft of knot or half super-junction structure, superjunction or half super-junction structure has been prior art, be will not be repeated here.
In addition, technical scheme proposed by the invention is applicable not only to carborundum VDMOS device, while suitable for carborundum RC-IGBT devices, the RC-IGBT devices are by the N of the carborundum VDMOS device+Substrate 9 replaces with the p-type of parallel arranged Collecting zone (17) and N-type collecting zone (18)；Further, in N-Epitaxial layer (8) and p-type collecting zone (17) and N-type collecting zone (18) can also have one layer of N-type cut-off (FS) layer (19) between.
It can be seen from those skilled in the art's general knowledge：In the silicon carbide power VDMOS device structure that the present invention is provided, Acceptor ion and donor ion can be exchanged in each structure, for technical measure, and substrate and epitaxial layer can be N-type Semi-conducting material, the doping polycrystalline silicon layer type that the corresponding present invention is set up is p-type；Substrate and epitaxial layer can be P-type semiconductor Material, the doping polycrystalline silicon layer type that the corresponding present invention is set up is N-type.In addition, it can be seen from the knowledge of hetero-junctions physics, passing through The doping concentration of epitaxial layer and polysilicon layer is adjusted, when substrate and epitaxial layer are N-type semiconductor material, doping polycrystalline silicon layer type Can also be N-type, when substrate and epitaxial layer are p-type semiconductor material, doping polycrystalline silicon layer type can also be p-type.
The gate dielectric layer and dielectric layer material used in the present invention can be silica (SiO2) or any conjunction Suitable material, for example：Silicon nitride (Si3N4), hafnium oxide (HfO2), alundum (Al2O3) (Al2O3) contour K dielectric materials.
The operation principle of the present invention is described below：
Power VDMOSFET device usually requires to use with diode inverse parallel in the application such as inverter circuit, chopper circuit, and one As there are following two methods to realize：
1) directly uses its parasitic PIN diode, i.e. Pbase areas, N-Drift region and N+The poles of PIN bis- that substrate is formed Pipe.It can be seen from the general knowledge of this area：The PN junction conduction voltage drop of carborundum PIN diode is about 3V or so, higher conducting Pressure drop result in high power attenuation and slow operating rate, and this should in inverter circuit, chopper circuit etc. for VDMOS device With very unfavorable, in addition, being directly easily caused the problem of reverse recovery characteristic is poor using parasitic silicon carbide diode；
2) is used and an antiparallel mode of fast recovery diode (FRD).Which can improve to a certain extent The characteristic of diode, but have that production cost is high, system bulk is big and the low deficiency of reliability.
And structure of the present invention passes through p-type (N-type) in the floor polysilicon of JFET areas surface deposition one of carborundum VDMOS device P-type (N-type) Si and N-type (p-type) SiC in carborundum JFET areas surface forms hetero-junctions in integrated two pole of device inside in polysilicon Pipe.On the one hand, by p-type polysilicon and N-type carborundum or N-type polycrystalline silicon form the knot pressure of hetero-junctions with p-type carborundum Drop is about 1V, and compared with the knot pressure drop of parasitic carborundum PN junction is about 3V, it is heterogeneous that p-type polysilicon and N-type carborundum are formed Knot can be turned under relatively low pressure drop, therefore, cause device in device inside integrated diode by technical measure Have the advantages that conduction voltage drop is low in actual applications.On the other hand, p-type polysilicon and N-type carborundum formation hetero-junctions, two During pole pipe forward conduction, because the effect of hetero-junctions is only electronic conduction, the injection in no hole, conductive mould during diode applications Formula is many subconductivity (present invention forms hetero-junctions and the injection without few son is believed that in forward conduction) so that reverse recovery time It is short, the few advantage of QRR, therefore, with good reverse recovery characteristic；Reversely it is pressure-resistant when, due to above-mentioned hetero-junctions Electronic barrier height with about 1.5eV, and the first Pbase areas 7 and the 2nd Pbase areas 71 are there is provided electric field shielding work Have and traditional VDMOS device identical voltage blocking capability and low reverse with so that device architecture disclosed by the invention Electric leakage.Meanwhile, the p-type polysilicon structure that VDMOS device is connected in mode of operation, due to device JFET areas surface with source electrode The grid width for reducing VDMOS device JFET areas surface is introduced, grid capacitance and gate charge is reduced, is not influenceing On the basis of the other characteristics of VDMOS device, the switching speed of VDMOS device is improved, and reduces the requirement to drive circuit.
The beneficial effects of the invention are as follows：
Present invention offer causes polysilicon and epitaxial layer shape in the JFET areas surface deposition polysilicon of carborundum VDMOS device Into hetero-junctions, this technological means can have remarkable result for boost device performance：
(1) a kind of carborundum VDMOS device proposed by the present invention, compared to the directly parasitic silicon carbide diodes of use VDMOS, By in device the technological means of integrated diode reduce forward conduction voltage drop, therefore make it in inverter circuit, chopper circuit It is more easy to realize forward conduction in applying Deng transformation of electrical energy, and with lower-wattage loss and higher operating efficiency.
(2) conduction mode of present invention proposition device architecture is in diode applications, from the double of carborundum parasitic diode Extremely conductive (conductance modulation) is changed into many subconductivity, so that device is in the transformation of electrical energy application such as inverter circuit, chopper circuit In have reverse recovery time short, the characteristics of QRR is few and faster switching speed.
(3) a kind of carborundum VDMOS device proposed by the present invention, compared to the inverse parallel one outside carborundum VDMOS device The application mode of individual fast recovery diode (FRD), directly uses in the integrated diode of device inside, reduces device and use Number, reduces the line between device, with the advantage that production cost is low, device reliability is high and system bulk is small.
(4) a kind of carborundum VDMOS device proposed by the present invention, reversely it is pressure-resistant when due to hetero-junctions 1.5eV or so Electronic barrier height, and the electric field shielding effect that the first Pbase areas 7 and the 2nd Pbase areas 71 are provided so that the structure has Have and traditional VDMOS device identical voltage blocking capability and low reverse leakage.
(5) a kind of carborundum VDMOS device proposed by the present invention, by the grid width and grid that reduce JFET areas surface Pole electric charge, on the basis of the other characteristics of VDMOS device are not influenceed, further increases the switching speed of VDMOS device, and Reduce the requirement to drive circuit.
Brief description of the drawings
Fig. 1 is Conventional silicon carbide VDMOS device structure cell schematic diagram；
Fig. 2 is the basic structure cell schematic diagram of a kind of carborundum VDMOS device that the present invention is provided；
Fig. 3 is a kind of the first derived structure schematic diagram of basic structure cell of carborundum VDMOS device that the present invention is provided；
Fig. 4 is a kind of the second derived structure schematic diagram of basic structure cell of carborundum VDMOS device that the present invention is provided；
Fig. 5 is that a kind of carborundum VDMOS device preparation method that the present invention is provided forms N- carbon on silicon carbide N+substrate The structural representation formed after SiClx epitaxial layer；
Fig. 6 be a kind of carborundum VDMOS device preparation method for providing of the present invention on silicon carbide N-epitaxial layer by light Carve and the structural representation behind ion implanting formation Pbase areas；
Fig. 7 be a kind of carborundum VDMOS device preparation method for providing of the present invention in carborundum Pbase areas by photoetching With ion implanting formation carborundum P+Structural representation behind base；
Fig. 8 be a kind of carborundum VDMOS device preparation method for providing of the present invention in carborundum Pbase areas by photoetching With ion implanting formation silicon carbide N+Structural representation after source region；
Fig. 9 be a kind of carborundum VDMOS device preparation method for providing of the present invention after device surface formation gate dielectric layer, Etch away the structural representation after the part gate dielectric layer formation P+ polysilicon contacts area window of JFET upper centers；
Figure 10 is that a kind of carborundum VDMOS device preparation method that the present invention is provided deposits P+ polysilicon layers in device surface Structural representation afterwards；
It is unwanted that Figure 11 is that a kind of carborundum VDMOS device preparation method for providing of the present invention is etched away in device surface Polysilicon layer and its under gate dielectric layer after the structural representation that is formed；
Figure 12 is that a kind of structure of the carborundum VDMOS device preparation method of the invention provided after metal contact is formed is shown It is intended to；
In figure：1 is first gate electrode, and 11 be the second gate electrode, and 2 be the first polysilicon gate, and 21 be the second polysilicon gate, 3 It is the second source electrode for the first source electrode, 31,4 be the first gate dielectric layer, and 41 be the second gate dielectric layer, and 5 be the first P+Contact zone, 51 be the 2nd P+Contact zone, 6 be the first N+Source region, 61 be the 2nd N+Source region, 7 be the first Pbase areas, and 71 be the 2nd Pbase areas, 8 For N-Epitaxial layer, 9 be N+Substrate, 10 be drain electrode, and 12 be P+Polysilicon layer, 13 be metal electrode, and 14 be first medium layer, 15 It is the first p-type silicon carbide region for second dielectric layer, 16,161 be the second p-type silicon carbide region.
Embodiment
Below in conjunction with Figure of description, by taking the carborundum VDMOS device of 1700V a kind of as an example, it is described in detail the present invention's Technical scheme, while the principle and characteristic to the present invention are described further.The present embodiment is served only for explaining the present invention, not For limiting the scope of the present invention.
Embodiment 1：
A kind of carborundum VDMOS device that the present invention is provided, the structure cell of its basic structure is as shown in Figure 2.Including certainly It is lower and on the thickness that sets gradually be about 0.5~6 μm metal leakage pole 10, doping concentration be 1 × 1018cm-3~1 × 1019cm-3, thickness is 50~200 μm of N+Substrate 9 and thickness are 15~18 μm, doping concentration is about 1 × 1015cm-3~5 × 1016cm-3N-Epitaxial layer 8；There is doping concentration to be 1 × 10 for the top of N- epitaxial layers 817~7 × 1017cm-3, injection depth About 0.5~1 μm of the first Pbase areas 7, its upper strata other end has the 2nd Pbase areas 71 of identical parameters；Described first It is 1 × 10 to have separate doping concentration in Pbase areas 719~1 × 1020cm-3, injection depth be about 0.3~0.5 μm First N+Source region 6 and doping concentration are about 3 × 1019~1 × 1020cm-3, injection depth be about 0.3~0.5 μm of the first P+Contact Area 5；In the 2nd Pbase areas 71 there is separate doping concentration to be about 1 × 1019~1 × 1020cm-3, injection depth About 0.3~0.5 μm of the 2nd N+ source regions 61 and doping concentration is about 3 × 1019~1 × 1020cm-3, injection depth be about 0.3 ~0.5 μm of the 2nd P+Contact zone 51；First P+Contact zone 5 and the N of part the first+There is the upper surface of source region 6 thickness to be about 1 ~6 μm of the first metal source 3；2nd P+Contact zone 51 and the N of part the 2nd+There is the upper surface of source region 61 thickness to be about 1 ~6 μm of the second metal source 31；It is characterized in that：The upper surface of first Pbase areas 7 and the first N+Source region 6 and N-Outside Prolonging the portion of upper surface of layer 8 also has first grid structure, and affiliated first grid structure is in the first Pbase areas 7 or so two Side respectively with the first N+Source region 6 and N-The surface of epitaxial layer 8 is in contact, the first grid structure by the first gate oxide 4, be located at First polysilicon gate 2 of the top of the first gate oxide 4 and the gate electrode 1 positioned at the upper surface of the first polysilicon gate 2 are constituted；Described The upper surface of two Pbase areas 71 and the N of N- epitaxial layers 8 and the 2nd+The portion of upper surface of source region 61 also has second grid structure, institute State second grid structure described the right and left of 2nd Pbase areas 71 respectively with the N of N- epitaxial layers 8 and the 2nd+The surface phase of source region 61 Contact, the second grid structure is by the second gate oxide 41, the second polysilicon gate positioned at the upper surface of the second gate oxide 41 21 and the gate electrode 11 positioned at the upper surface of the second polysilicon gate 21 constitute；The thickness of gate oxide 4,41 is 0.02~0.2 μm, many The thickness of crystal silicon grid 2,21 is 0.3~1 μm, doping concentration is 1 × 1017~5 × 1019cm-3, the thickness of gate electrode 1,11 is 0.5 ~6 μm, the grid structure and N+The length that source region 6,61 is contacted is 0.1~0.5 μm, the grid structure and N-Epitaxial layer 8 connects Tactile length is 0.1~3 μm；Device JFET areas surface between first and second grid structure also has P+Polysilicon layer 12, the P+Polysilicon layer 12 and the N on JFET areas surface-Epitaxial layer 8 is directly contacted, and forms Si/SiC hetero-junctions, the P+It is many The thickness of crystal silicon layer 12 is 0.3~1 μm, width is 0.5~3 μm, and doping concentration is 1 × 1017~5 × 1019cm-3, with described One and second grid structure distance be 0.1~1 μm；The P+The upper surface of polysilicon layer 12 has metal electrode 13, the P+It is many Crystal silicon layer 12 and thereon metal electrode 13 are connected with metal source 3,31 by metal lead wire respectively, the metal electrode 13 Thickness is 0.5~6 μm；Between each metal contact, P+It is suitable by BPSG or other between polysilicon layer and polysilicon gate Medium it is mutually isolated.
Embodiment 2：
Except P+The lower section both sides of polysilicon layer 12 also have and N-The first medium layer 14 and second that epitaxial layer 8 is directly contacted is situated between Matter layer 15, remaining structure of the present embodiment is same as Example 1.
In diode applications, first medium layer 14 and second dielectric layer 15 are in P+The electricity that the lower section of polysilicon layer 12 is formed Sub- accumulation layer, can further reduce the drift zone resistance of device, and then reduce the forward conduction voltage drop of device.
Embodiment 3：
Except in N-Have positioned at the lower section of the first Pbase areas 7 in epitaxial layer 8 and also and form superjunction or half super-junction structure first P-type silicon carbide region 16, in N-Have positioned at the lower section of the first Pbase areas 7 in epitaxial layer 8 and also and form superjunction or half super-junction structure Second p-type silicon carbide region 161, remaining structure of the present embodiment is same as Example 1.
The formation of superjunction or half super-junction structure, can further reduce diode applications and when MOS is applied device drift Area's resistance, and then reduce the forward conduction voltage drop of device.
Compared with the structure cell of Conventional silicon carbide VDMOS device shown in Fig. 1, the present invention is by carborundum VDMOS device The floor polysilicon layer of JFET areas surface deposition one, and then formed Si/SiC hetero-junctions, can be optimized by above-mentioned technological means Application of the VDMOS device in the field of conversion of electrical energy such as inverter circuit, chopper circuit, text specific as follows is described：
(1), relative to directly using the parasitic silicon carbide diodes of VDMOS, because the Si/SiC hetero-junctions is compared to carbonization The parasitic silicon carbide diode of silicon VDMOS device have relatively low conduction voltage drop (Si/SiC hetero-junctions conduction voltage drops are about 1.2V, Carborundum PN junction conduction voltage drop is about 3V) so that Si/SiC hetero-junctions is turned on prior to parasitic diode.This point creates this hair Bright carborundum VDMOS device is in the application such as inverter circuit, chopper circuit, with relatively low power attenuation, faster work speed Degree and higher operating efficiency；Meanwhile, the conduction mode of device of the present invention is in diode applications by parasitic two poles of carborundum The bipolar conduction (conductance modulation) of pipe is changed into many subconductivity, and (present invention is believed that nothing when forming Si/SiC hetero-junctions forward conductions The injection of few son), therefore carborundum VDMOS device of the present invention during inverter circuit, chopper circuit etc. are applied when having Reverse recovery Between short, the characteristics of QRR is few, with good reverse recovery characteristic and fast switching speed.
(2), relative to the application mode of one fast recovery diode (FRD) of inverse parallel outside carborundum VDMOS device, Carborundum VDMOS device of the present invention is directly used in the integrated diode of device inside；Reduced by above-mentioned technological means Device uses number, reduces the line between device, with production cost is low, device reliability is high and system bulk is small Advantage.
(3), the effect relative to carborundum VDMOS device, a kind of carborundum VDMOS device of the invention in itself, passes through Grid width is reduced, gate capacitance is reduced, and the reduction of gate capacitance is conducive to the lifting of device operating rate.
Embodiment 4：
This implementation provides a kind of method for making 1700V carborundum VDMOS devices, it is characterised in that comprise the following steps：
The first step：It is 1 × 10 in doping concentration using epitaxy technique18cm-3~1 × 1019cm-3, thickness be 300 μm~ 500 μm of silicon carbide N+It is 1 × 10 that the upper surface of substrate 9, which makes doping concentration,15cm-3~5 × 1016cm-3, thickness be 15 μm~18 μ M N-Epitaxial layer 8, cellular width is in 10 μm~20 μ ms, as shown in Figure 5；
Second step：After photoetching, using ion implantation technology respectively in N at 200~600 DEG C-Upper strata of epitaxial layer 8 or so two Implanting p-type semiconductor impurities Al ions or B ions are held, it is 1 × 10 to form doping concentration17cm-3~7 × 1017cm-3, injection depth The JFET sector widths being each about between 0.5 μm~1 μm of Liang Ge Pbase areas 7,71, Liang Ge Pbase areas 7,71 are about 3 μm~10 μ M, as shown in Figure 6；
3rd step：After photoetching, distinguished at 200~600 DEG C using ion implantation technology on Liang Ge Pbase areas 7,71 upper stratas Implanting p-type semiconductor impurities Al ions or B ions, it is 1 × 10 to form doping concentration19cm-3~1 × 1020cm-3, injection depth About 0.3 μm~0.5 μm of two P+Contact zone 5,51, as shown in Figure 7；
4th step：After the completion of photoetching, using ion implantation technology respectively in Liang Ge Pbase areas 7,71 at 200~600 DEG C N-type semiconductor impurity P ion or N ions are injected in upper strata, and it is 3 × 10 to form doping concentration19cm-3~1 × 1020cm-3, injection Depth is about 0.3 μm~0.5 μm of two N+Source region 6,61；First P+The N of contact zone 5 and the first+Source region 6 is separate, institute State the 2nd P+The N of contact zone 51 and the 2nd+Source region 61 is separate；After the completion of ion implanting, carried out under 1300~1700 DEG C of high temperature High annealing, as shown in Figure 8；
5th step：It is about 0.02 μm~0.2 μm of gate medium in device surface growth thickness using oxidation or depositing technics Material layer, then gets rid of gate dielectric material layer 0.5~3 μm wide above JFET centre positions, in device using etching technics Part upper surface forms two separate gate dielectric material areas, and etching position forms subsequent technique deposit P+Polysilicon layer 12 Window is as shown in Figure 9；It is 1 × 10 to deposit one layer of doping concentration in device surface17cm-3~5 × 1019cm-3, 0.3 μm~1 μ m-thick P-type polysilicon layer, as shown in Figure 10；Then by etching technics etch away unwanted polysilicon layer and its under gate medium Material layer, two polysilicon gates 2 of acquisition, 21, gate dielectric layer 4,41 and P+Polysilicon layer 12；The P of formation+Polysilicon layer 12 Width be 0.5 μm~3 μm, P+The distance of polysilicon layer 12 and polysilicon gate 2,21 is 0.1 μm~1 μm, polysilicon gate 2,21 With corresponding N+The length that source region 6,61 is contacted is 0.1 μm~0.5 μm, polysilicon gate 2,21 and N-Epitaxial layer 8 contact length be 0.1 μm~3 μm, as shown in figure 11；
6th step：Using Metal deposition and etching technics, in the first P+Contact zone 5 and the N of part the first+The upper table of source region 6 is looked unfamiliar Into the first metal source 3；In the 2nd P+Contact zone 51 and the N of part the 2nd+The upper surface of source region 61 generates the second metal source 31；In P+The upper surface of polysilicon layer 12 formed metal electrode 13, metal electrode 13 by metal lead wire respectively with two source metals Electrode 3,31 is connected；The corresponding generation gate electrode 1,11 on two polysilicon gates 2,21；The device back side is carried out after being thinned to pass through The thickness that deposit forms all metal electrodes 3,31,1,11,13,10 in drain electrode 10, device is about 0.5 μm~6 μm, such as Figure 12 It is shown；Finally prepare symmetrical carborundum VDMOS device.
Embodiment 5：
The present embodiment except in the 5th step by changing layout size, etch away excess polysilicon layer and its under grid During layer of dielectric material so that the P of reservation+The size of multi-crystal silicon area 12 is more than the size that etching gate dielectric material layer forms window, So as in P+The lower section both sides of polysilicon layer 12 are made and N-First medium layer 14 and second dielectric layer 15 that epitaxial layer 8 is directly contacted Beyond the difference of embodiment 4, remaining operation is same as Example 4.
Need statement be：This area work technical staff can be according to this area ABC, and the carbofrax material is also Gallium nitride can be used, the wide-band gap material such as diamond is replaced；The present invention can not only realize N-channel using p-type polysilicon material Element manufacturing, also realizes the making of P-channel device using N-type polycrystalline silicon material；Gate dielectric layer material of the present invention is not limited to two Silica, in addition to：Silicon nitride (Si3N4), hafnium oxide (HfO2), alundum (Al2O3) (Al2O3) contour K dielectric materials.Meanwhile, The embodiment of manufacturing process can also be adjusted according to actual needs.
Embodiments of the invention are set forth above in association with accompanying drawing, but the invention is not limited in above-mentioned specific Embodiment, above-mentioned embodiment is only schematical, rather than restricted, and one of ordinary skill in the art exists Under the enlightenment of the present invention, in the case of present inventive concept and scope of the claimed protection is not departed from, many shapes can be also made Formula, these are belonged within the protection of the present invention.

Claims (9)

1. a kind of carborundum VDMOS device, its structure cell includes：The metal leakage pole (10) that sets gradually from bottom to top, N+Lining Bottom (9) and N-Epitaxial layer (8)；The N-Epitaxial layer (8) upper strata one end has the first Pbase areas (7), the N-On epitaxial layer (8) The floor other end has the 2nd Pbase areas (71)；There is the first separate N in the first Pbase areas (7)+Source region (6) and First P+Contact zone (5)；There is the 2nd separate N in the 2nd Pbase areas (71)+Source region (61) and the 2nd P+Contact Area (51)；First P+Contact zone (5) and the N of part the first+The upper surface of source region (6) has the first metal source (3)；Institute State the 2nd P+Contact zone (51) and the N of part the 2nd+The upper surface of source region (61) has the second metal source (31)；Its feature exists In：Also include and the first Pbase areas (7) upper surface, the first N+ source regions (6) portion of upper surface and N-Epitaxial layer (8) part upper table The first grid structure that face is in contact；The first grid structure includes the first gate dielectric layer (4), positioned at the first gate dielectric layer (4) the first polysilicon gate (2) of upper surface and the first gate electrode (1) positioned at the first polysilicon gate (2) upper surface；Also include with 2nd Pbase areas (71) upper surface, the 2nd N+ source regions (61) portion of upper surface and N-Epitaxial layer (8) portion of upper surface is in contact Second grid structure；The second grid structure includes the second gate dielectric layer (41), positioned at the second gate dielectric layer (41) upper surface The second polysilicon gate (21) and the second gate electrode (11) positioned at the second polysilicon gate (21) upper surface；Also include and the first grid The P of JFET areas upper surface formation Si/SiC hetero-junctions between pole structure and second grid structure+Polysilicon layer (12), it is described P+Polysilicon layer (12) upper surface has metal electrode (13), the P+Polysilicon layer (12) and metal electrode (13) are respectively with One metal source (3) and the second metal source (31) connection；Between each metal structure and P+Polysilicon layer (12) It is mutually isolated by medium with two polysilicon gates (2,21).
2. a kind of carborundum VDMOS device, its structure cell includes：The metal leakage pole that sets gradually from bottom to top, P+Substrate and P-Epitaxial layer；The P-Epitaxial layer upper strata one end has the first Nbase areas, the P-The epitaxial layer upper strata other end has second Nbase areas；There is the first separate P in the first Nbase areas+Source region and the first N+Contact zone；2nd Nbase There is the 2nd separate P in area+Source region and the 2nd N+Contact zone；First N+Contact zone (5) and the P of part the first+Source region Upper surface have the first metal source；2nd N+Contact zone and the P of part the 2nd+The upper surface of source region has the second gold medal Belong to source electrode；It is characterized in that：Also include and the first Nbase areas upper surface, the first P+ region portions upper surface and P-Epitaxial layer The first grid structure that portion of upper surface is in contact；The first grid structure includes the first gate dielectric layer, is situated between positioned at the first grid The first polysilicon gate and the first gate electrode positioned at the first polysilicon gate upper surface of matter layer upper surface；Also include and second Nbase areas upper surface, the 2nd P+ region portions upper surface and P-The second grid structure that epitaxial layer portion upper surface is in contact；Institute Second grid structure is stated including the second gate dielectric layer, the second polysilicon gate positioned at the second gate dielectric layer upper surface and positioned at second Second gate electrode of polysilicon gate upper surface；Also include the JFET areas upper surface between first grid structure and second grid structure Contact forms the N of Si/SiC hetero-junctions+Polysilicon layer, the N+Polysilicon layer upper surface has metal electrode, the N+Polysilicon Layer and metal electrode are connected with the first metal source and the second metal source respectively；Between each metal structure and N+ Polysilicon layer and two polysilicon gates are mutually isolated by medium.
3. a kind of carborundum VDMOS device according to claim 1, it is characterised in that N-Also have in epitaxial layer (8) and divide She Yu not the first Pbase areas (7) lower section and the 2nd Pbase areas (71) lower section and the first P for forming superjunction or half super-junction structure Type silicon carbide region (16) and the second p-type silicon carbide region (161).
4. a kind of carborundum VDMOS device according to claim 2, it is characterised in that P-Also have in epitaxial layer and set respectively Below the first Nbase areas and below the 2nd Nbase areas and formed superjunction or half super-junction structure the first p-type silicon carbide region and Second p-type silicon carbide region.
5. a kind of carborundum VDMOS device according to claim 3 or 4, it is characterised in that P+Polysilicon layer (12) or N+In polysilicon layer also have respectively with N-Epitaxial layer (8) or P-First medium layer (14) and second medium that epitaxial layer is in contact Layer (15).
6. a kind of preparation method of carborundum VDMOS device, it is characterised in that comprise the following steps：
The first step：Using epitaxy technique, in silicon carbide N+N is made in substrate (9) upper surface-Epitaxial layer (8)；
Second step：Using photoetching and ion implantation technology, in N-Epitaxial layer (8) upper strata one end implanting p-type semiconductor impurities formation the One Pbase areas (7), in N-Epitaxial layer (8) upper strata the 2nd Pbase areas (71) of other end implanting p-type semiconductor impurities formation；
3rd step：Using photoetching and ion implantation technology, in the first Pbase areas (7) upper strata implanting p-type semiconductor impurities formation the One P+Contact zone (5), in the 2nd the 2nd P of Pbase areas (71) upper strata implanting p-type semiconductor impurities formation+Contact zone (51)；
4th step：Using photoetching and ion implantation technology, the injection N-type semiconductor impurity formation the on the first Pbase areas (7) upper strata One N+Source region (6), in the 2nd Pbase areas (71) upper strata injection N-type semiconductor impurity the 2nd N+ source regions (61) of formation；Described first P+ contact zones (5) and the first N+ source regions (6) are separate, and the 2nd P+ contact zones (51) and the 2nd N+ source regions (61) are mutually solely It is vertical；Then the impurity injected by high-temperature annealing activation；
5th step：Using deposit or oxidation and etching technics, gate dielectric layer is grown in device upper surface, and etch removal Part gate dielectric layer formation window above JFET areas centre position, then deposits P in device upper surface+Polysilicon layer, etching Excess polysilicon layer and unnecessary gate dielectric layer are removed, the first gate dielectric layer (4), the second gate dielectric layer (41), the first polycrystalline is made Si-gate (2), the second polysilicon gate (21) and P+Polysilicon layer (12), wherein：First gate dielectric layer (4) is in the first Pbase areas (7) Upper surface, and the left and right sides respectively with the first N+Source region (6) portion of upper surface and N-Epitaxial layer (8) portion of upper surface is in contact, First polysilicon gate (2) is in the first gate dielectric layer (4) upper surface, and the second gate dielectric layer (41) is in the 2nd Pbase areas (71) upper table Face, and the left and right sides respectively with the first N+Source region (6) portion of upper surface and N-Epitaxial layer (8) portion of upper surface is in contact, and second Polysilicon gate (21) is in the second gate dielectric layer (41) upper surface, P+Polysilicon layer (12) is located at the first gate dielectric layer (4) and second Between gate dielectric layer (41)；
6th step：Using Metal deposition and etching technics, in the first N+Source region (6) and the first P+Contact zone (5) upper surface generation the One metal source (3)；In the 2nd N+Source region (61) and the 2nd P+Contact zone (51) upper surface generates the second metal source (31)；The first metal gate electrode (1) is generated in the first polysilicon gate (2) upper surface；In the second polysilicon gate (21), upper table is looked unfamiliar Into the second metal gate electrode (11)；By device thinning back side deposit metal formation drain electrode (10)；In P+On multi-crystal silicon area (12) Surface forms metal electrode (13)；Metal electrode (13) respectively with the first metal electrode (3) and the second metal source (31) phase Even；Carborundum VDMOS device is made.
7. a kind of preparation method of carborundum VDMOS device, it is characterised in that the first step：Using epitaxy technique, in silicon carbide N+ N is made in substrate (9) upper surface-Epitaxial layer (8)；
Second step：Using photoetching and ion implantation technology, in N-Epitaxial layer (8) upper strata one end implanting p-type semiconductor impurities formation the One Pbase areas (7), in N-Epitaxial layer (8) upper strata the 2nd Pbase areas (71) of other end implanting p-type semiconductor impurities formation；
3rd step：Using photoetching and ion implantation technology, in the first Pbase areas (7) upper strata implanting p-type semiconductor impurities formation the One P+Contact zone (5), in the 2nd the 2nd P of Pbase areas (71) upper strata implanting p-type semiconductor impurities formation+Contact zone (51)；
4th step：Using photoetching and ion implantation technology, the injection N-type semiconductor impurity formation the on the first Pbase areas (7) upper strata One N+Source region (6), in the 2nd Pbase areas (71) upper strata injection N-type semiconductor impurity the 2nd N+ source regions (61) of formation；Described first P+ contact zones (5) and the first N+ source regions (6) are separate, and the 2nd P+ contact zones (51) and the 2nd N+ source regions (61) are mutually solely It is vertical；Then the impurity injected by high-temperature annealing activation；
5th step：Using deposition and etching technics, gate dielectric layer is grown in device upper surface, etching removes JFET areas centre position The part gate dielectric layer formation window of top, then deposits P in device upper surface+Polysilicon layer, etching removes excess polysilicon Layer and unnecessary gate dielectric layer, be made the first gate dielectric layer (4), the second gate dielectric layer (41), the first polysilicon gate (2), more than second Crystal silicon grid (21), first medium layer (14), second dielectric layer (15) and P+Polysilicon layer (12), wherein：First gate dielectric layer (4) In the first Pbase areas (7) upper surface, and the left and right sides respectively with the first N+Source region (6) portion of upper surface and N-Epitaxial layer (8) Portion of upper surface is in contact, and the first polysilicon gate (2) is in the first gate dielectric layer (4) upper surface, and the second gate dielectric layer (41) is Two Pbase areas (71) upper surfaces, and the left and right sides respectively with the first N+Source region (6) portion of upper surface and N-Epitaxial layer (8) part Upper surface is in contact, and the second polysilicon gate (21) is in the second gate dielectric layer (41) upper surface, P+Polysilicon layer (12) is located at first Between gate dielectric layer (4) and the second gate dielectric layer (41), in P+There is first medium layer (14) and second in polysilicon layer (12) Dielectric layer (15)；
6th step：Using Metal deposition and etching technics, in the first N+Source region (6) and the first P+Contact zone (5) upper surface generation the One metal source (3)；In the 2nd N+Source region (61) and the 2nd P+Contact zone (51) upper surface generates the second metal source (31)；The first metal gate electrode (1) is generated in the first polysilicon gate (2) upper surface；In the second polysilicon gate (21), upper table is looked unfamiliar Into the second metal gate electrode (11)；By device thinning back side deposit metal formation drain electrode (10)；In P+On multi-crystal silicon area (12) Surface forms metal electrode (13)；Metal electrode (13) respectively with the first metal electrode (3) and the second metal source (31) phase Even；Carborundum VDMOS device is made.
8. the preparation method of a kind of carborundum VDMOS device according to claim 6 or 7, it is characterised in that in the 6th step Also include by dielectric deposition and etching technics causing between each metal structure and P before+Multi-crystal silicon area (12) with more than two Isolated between crystal silicon grid (2,21) using medium.
9. the preparation method of a kind of carborundum VDMOS device according to claim 8, it is characterised in that carrying out second Walk also to include before forming Pbase areas：By multistep photoetching and the technique of ion implanting, form super in N- epitaxial layers (8) Level or half super-junction structure.
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