CN114744049A - Silicon carbide MOSFET semiconductor device and manufacturing method - Google Patents
Silicon carbide MOSFET semiconductor device and manufacturing method Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 67
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- 230000005669 field effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
The application relates to a silicon carbide MOSFET semiconductor device and a manufacturing method thereof, which is characterized by comprising the following steps: the semiconductor device comprises a substrate layer, an epitaxial layer, a well region and a first metal layer. The well region comprises a first well region, a second well region and a third well region, a spacer region is arranged between the first well region and the second well region, the first well region and the second well region are of a second conductive type, the spacer region is of a first conductive type with second doping concentration, the first doping concentration is smaller than the second doping concentration, the third well region is of a first conductive type with third doping concentration, and the third well region is arranged on one side of the first well region, which deviates from the spacer region, and one side of the second well region, which deviates from the spacer region. The first metal layer is positioned on the well region, at least covers the spacer region, and ohmic contact is formed between the first metal layer and the spacer region. The embodiment of the application can effectively reduce the reverse conduction voltage drop of the silicon carbide MOSFET transistor, reduce the reverse recovery time of the body diode and simultaneously has lower manufacturing cost.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET semiconductor device and a manufacturing method thereof.
Background
A Semiconductor Field Effect Transistor (MOSFET), particularly a body diode of a silicon carbide MOSFET Transistor, has a problem of high on-state voltage drop when the MOSFET is turned on in the reverse direction due to a high PN junction built-in voltage, and also has a problem of long reverse recovery time. Thus limiting the use of MOSFET body diodes in reverse freewheeling scenarios and the like.
The existing technology solves the above problems by avoiding the use of the body diode through an additional reverse parallel silicon-based fast recovery diode or a silicon carbide schottky diode, or by introducing an additional schottky metal process, an integrated schottky diode is embedded inside a cell of the MOSFET device, thereby shielding the use of the PN junction body diode.
However, the above method increases the number of chips used or increases the cost of the chip manufacturing process.
Disclosure of Invention
The embodiment of the application provides a silicon carbide MOSFET semiconductor device, a body diode of which can provide lower reverse conduction voltage drop, has shorter reverse recovery time and simultaneously has lower manufacturing cost.
In one aspect, a silicon carbide MOSFET semiconductor device is provided according to an embodiment of the present application, including: a substrate layer; the epitaxial layer is arranged on the substrate layer and comprises a first surface far away from the substrate layer, and the epitaxial layer is of a first conductivity type with a first doping concentration. The epitaxial layer is arranged on the first surface of the epitaxial layer, the epitaxial layer is arranged on the second surface of the epitaxial layer, the first well region and the second well region are arranged in the epitaxial layer, the epitaxial layer is arranged on the second surface of the epitaxial layer, the epitaxial layer is arranged on the first surface of the epitaxial layer, the epitaxial layer is arranged on the second surface of the epitaxial layer, the first well region and the second well region are arranged in the epitaxial layer, and the epitaxial layer is arranged on the epitaxial layer; the first metal layer is positioned on the well region, the first metal layer at least covers the spacer region, and ohmic contact is formed between the first metal layer and the spacer region.
According to an aspect of the embodiments of the present application, the epitaxial layer further includes a trench having a first surface recessed along a thickness of the epitaxial layer, and the first well region and the second well region are disposed inwardly of the epitaxial layer from a bottom wall and sidewalls of the trench.
According to an aspect of an embodiment of the application, the first electrode layer extends at least partially into the trench.
According to an aspect of the embodiment of the present application, the well region further includes a fourth well region, the fourth well region is of the second conductivity type, and the fourth well region is disposed between the epitaxial layer and the third well region and supports the third well region.
According to an aspect of an embodiment of the application, the third doping concentration is greater than the second doping concentration.
According to one aspect of the embodiments of the present application, the trench sidewall is provided with a second metal layer, and an ohmic contact is formed between the second metal layer and the third well region.
According to an aspect of the embodiment of the present application, the semiconductor device further includes a third metal layer, the third metal layer is located on the well region, the third metal layer is overlapped with at least a portion of the third well region on the orthographic projection of the first surface, and is overlapped with the first well region and the second well region, and the third metal layer is abutted against at least one of the first well region, the second well region and the third well region to form an ohmic contact.
According to an aspect of the embodiment of the present application, the epitaxial layer further includes a blocking portion, the first well region and the second well region are disposed at an interval along a thickness direction of the epitaxial layer, and at least a portion of the blocking portion coincides with the spacer region on an orthogonal projection of the first surface, and the blocking portion is of the second conductivity type.
In another aspect, a method for fabricating a silicon carbide MOSFET semiconductor device is provided according to an embodiment of the present application, including: a substrate layer is provided. An epitaxial layer is formed on the substrate layer, the epitaxial layer including a first surface remote from the substrate layer, the epitaxial layer being of a first conductivity type having a first doping concentration. And doping a second conductive type material to the preset region of the epitaxial layer on the first surface to form a well region, wherein the well region comprises a first well region and a second well region. A spacer region having a second doping concentration is formed between the first well region and the second well region by doping the epitaxial layer with a first conductive type material from the first surface, the first doping concentration being less than the second doping concentration. And doping the first conductive type material on the side of the first well region, which faces away from the spacer region, and the side of the second well region, which faces away from the spacer region to form a third well region with a third doping concentration. Providing a metal material, and forming a first metal layer on the well region, wherein the first metal layer at least covers the spacer region.
According to another aspect of the embodiments of the present application, the step of doping the predetermined region of the epitaxial layer with the second conductive type material at the first surface to form the well region includes: the first surface is a plane, and a preset area is selected on the first surface for doping. Or forming a groove along the thickness of the epitaxial layer in a concave mode to form a concave-convex first surface, and doping a second conductive type material into the epitaxial layer along the first surface corresponding to the bottom and the side portion of the groove to form a well region.
According to the silicon carbide MOSFET semiconductor device of the embodiment of the application, the first well region and the second well region are separated by the spacer region with a preset distance, and the distance is generally short, so that a pinch-off barrier is easily formed. When the silicon carbide MOSFET semiconductor device is in forward blocking, the first well region and the second well region have shorter spacing distance, and the expanded depletion region further raises the Pinch-off potential barrier to form a Pinch-off effect (Pinch-off), so that no leakage current is formed in a channel of the spacing region. When the silicon carbide MOSFET semiconductor device is reversely conducted, when the source-drain voltage exceeds the pinch-off barrier, the spacer channel is opened, the reverse current of the silicon carbide MOSFET semiconductor device flows through the channel, and the pinch-off barrier is far lower than the built-in potential difference of a silicon carbide PN junction, so that the reverse current preferentially flows through the spacer channel, the conduction voltage drop is lower, the reverse current is mainly unipolar carriers, and almost no reverse recovery time exists when the silicon carbide MOSFET semiconductor device is turned off.
Drawings
Features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic structural view of a silicon carbide MOSFET semiconductor device provided in an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view taken along line A-A of FIG. 1;
fig. 3 is a schematic view of another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application;
fig. 4 is a graph of the underlying ampere characteristic at forward voltage for the silicon carbide MOSFET semiconductor device of fig. 1;
fig. 5 is a graph of the underlying ampere characteristic of the silicon carbide MOSFET semiconductor device of fig. 1 at reverse voltage;
fig. 6 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view taken along line B-B of FIG. 6;
fig. 8 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application;
fig. 9 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application;
fig. 10 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application;
fig. 11 is a schematic flow chart illustrating a method of manufacturing a silicon carbide MOSFET semiconductor device according to an embodiment of the present application;
fig. 12 to 17 are schematic cross-sectional structures of the silicon carbide MOSFET semiconductor device according to the embodiment of the present application at stages in the manufacturing process;
fig. 18 is a schematic block flow chart diagram illustrating a method of fabricating yet another silicon carbide MOSFET semiconductor device in accordance with an embodiment of the present application;
fig. 19 is a schematic cross-sectional structure view of a further silicon carbide MOSFET semiconductor device of an embodiment of the present application at a corresponding stage in its method of fabrication;
reference numerals:
1. a substrate layer;
2. an epitaxial layer; 21. a first surface; 22. a trench; 23. a blocking portion;
3. a well region; 31. a first well region; 32. a second well region; 33. a spacer region; 34. a third well region; 35. a fourth well region; 36. a contact region;
4. a first metal layer;
5. a first electrode layer;
6. a gate electrode; 61. a gate insulating layer;
7. a second metal layer;
8. a third metal layer;
x, a first direction.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The following description will be given with the directional terms as they are shown in the drawings, and will not limit the specific structure of the silicon carbide MOSFET semiconductor device and the method for manufacturing the silicon carbide MOSFET semiconductor device of the present application. In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be directly connected or indirectly connected. The specific meaning of the above terms in the present application can be understood as appropriate by one of ordinary skill in the art.
The silicon carbide MOSFET Semiconductor device according to the embodiment of the present application may be a silicon carbide Semiconductor Field Effect Transistor (SiC MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or the like, and hereinafter, the Semiconductor device will be mainly described by taking a structure of the SiC MOSFET as an example. It is to be understood that the silicon carbide MOSFET semiconductor device of the embodiment of the present application may also be various types of semiconductor devices of other structures similar to the SiC MOSFET.
For a better understanding of the present application, a semiconductor device according to an embodiment of the present application is described in detail below with reference to fig. 1 to 19.
Fig. 1 is a schematic structural diagram of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. Fig. 2 is a schematic sectional view taken along the line a-a in fig. 1. Fig. 3 is a schematic view of another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. Fig. 4 is a graph of the underlying ampere characteristic at forward voltage for the silicon carbide MOSFET semiconductor device shown in fig. 1. Fig. 5 is a graph of the underlying ampere characteristic of the silicon carbide MOSFET semiconductor device of fig. 1 at reverse voltage.
A silicon carbide MOSFET semiconductor device, of which a schematic view of at least one cell (pitch) structure is shown in fig. 1, may include an active region and a termination region surrounding at least a portion of a periphery of the active region.
Herein, the cell structure refers to the smallest repeating unit of the conductive structure of the active region of the silicon carbide MOSFET semiconductor device. The structural schematic diagram in the application is a schematic diagram on the structural principle, and the actual size, the detail position and the like of each part contained in the power device can be adjusted according to the actual situation.
The silicon carbide MOSFET semiconductor device provided by the embodiment of the application comprises a substrate layer 1, an epitaxial layer 2, a well region and a first metal layer 4, wherein the substrate layer 1 and the epitaxial layer 2 are arranged in a stacked mode. The epitaxial layer 2 covers the substrate layer 1. The epitaxial layer 2 comprises a first surface 21 remote from the substrate layer 1, the epitaxial layer 2 being of a first conductivity type having a first doping concentration. Well region 3 extends the setting to epitaxial layer 2 by first surface 21, and well region 3 includes first well region 31, second well region 32 and third well region 34, sets up interval 33 between first well region 31 and the second well region 32, and first well region 31 and second well region 32 are the second conductivity type, and interval 33 is the first conductivity type who has the second doping concentration, and first doping concentration is less than the second doping concentration. The third well region 34 is of the first conductivity type with a third doping concentration, the third well region 34 being arranged on a side of the first well region 31 facing away from the spacer 33 and on a side of the second well region 32 facing away from the spacer 33. The first metal layer 4 is located on the well region, and the first metal layer 4 at least covers the spacer region on the orthographic projection of the first surface. An ohmic contact is formed between the first metal layer 4 and the spacer.
The epitaxial layer 2 may refer to one epitaxial layer 2 or a plurality of epitaxial layers. For example, the epitaxial layer 2 may be formed of one or more semiconductor materials such as silicon carbide (SiC). In more detail, the epitaxial layer 2 may include at least one silicon carbide epitaxial layer 2. Silicon carbide may have a wider band gap than silicon and thus may maintain stability even at high temperatures compared to silicon. In addition, since the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can stably operate even at high temperatures.
The epitaxial layer 2 may include a spacer 33. The spacer region 33 may have a first conductive type, and may be formed by implanting an impurity of the first conductive type into a portion of the semiconductor layer. For example, the spacer 33 may be formed by doping an impurity of the first conductivity type in the epitaxial layer 2 of silicon carbide. Alternatively, as shown in fig. 3, the doping concentration of the contact region 36 of the first metal layer 4 in contact with the spacer region 33 may be greater than the doping concentration of the remaining region of the spacer region 33 facing away from the contact region 36, and the high doping of the contact region 36 is more favorable for forming an ohmic contact with the first metal layer 4.
The well region may be formed in epitaxial layer 2 so as to be at least partially distributed in contact with spacer region 33 and may have the second conductivity type. The well region may be formed, for example, by doping impurities of a second conductivity type opposite to the first conductivity type in the epitaxial layer 2.
In some optional examples, as shown in fig. 2, the silicon carbide MOSFET semiconductor device may further include a gate insulating layer 61 and a gate electrode 6 disposed on the epitaxial layer 2, and in a specific implementation, one cell structure of the silicon carbide MOSFET semiconductor device includes the gate insulating layer 61, the gate electrode 6 and the well region 3.
The first well region 31 and the second well region 32 in the well region 3 are of the second conductivity type, and the spacing between the first well region 31 and the second well region 32 is the distance of the spacer region 33 in the first direction X. The second conductivity type is a P-type conductivity type. The spacer 33 is a second doping concentration region, i.e., N-type conductivity. Since the doping concentration of the spacer region 33 is higher than that of other regions of the epitaxial layer 2, and the spacing between the first well region 31 and the second well region 32 is at a predetermined value, the spacer region 33 between the first well region 31 and the second well region 32 can be made to form a pinch-off barrier. It is understood that one of the first conductive type and the second conductive type is an N-type conductive type and the other is a P-type conductive type. In the embodiment of the present application, the first conductive type is an N-type conductive type, and the second conductive type is a P-type conductive type.
It should be noted that the distance between the first well region 31 and the second well region 32 is determined by the depth of the first well region 31 and the second well region 32 in the thickness direction of the epitaxial layer 2 and the doping concentration of the spacer region 33, as shown in fig. 3 and 4, in the embodiment of the present invention, the extending depth of the first well region 31 and the second well region 32 in the epitaxial layer 2 is 2um, and the doping concentration of the spacer region 33 is 1 × 1016 cm-3-5×1017 cm-3The silicon carbide MOSFET semiconductor device is explained as an example. It is to be understood that the depth of the well region 3 of the silicon carbide MOSFET semiconductor device, the doping concentration of the spacer region 33, and the distance between the first well region 31 and the second well region 32 are not particularly limited in the embodiments of the present application.
Fig. 4 is a graph of the underlying ampere characteristic at forward voltage for the silicon carbide MOSFET semiconductor device of fig. 1. Fig. 5 is a graph of the underlying ampere characteristic of the silicon carbide MOSFET semiconductor device of fig. 1 at reverse voltage. In fig. 4, the ordinate represents the current in amperes, the abscissa represents the voltage in volts, the curve M1 is the forward voltage underlying ampere characteristic curve of a silicon carbide MOSFET having a first well region 31 and a second well region 32 spaced apart by 0.4um, the curve M2 is the forward voltage underlying ampere characteristic curve of a silicon carbide MOSFET having a first well region 31 and a second well region 32 spaced apart by 0.5um, the curve M3 is the forward voltage underlying ampere characteristic curve of a silicon carbide MOSFET having a first well region 31 and a second well region 32 spaced apart by 0.6um, and the curve N1 is the forward voltage underlying ampere characteristic curve of a silicon carbide MOSFET having a first well region 31 and a second well region 32 spaced apart by 0 um.
As shown in fig. 4, since the spacer 33 has the blocking barrier, when the distance between the first well region 31 and the second well region 32 is within a reasonable range, the spacer 33 also has a higher blocking voltage capability when the sic MOSFET semiconductor device blocks forward, as shown by the curve M1 and the curve M2. However, when the predetermined distance between the first well region 31 and the second well region 32 is greater than the threshold value, the spacer region 33 has no significant voltage blocking capability, as shown by the curve M3. Therefore, the depth parameters of the first well region 31 and the second well region 32 are 2um, and the doping concentration of the spacer region 33 is 1 × 1016 cm-3-5×1017 cm-3And when the distance between the first well region 31 and the second well region 32 is less than 0.5um, the spacer region 33 may have a voltage blocking capability.
As shown in fig. 5, when the sic MOSFET semiconductor device is turned on in the reverse direction, and the distance between the first well region 31 and the second well region 32 is within a reasonable range, the source-drain current preferentially passes through the spacer region 33, as shown by a curve M1, a curve M2, and a curve M3, but as the preset distance between the first well region 31 and the second well region 32 decreases, the on-current capability of the spacer region 33 gradually decreases, and when the preset distance between the first well region 31 and the second well region 32 is 0, the reverse current of the sic MOSFET semiconductor device is completely turned on by the PN junction diode, and within a certain range, the on-voltage drop is also the largest, as shown by a curve N1.
Referring to fig. 4 and 5, the depth parameters of the first well 31 and the second well 32 are set to 2um, and the doping concentration of the spacer 33 is set to 1 × 1016 cm-3-5×1017 cm-3When the value of the spacing layer is 0.5um, the silicon carbide MOSFET semiconductor device has obviously lower conduction voltage drop under a reverse conduction working mode, and under the condition that reverse conduction current is less than 60A, a PN junction diode in the MOSFET cannot be started, and minority carrier injection effect cannot be triggered, so that the silicon carbide MOSFET semiconductor device has the advantages that the silicon carbide MOSFET semiconductor device has obviously lower conduction voltage drop, and the reverse conduction current is smaller than 60AThe transition time of the bulk device from reverse conduction to the blocking state is shorter. On the other hand, the silicon carbide MOSFET semiconductor device still has qualified forward blocking voltage capability.
Fig. 6 is a schematic view of another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. Fig. 7 is a schematic sectional view taken along the direction B-B in fig. 6. Fig. 8 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application.
As shown in fig. 6 and 7, in some alternative embodiments, the epitaxial layer 2 further includes trenches 22 with the first surface 21 recessed along the thickness of the epitaxial layer 2, and the well regions 3 are disposed from the bottom and sidewalls of the trenches 22 extending into the epitaxial layer 2. The grooves 22 may extend in a polygonal shape on the first surface 21.
In the embodiment of the present application, a groove formed on the first surface 21 and penetrating through the first surface 21 along the first direction X is taken as an example for illustration, and in some other embodiments, the groove 22 may extend on the first surface 21 in other polygons, such as a square, a pentagon, and a hexagon.
In some alternative embodiments, as shown in fig. 7, the first electrode layer 5 is disposed to cover the trench 22, and optionally, a part of the film layer in the first electrode layer 5 may extend into the trench 22. Alternatively, as shown in fig. 8, in a Trench silicon carbide Semiconductor Field Effect Transistor (SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor, SiC Trench MOSFET), there is a cell structure in a dashed box. The separation of the second conductivity type in the well region 3 in the prior art into the first well region 31 and the second well region 32 and the spacer region 33 also serves to rectify and reduce the reverse recovery time. In the well region 3, the first metal layer 4 disposed above the spacer region 33 forms an ohmic contact with the spacer region 33.
In some alternative embodiments, with continued reference to fig. 6 and 7, the second metal layer 7 is disposed on the sidewall of the trench 22, and an ohmic contact is formed between the second metal layer 7 and the third well region 34. The third well region 34 is disposed around the trench 22 and does not overlap the first metal layer 4 in the region of the trench 22 on the orthographic projection of the first surface 21, so that the ohmic contact regions of the third well region 34 and the second metal layer 7 are on the side walls of the trench 22, and the ohmic contact of the third well region 34 disposed on the first surface 21 is not needed, thereby shortening the size of the cellular structure on the first surface 21. It will be appreciated that the second metal layer 7 may also cover the areas of the first well regions 31 and the second well regions 32 in the trenches 22 and on the first surface 21 during the manufacturing process. The second metal layer 7 covering in these areas forms equipotential contacts with the first well region 31 and the second well region 32.
In some alternative embodiments, with continuing reference to fig. 6 and 7, it is understood that a fourth well region 35 may be further disposed in the well region 3 to connect the first well region 31 and the second well region 32, and the doping concentration of the fourth well region 35 is a second conductivity type lower than the doping concentrations of the first well region 31 and the second well region 32. The fourth well region 35 can be formed by injecting together with the first well region 31 and the second well region 32, the fourth well region 35 can also be formed by injecting alone, and the fourth well region can have more contact areas with the third well region after being formed, so that the formation of a PN junction is easier.
In some alternative embodiments, the third doping concentration is greater than the second doping concentration. It will be appreciated that the third well region and the first and second well regions require sufficient contact areas to allow the diffusion and drift motions to reach a dynamic equilibrium in the contact area of the third well region 34 and the first and second well regions 31 and 32, thereby creating a PN junction in this contact area.
Fig. 9 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. In some alternative embodiments, as shown in fig. 9, the third metal layer 8 is located on the well region 3, and the third metal layer 8 coincides with at least a portion of the third well region 34, and coincides with the first well region 31 and the second well region 32 in an orthographic projection of the first surface 21. The third metal layer 8 forms an ohmic contact with the contact surfaces of the first well region 31, the second well region 32, and the third well region 34. Specifically, when the trench 22 structure is not provided, the third metal layer 8 overlaps with partial regions of the first well region 31, the second well region 32, and the third well region 34 on the orthographic projection of the first surface 21, and the third metal layer 8 is provided on the overlapping region of the first surface, and can form ohmic contact with contact surfaces of the first well region 31, the second well region 32, and the third well region 34. It should be noted that the region where the ohmic contact can be formed includes, but is not limited to, the above-mentioned position. The materials used for the first metal layer 4, the second metal layer 7 and the third metal layer 8 may be the same metal. Optionally, one or more of the first metal layer 4, the second metal layer 7, and the third metal layer 8 may be simultaneously formed in one process, and the formed one or more of the first metal layer 4, the second metal layer 7, and the third metal layer 8 may form an ohmic contact with the contact region of the well region 3. The first electrode layer 5 and the first metal layer 4, the second metal layer 7 and the third metal layer 8 may be short-circuited.
Fig. 10 is a schematic view of still another structure of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. In some alternative embodiments, as shown in fig. 10, the epitaxial layer 2 further includes a barrier portion 23, the barrier portion 23 and the first well region 31 and the second well region 32 are spaced apart from each other in a thickness direction of the epitaxial layer 2, and the barrier portion 23 at least partially coincides with the spacer 33 on an orthogonal projection of the first surface 21, and the barrier portion 23 is of the second conductivity type. Note that the barrier portion 23 is located below the first well region 31, the second well region 32, and the spacer region 33 in the thickness direction of the epitaxial layer 2, and is spaced apart from the first well region 31, the second well region 32, and the spacer region 33. The blocking portion 23 can block the spacer 33 to a certain extent, so that the preset size of the spacer 33 in the first direction X can be increased, the requirement on the precision of the lithography apparatus is reduced, or the depths of the first well region 31 and the second well region 32 are reduced, the energy requirement on the ion implantation apparatus is reduced, and the manufacturing difficulty and cost are reduced.
Embodiments of the present invention further provide a method for manufacturing a silicon carbide MOSFET semiconductor device, which is applied to a process for forming the silicon carbide MOSFET semiconductor device according to the above embodiments of the present invention, and the method for manufacturing the silicon carbide MOSFET semiconductor device will be described below with several embodiments.
Fig. 11 is a schematic flow chart illustrating a method of manufacturing a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. Fig. 12 to 17 are schematic cross-sectional structure diagrams corresponding to respective stages of a method for manufacturing a silicon carbide MOSFET semiconductor device according to an embodiment of the present application. The manufacturing method comprises the following steps:
and S100, providing a SiC substrate layer.
S200, forming an epitaxial layer 2 on the substrate layer 1, where the epitaxial layer 2 includes a first surface 21 far from the substrate layer 1, and the epitaxial layer 2 is of a first conductivity type having a first doping concentration.
As shown in fig. 12, in steps S100 to S200, the first conductivity type is, for example, N type, and the epitaxial layer 2 is, for example, N type layer with a first doping concentration. The epitaxial layer 2 may be an epitaxial wafer of the first conductivity type with sufficient thickness, for example silicon carbide, and in other embodiments may also be a wafer with a field stop layer. The thickness of the epitaxial layer 2 is determined by the withstand voltage value of the device design.
S300, doping a second conductive type material on the first surface 21 toward a predetermined region of the epitaxial layer 2 to form a well region 3, where the well region 3 includes a first well region 31 and a second well region 32.
As shown in fig. 13, in step S300, the second conductivity type is, for example, P type, and ions of the second conductivity type are implanted into the epitaxial layer 2 at the first surface 21 of the epitaxial layer 2 by an ion implantation apparatus, so as to form the first well region 31 and the second well region 32. When the silicon carbide epitaxial wafer is used for ion implantation, the diffusion movement of ions can be ignored, and ions with preset doping concentration can be implanted into the preset area.
S400, doping the epitaxial layer 2 with a first conductivity type material from the first surface 21 between the first well region 31 and the second well region 32 to form a spacer region 33 having a second doping concentration, the first doping concentration being smaller than the second doping concentration.
As shown in fig. 14, in step S400, ions of the first conductivity type are implanted into the epitaxial layer 2 at the first surface 21 of the epitaxial layer 2 by an ion implantation apparatus, so that the doping concentration of the first conductivity type in the region between the first well region 31 and the second well region 32 is greater than that of the region of the epitaxial layer 2. Note that the spacer region 33 has a pinch-off barrier within a predetermined distance between the first well region 31 and the second well region 32.
S500, doping the first conductive type material at a side of the first well region 31 facing away from the spacer 33 and a side of the second well region 32 facing away from the spacer 33 forms a third well region 34 having a third doping concentration. As shown in fig. 15 and 16, the third well region 34 forms PN junctions with contact regions of the first well region 31 and the second well region 32, respectively. Alternatively, as shown in fig. 15, before the third well region 34 is formed by doping the first conductive type material, the fourth well region 35 may be formed by doping the second conductive type material. The fourth well region 35, the first well region 31 and the second well region 32 are manufactured together, and process steps are reduced. Forming the third well region 34 in the fourth well region 35 can compensate for the situation that the contact area between the first well region 31 and the third well region 34 is too small, and form a surface channel on the side away from the first well region 31 and the second well region 32. Or the fourth well region 35 can be separately fabricated before or after the first well region 31 and the second well region 32 are fabricated, so as to reduce the implantation dose in the channel surface region.
S600, providing a metal material, and forming a first metal layer 4 on the well region, wherein the first metal layer 4 covers at least the spacer 33. As shown in fig. 17, in step S500, the first metal layer 4 covers the spacer region 33 so that an ohmic contact is formed between the spacer region 33 and the first metal layer 4.
Fig. 18 is a schematic block flow chart illustrating a method of fabricating a further silicon carbide MOSFET semiconductor device in accordance with an embodiment of the present application. Fig. 19 is a schematic cross-sectional structure view of a silicon carbide MOSFET semiconductor device according to an embodiment of the present application at a corresponding stage in its fabrication method. In some embodiments, referring to fig. 18 and 19, in step S300, the method includes:
s301, the first surface is a plane, and a preset area is selected on the first surface to be doped. As shown in fig. 15, the well region may be formed directly on the first surface.
S302, or forming a groove along the thickness of the epitaxial layer in a concave mode to form a concave-convex first surface, and doping a second conductive type material into the epitaxial layer along the first surface corresponding to the bottom and the side area of the groove to form a well region.
As shown in fig. 18 and 19, in step S301, the trench 22 may be defined by using a mask layer, and the trench 22 may be formed by using an etching process. The plurality of grooves 22 are formed in one step, and the one-step forming means that a mask process is adopted. In particular, dry etching may be used. During fabrication, an ion implantation of the second conductivity type may be performed through the trench 22, thereby forming well regions 3 on the sidewalls and bottom walls of the trench 22. It will be appreciated that there may also be gates, gate insulators, sources, etc. in silicon carbide MOSFET semiconductor devices on the epitaxial layer. It should be noted that step S301 and step S302 are not in order in the actual manufacturing process. While the application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. The present application is not intended to be limited to the particular embodiments disclosed herein but is to cover all embodiments that may fall within the scope of the appended claims.
Claims (10)
1. A silicon carbide MOSFET semiconductor device, comprising:
a substrate layer;
the epitaxial layer is arranged on the substrate layer and comprises a first surface far away from the substrate layer, and the epitaxial layer is of a first conductivity type with a first doping concentration;
the epitaxial layer is provided with a first surface, the first surface extends into the epitaxial layer, the first surface is provided with a first well region, the second surface extends into the epitaxial layer, the first well region and the second well region are provided with a second conductive type, the spacer region is a first conductive type with a second doping concentration, the first doping concentration is smaller than the second doping concentration, the third well region is a first conductive type with a third doping concentration, and the third well region is arranged on one side of the first well region, which is far away from the spacer region, and one side of the second well region, which is far away from the spacer region;
the first metal layer is positioned on the well region, the first metal layer at least covers the spacer region, and ohmic contact is formed between the first metal layer and the spacer region.
2. The silicon carbide MOSFET semiconductor device of claim 1, wherein the epitaxial layer further comprises a trench having the first surface recessed along a thickness of the epitaxial layer, the first and second well regions extending inwardly of the epitaxial layer from the trench bottom and sidewalls.
3. The silicon carbide MOSFET semiconductor device of claim 2, further comprising a first electrode layer extending at least partially into the trench.
4. The silicon carbide MOSFET semiconductor device of claim 3, wherein the trench sidewalls are provided with a second metal layer, the second metal layer forming an ohmic contact with the third well region.
5. The silicon carbide MOSFET semiconductor device of claim 1, wherein the well region further comprises a fourth well region of the second conductivity type disposed between the epitaxial layer and the third well region and carrying the third well region.
6. The silicon carbide MOSFET semiconductor device of claim 1, wherein the third doping concentration is greater than the second doping concentration.
7. The silicon carbide MOSFET semiconductor device of claim 1, further comprising a third metal layer on the well region, the third metal layer coinciding, in orthographic projection of the first surface, with at least a portion of the third well region and with the first and second well regions, the third metal layer forming an ohmic contact against at least one of the first and second and third well regions.
8. The silicon carbide MOSFET semiconductor device of claim 1, wherein the epitaxial layer further comprises a barrier portion, the barrier portion and the first and second well regions are spaced apart along a thickness direction of the epitaxial layer, and the barrier portion at least partially overlaps the spacer region in an orthographic projection of the first surface, the barrier portion being of the second conductivity type.
9. A method for manufacturing a silicon carbide MOSFET semiconductor device is characterized by comprising the following steps:
providing a substrate layer;
forming an epitaxial layer on the substrate layer, wherein the epitaxial layer comprises a first surface far away from the substrate layer, and the epitaxial layer is of a first conductivity type with a first doping concentration;
doping a second conductive type material to a preset area of the epitaxial layer on the first surface to form a well region, wherein the well region comprises a first well region and a second well region;
doping a first conductive type material from the first surface to the epitaxial layer between the first well region and the second well region to form a spacer region having a second doping concentration, wherein the first doping concentration is smaller than the second doping concentration;
doping a first conductive type material on one side of the first well region, which faces away from the spacer region, and one side of the second well region, which faces away from the spacer region, to form a third well region with a third doping concentration;
providing a metal material, and forming a first metal layer on the well region, wherein the first metal layer at least covers the spacer region.
10. The method of fabricating a silicon carbide MOSFET semiconductor device according to claim 9, wherein the step of doping the predetermined region of the epitaxial layer with the second conductivity type material to form the well region from the first surface comprises:
the method comprises the following steps that a first surface is a plane, and a preset area is selected on the first surface to be doped; alternatively, the first and second electrodes may be,
and forming a groove along the thickness of the epitaxial layer in a concave mode to form a concave-convex first surface, and doping the second conductive type material into the epitaxial layer along the first surface corresponding to the bottom and side regions of the groove to form a well region.
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| CN117059672A (en) * | 2023-10-11 | 2023-11-14 | 通威微电子有限公司 | Semiconductor device integrated with SBD and manufacturing method thereof |
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