KR100718775B1 - Image sensor and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide an image sensor and a method of manufacturing the same that can suppress the generation of a dark signal and improve the photocharge transmission efficiency, the present invention for this purpose is a second conductive formed first diffusion region of the first conductivity type A substrate, a transistor gate electrode formed on the substrate to be aligned with one side of the first diffusion region, a spacer formed on both sidewalls of the transistor gate electrode, and a depth in a region corresponding to the spacer. It provides an image sensor including a second diffusion region of the second conductivity type formed on the surface of the first diffusion region to be shallower than the depth in the region exposed to one side of the spacer.

 Image sensor, pinned photodiode, photoelectric transport efficiency, dark signal, P0 diffusion area.

Description

Image sensor and manufacturing method thereof {IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing an image sensor having a typical pinned photodiode.

2 is a cross-sectional view showing an image sensor having a pinned photodiode according to Embodiment 1 of the present invention.

3 is a cross-sectional view showing an image sensor having a pinned photodiode according to Embodiment 2 of the present invention.

4A to 4D are cross-sectional views illustrating a method of manufacturing an image sensor according to Embodiment 2 of the present invention shown in FIG.

<Description of the symbols for the main parts of the drawings>

20: substrate

21: gate insulating film

22: gate conductive film

23: gate electrode for transistor

24, 33: buffer oxide film

25: N ^- diffusion region

26, 34: mask pattern

27, 35: ion implantation process

28, 28a: P ⁰ diffusion region

29: nitride film

30: etching process

31: spacer

The present invention relates to an image sensor and a method for manufacturing the same, and more particularly, to an image sensor having a pinned photodiode and a method for manufacturing the same.

As is well known, a pinned photodiode is used as a device for generating and accumulating photocharges by sensing light from the outside in a charge coupled device (CCD) image sensor or a CMOS image sensor. It has a PNP (or NPN) junction structure and is also called a buried photodiode.

Such a pinned photodiode has several advantages over other photodiodes such as a source / drain PN junction structure or a MOS capacitor structure, and one of them can increase the depth of the depletion layer. The ability to convert incident photons to electrons is excellent (High Quantum Efficiency). That is, in the pinned photodiode of the PNP junction structure, since the depletion layer is formed by two P regions interposed between the N regions while the N region is completely depleted, the depth of the depletion layer may be increased to increase the "Quantum Efficiency". As a result, the light sensitivity is excellent.

1 is a cross-sectional view illustrating an image sensor having a general pinned photo diode. Referring to FIG. 1, a conventional image sensor includes a P-type substrate 10 having a P-type epi layer (P_epi, not shown), a gate electrode 13 for a transistor formed in a portion of the epi layer, and a transistor. The low concentration N-type (N ⁻ ) diffusion region 15 formed in the epitaxial layer exposed to one side of the gate electrode 13, the spacer 16 formed on both side walls of the gate electrode 13, and the spacer 16. It includes a P ⁰ diffusion region 17 formed on the surface of the N ^- diffusion region 15 exposed to one side of the. Preferably, the gate electrode 13 for a transistor is to function as a transfer transistor, and consists of the gate insulating film 11 and the gate conductive film 12. As shown in FIG.

Here, an image sensor having a PNP type pinned photodiode composed of a P-type epi layer (not shown) / N ^- diffusion region 15 / P ⁰ diffusion region 17 is shown. At this time, P ⁰ diffusion region 17 N ^- diffusion region 15, the surface is depleted (Depletion) prevent and N ^- diffusion region 15 capture (Capture), the surface excess electron (Extra electron) are P-type to be It prevents the generation of dark signal caused by moving to the epi layer.

As such, the P ⁰ diffusion region 17 is closely related to the dark signal and the photoelectric transfer efficiency of the image sensor. For example, if the depth of the P ⁰ diffusion region 17 is increased, it is possible to effectively suppress the dark signal generation, but there is a problem in that the photocharge transmission efficiency is lowered, whereas if the depth of the P ⁰ diffusion region 17 is decreased, the photocharge Although transmission efficiency may be improved, there is a problem in that dark signal generation is increased. That is, in the impurity ion implantation process for forming the P ⁰ diffusion region 17, when the impurity ions having a high doping concentration are implanted with high energy, the photocharge transfer efficiency may be deteriorated, thereby forming the P ⁰ diffusion region 17. In the impurity ion implantation process, when impurity ions of low doping concentration are implanted with low energy, a dark signal generation is increased.

Accordingly, an object of the present invention is to provide an image sensor and a method of manufacturing the same, which are designed to solve the above problems of the prior art and can improve photoelectric charge transfer efficiency while suppressing dark signal generation.

According to an aspect of the present invention, there is provided a substrate of a second conductivity type in which a first diffusion region of a first conductivity type is formed; A gate electrode for a transistor formed on the substrate to be aligned with one side of the first diffusion region; Spacers formed on both sidewalls of the transistor gate electrode; And a region formed to be aligned with the gate electrode on an upper surface of the first diffusion region, wherein a region exposed to one side of the spacer is higher than the region corresponding to the spacer, having a higher doping concentration, and having a higher depth and a lower upper surface. It provides an image sensor including a second diffusion region of the second conductivity type formed to have.

In addition, the present invention according to another aspect for achieving the above object, forming a gate electrode for the transistor on the substrate of the first conductivity type; Forming a first diffusion region of a second conductivity type in an exposed portion of the substrate to be aligned with one side of the transistor gate electrode; Forming a second diffusion region of a first conductivity type on an upper surface of the first diffusion region to be aligned with one side of the transistor gate electrode; Forming spacers on both sidewalls of the transistor gate electrode; Forming a third diffusion region of the first conductivity type deeper than the second diffusion region in the first and second diffusion regions exposed to one side of the spacer; And etching the second diffusion region exposed to one side of the spacer to a predetermined depth.

According to the present invention, the surface of the first diffusion region of the first conductivity type formed in the substrate such that the depth in the region corresponding to the spacer formed on both side walls of the transistor gate electrode is smaller than the depth in the region exposed to one side of the spacer. By forming the second diffusion region of the second conductivity type in the upper portion, it is possible to suppress dark signal generation of the image sensor and to effectively improve photocharge transfer efficiency.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example 1

2 is a cross-sectional view showing an image sensor having a pinned photodiode according to Embodiment 1 of the present invention. Here, a CMOS image sensor having a PNP type pinned photo diode will be shown for convenience of description.

Referring to FIG. 2, the image sensor according to the first exemplary embodiment of the present invention is a substrate of a second conductivity type, eg, P type, in which a first diffusion type of a first conductivity type, for example, a low concentration N ⁻ diffusion region 25 is formed. 20, a transistor gate electrode 23 formed on the substrate 20 to be aligned with one side of the N ⁻ diffusion region 25, and a spacer 31 formed on both sidewalls of the transistor gate electrode 23. And the P ⁰ diffusion region 28a formed on the surface of the N ⁻ diffusion region 25 so that the depth in the region corresponding to the spacer 31 is shallower than the depth in the region exposed to one side of the spacer 31. Include.

At this time, although not shown in the drawing, a high concentration P-type epitaxial layer is formed on the substrate 20. Accordingly, in Embodiment 1 of the present invention, a PNP type pinned port diode including a P type epitaxial layer / N ^- diffusion region 25 / high concentration P ⁰ diffusion region 28a is provided. The transistor gate electrode 23 is formed of a gate insulating film 21 and a gate conductive film 22 similarly to a general gate electrode, and the spacer 31 has a structure in which an oxide film 24 and a nitride film 29 are stacked. Can be done.

It is important to note that the P ⁰ diffusion region 28a is formed to have a different depth for each region. Preferably, the P ⁰ diffusion region 28a is formed such that the depth h ₁ in the region corresponding to the spacer 31 is shallower than the depth h ₂ in the region exposed to one side of the spacer 31. . Through this, it is possible to suppress dark signal generation of the image sensor and to improve photocharge transfer efficiency. In addition, the P ⁰ diffusion region 28a is formed with a different doping concentration for each region. Preferably, the P ⁰ diffusion region 28a is formed such that the doping concentration in the region corresponding to the spacer 31 is lower than the doping concentration in the region exposed to one side of the spacer 31.

Specifically, the spacer is formed to a shallow depth of less than 31 in the P ⁰ diffusion region (28a) of the P ⁰ diffusion region (28a) in the region exposed to a side of the spacer 31 in an area corresponding to the being, N ^- Photoelectric charges focused on the diffusion region 25 may be improved to be transferred to a floating diffusion region (not shown). In addition, by deeply securing the depth of the P ⁰ diffusion region 28a in the region exposed to one side of the spacer 31, dark signal generation can be efficiently suppressed.

Example 2

3 is a cross-sectional view showing an image sensor having a pinned photodiode according to Embodiment 2 of the present invention. The second embodiment of the present invention is the same as the first embodiment, except that the P ⁰ diffusion region 28a is formed with a step between a region corresponding to the spacer and a region exposed to one side of the spacer. Therefore, by maintaining the overall height of the P ⁰ diffusion region 28a constant in the area exposed to one side of the spacer, the optical property degradation problem that may occur as the height of the P ⁰ diffusion region 28a is excessively increased. I can solve it. That is, according to the second embodiment of the present invention, in addition to the effect obtained through the first embodiment of the present invention, an optical characteristic improvement effect can be obtained.

Referring to FIG. 3, the image sensor according to the second exemplary embodiment of the present invention is a substrate of a second conductivity type, eg, P type, having a first conductivity type first diffusion region, for example, a low concentration N ⁻ diffusion region 25. 20, a transistor gate electrode 23 formed on the substrate 20 so as to be aligned with one side of the N ⁻ diffusion region 25, a spacer 31 formed on both sidewalls of the transistor gate electrode 23, and The P ⁰ diffusion region formed on the surface of the N ⁻ diffusion region 25 so that the depth in the region corresponding to the spacer 31 has a step difference with each other while being smaller than the depth in the region exposed to one side of the spacer 31 ( 28a).

At this time, although not shown in the drawing, a high concentration P-type epitaxial layer is formed on the substrate 20. Accordingly, according to the second embodiment of the present invention, there is provided a PNP type pinned port diode composed of a P-type epitaxial layer / N ^- diffusion region 25 / high concentration P ⁰ diffusion region 28a.

In particular, P ⁰ diffusion region (28a) has a spacer (31) one side of the area, P ⁰ diffusion region (28a) in corresponding to the upper surface of the spacer 31 of the P ⁰ diffusion region (28a) in the area exposed to the It is formed a certain depth lower than the upper surface of the. For example, the step between the P ⁰ diffusion region 28a in the region exposed to one side of the spacer 31 and the P ⁰ diffusion region 28a in the region corresponding to the spacer 31 is set to 400 to 600 kV. Preferably, the P ⁰ diffusion region 28a has a step of 500 ns for each region. Accordingly, the P ⁰ diffusion region 28a is formed in a step shape and has a height h ₁ in a region corresponding to the spacer 31 and a height h ₂ in a region exposed to one side of the spacer 31. Will have

In addition, the P ⁰ diffusion region 28a is formed to have different doping concentrations in a region exposed to one side of the spacer 31 and a region corresponding to the spacer 31. For example, the P ⁰ diffusion region 28a is formed to have a higher doping concentration than the region corresponding to the spacer 31 in the region exposed to one side of the spacer 31.

4A to 4D are cross-sectional views illustrating a method of manufacturing an image sensor according to Embodiment 2 of the present invention. For reference, the manufacturing method of the image sensor according to the first embodiment of the present invention is the same as the second embodiment of the present invention except for the step of etching a substrate after forming a spacer, according to the first embodiment of the present invention. Description of the manufacturing method of the image sensor has been omitted. Also, for convenience of description, only a method of manufacturing an image sensor having a PNP type pinned photodiode will be described.

First, as shown in FIG. 4A, a plurality of transistor gate electrodes 23 are formed on a P-type substrate 20 having a P-type epitaxial layer (not shown) thereon. For example, the gate insulating film 21 and the gate conductive film 22 are sequentially formed on the substrate 20, and then selectively etched to form the gate electrode 23 for the transistor.

Subsequently, after forming a mask pattern (not shown) having a structure for opening the photodiode region in which the photodiode is to be formed, an ion implantation process using the mask pattern as an ion implantation mask is performed to low concentration in the substrate 20 of the photodiode region. N ^- diffusion region 25 is formed. As a result, the N ⁻ diffusion region 25 is formed in alignment with one side of the transistor gate electrode 23.

Subsequently, as shown in FIG. 4B, the buffer oxide film 24 is formed along the stepped portion of the substrate 20 including the transistor gate electrode 23. Thereafter, after forming a mask pattern 26 having a structure for opening a region where a photodiode is to be formed, an ion implantation process 27 using this as an ion implantation mask is performed to the upper surface of the N ⁻ diffusion region 25. A high concentration P ⁰ diffusion region 28 is formed. For example, B0 ₂ impurity ions of 0.8 to 1.2 E12 atoms / cm 2 dose are implanted with an energy of 25 to 35 KeV to form the P ⁰ diffusion region 28. Preferably, a BF ₂ impurity ion of 1.0E12 atoms / cm 2 dose is implanted at an energy of 30 KeV with a tilt angle and a twist angle of 0 °. As a result, the P ⁰ diffusion region 28 is formed to have a depth of 'h ₁ ' from the surface of the substrate 20.

Subsequently, as illustrated in FIG. 4C, a strip process is performed to remove the mask pattern 26 (see FIG. 4B) and to deposit the nitride layer 29 on the buffer oxide layer 24.

Subsequently, an etching process 30 is performed to etch the nitride film 29 and the buffer oxide film 24. As a result, spacers 31 are formed on both side walls of the transistor gate electrode 23. In this case, it is important to etch the substrate 20 together with the nitride film 29 and the buffer oxide film 24 in the etching process 30 for forming the spacer 31. For example, the P ⁰ diffusion region 28 is etched from the surface of the substrate 20 by a thickness of 400 to 600 mm 3. Preferably, the P ⁰ diffusion region 28 is etched 500 nm thick from the substrate 20 surface.

Subsequently, as shown in FIG. 4D, the buffer oxide film 33 is formed along the stepped portion of the entire structure including the spacer 31. Thereafter, after forming the mask pattern 34 having the structure of opening the P ⁰ diffusion region 28, an ion implantation process 35 using the mask pattern 34 as an ion implantation mask is performed to form the spacer 31. P ⁰ diffusion regions (not shown) are formed in the P ⁰ diffusion region 28 and the N ⁻ diffusion region 25 exposed to one side. As a result, the P ⁰ diffusion region 28a having a stepped structure as a whole is formed.

That is, a P ⁰ diffusion region 28a having a step is formed between the region corresponding to the spacer 31 and the region exposed to one side of the spacer 31. Preferably, the P ⁰ diffusion region 28a is formed such that the depth h ₁ in the region corresponding to the spacer 31 is shallower than the depth h ₂ in the region exposed to one side of the spacer 31. .

Here, the above-described ion implantation step 35 may be performed only once or twice. In the case of performing only once, BF ₂ impurity ions of 3.8-4.2E12 atoms / cm 2 dose are implanted with an energy of 30-40KeV. Preferably, BF ₂ impurity ions of 4.0E12 atoms / cm 2 dose are implanted with an energy of 35 KeV.

On the other hand, when performing two times, the primary ion implantation step injects 3.8-4.2E12 atoms / cm 2 dose of BF ₂ impurity ions with energy of 30-40KeV, and the secondary ion implantation step is 8-12KeV BF ₂ impurity ions of 4.0 to 6.0E12 atoms / cm 2 dose are implanted with energy. Preferably, the primary ion implantation step injects BF ₂ impurity ions of 4.0E12 atoms / cm 2 doses with an energy of 35 KeV, and the secondary ion implantation process is BF ₂ impurity ions of 5.0E12 atoms / cm 2 doses with an energy of 10 KeV Inject

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a region in which a P ⁰ diffusion region in an area corresponding to a spacer formed on both sidewalls of a gate electrode for a transistor is exposed to one side of the spacer when an image sensor having a PNP-type pinned photodiode is manufactured. By forming a shallower depth than the P ⁰ diffusion region in, the efficiency of transferring the photocharges focused on the N diffusion region to the floating diffusion region can be improved.

In addition, according to the present invention, the depth of the P ⁰ diffusion region is secured by deeply securing the depth of the P ⁰ diffusion region in the region exposed to one side of the spacer formed on both side walls of the transistor gate electrode when manufacturing the image sensor having the PNP type pinned photodiode. Signal generation can be effectively suppressed.

In addition, according to the present invention, in manufacturing an image sensor having a PNP-type pinned photodiode, a P ⁰ diffusion region is formed to have a step between an area exposed to one side of a spacer formed on both side walls of a gate electrode for a transistor and a region corresponding to the spacer. Thus, the overall height of the P ⁰ diffusion region in the region exposed to one side of the spacer can be kept constant. As a result, the optical property of the image sensor may be improved by solving the problem of deterioration of optical properties that may occur as the height of the P ⁰ diffusion region is excessively increased.

Claims (15)

A second conductivity type substrate having a first diffusion region of a first conductivity type; A gate electrode for a transistor formed on the substrate to be aligned with one side of the first diffusion region; Spacers formed on both sidewalls of the transistor gate electrode; And A region which is formed on the surface of the first diffusion region to be aligned with the gate electrode, and a region exposed to one side of the spacer is higher than the region corresponding to the spacer, having a higher doping concentration, and having a higher depth and a lower step height. Second diffusion region of the second conductivity type formed Image sensor comprising a. delete delete The method of claim 1, The step is an image sensor of 400 ~ 600Å. delete The method of claim 1, And the second diffusion region in the region exposed to one side of the spacer and the second diffusion region in the region corresponding to the spacer have different doping concentrations. The method of claim 6, The second diffusion region has a higher doping concentration than the region corresponding to the spacer in the region exposed to one side of the spacer. Forming a gate electrode for a transistor on a substrate of a first conductivity type; Forming a first diffusion region of a second conductivity type in an exposed portion of the substrate to be aligned with one side of the transistor gate electrode; Forming a second diffusion region of a first conductivity type on an upper surface of the first diffusion region to be aligned with one side of the transistor gate electrode; Forming spacers on both sidewalls of the transistor gate electrode; Forming a third diffusion region of the first conductivity type deeper than the second diffusion region in the first and second diffusion regions exposed to one side of the spacer; And Etching the second diffusion region exposed to one side of the spacer to a predetermined depth; Image sensor manufacturing method comprising a. delete The method of claim 8, And etching the second diffusion region to etch the second diffusion region to a depth of 400 to 600 microns from the surface of the substrate. The method of claim 8, The forming of the third diffusion region may include implanting impurity ions having a higher doping concentration than the second diffusion region. The method of claim 11, The forming of the second diffusion region is performed by implanting impurity ions of 0.8-1.2E12 atoms / cm 2 dose with energy of 25-35 KeV. The method of claim 12, The forming of the third diffusion region is performed by implanting impurity ions of 3.8 to 4.2 E12 atoms / cm 2 dose with energy of 30 to 40 KeV. The method of claim 11, In the forming of the third diffusion region, impurity ions of 3.8 to 4.2 E12 atoms / cm 2 dose are implanted with energy of 30 to 40 KeV, and impurity ions of 4.0 to 6.0E12 atoms / cm 2 dose with energy of 8 to 12 KeV secondly. Method of manufacturing an image sensor made through the ion implantation process of two injection. delete

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