KR20040092737A - Cmos image sensor with improved dead zone characteristics and dark current characteristics and the method for fabricating thereof - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to improve dead zone and dark current properties by changing gradually doping profile of a p-type ion-implanted region. CONSTITUTION: A gate(23) of a transfer transistor is formed on a p-type substrate(20) having a field oxide layer(22). A spacer(26) is formed at both sidewalls of the gate. An n-type ion-implanted region(24) for a photodiode is formed in the substrate to align one side of the field oxide layer and one side of the gate. A p-type ion-implanted region with a stepped doping profile is formed on the n-type ion-implanted region. A lightly doped region(25c) of the p-type ion-implanted region is formed at the lower of the spacer, a heavily doped region(25a) is formed to align the field oxide layer, and a medium doped region(25b) is formed between the lightly and heavily doped regions.

Description

IMAGE SENSOR WITH IMPROVED DEAD ZONE CHARACTERISTICS AND DARK CURRENT CHARACTERISTICS AND THE METHOD FOR FABRICATING THEREOF}

The present invention relates to a CMOS image sensor, in particular, a CMOS image sensor that improves the dead zone characteristics and dark current characteristics by forming a p-type ion implantation region by changing the doping profile of the p-type ion implantation region constituting the photodiode step by step; It relates to a manufacturing method.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being in close proximity, and a CMOS (Complementary MOS) image sensor uses CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

CCD (charge coupled device) has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied in recent years. The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detects signals in a switching method, and implements an image by using a CMOS manufacturing technology, which consumes less power and uses 30 to 40 masks as many as 20 masks. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor.

1 is a circuit diagram showing a unit pixel composed of one photodiode (PD) and four MOS transistors in a conventional CMOS image sensor, and includes a photodiode 100 for generating photocharges by receiving light; The transfer transistor 101 for transporting the photocharges collected from the photodiode 100 to the floating diffusion region 102 and resets the floating diffusion region 102 by setting the potential of the floating diffusion region to a desired value and discharging electric charges. A reset transistor 103 for supplying a voltage to the floating diffusion region, a drive transistor 104 serving as a source follower buffer amplifier, and an addressing role for switching. It consists of a select transistor 105 that performs the following. Outside the unit pixel, a load transistor 106 is formed to read an output signal.

The operation of the unit pixel configured as described above is performed as follows. Initially, the reset transistor 103, the transfer transistor 101, and the select transistor 105 are turned on to reset the unit pixels.

At this time, the photodiode 100 begins to be depleted, and carrier charging occurs in the photodiode, and the floating diffusion region 102 is charged in proportion to the supply voltage VDD.

Thereafter, the transfer transistor 101 is turned off, the select transistor 105 is turned on, and the reset transistor 103 is turned off. In such an operation state, after reading the first output voltage V1 from the unit pixel output terminal Out and storing the first output voltage V1 in a buffer (not shown), the transfer transistor 101 is turned on to change the charge of the photodiode according to the light intensity. To the floating diffusion region 102, and then reads the second output voltage V2 again from the output terminal Out to change the analog data for the two voltage differences 'V1-V2' into digital data. One operation cycle is completed.

FIG. 2 is a cross-sectional view of a photodiode 100 and a transfer transistor 101 in a unit pixel of a CMOS image sensor according to the related art, wherein the photodiode is formed of a p / n / p type photodiode. The case is shown.

Referring to FIG. 2, the unit pixel includes a p-type epitaxial layer 11 and a field oxide film 12 epitaxially grown on a p-type substrate 10, and a gate electrode 13 of a transfer transistor on the surface of the epitaxial layer. Is formed. In addition, an n-type ion implantation region 14 for a photodiode is formed inside the p-type epi layer 11, and an upper portion of the n-type ion implantation region 143 for a photodiode and a lower surface of the p-type epilayer 11 are formed. The p-type ion implantation region 16 for photodiodes is formed in this structure.

The gate 13 of the transfer transistor has a spacer 15 on a sidewall thereof, and a floating diffusion region (FD) 17 is formed on one side of the gate 13.

When the reverse bias is applied between the n-type ion implantation region 14 for photodiode and p region (p-type ion implantation region 16 for photodiode and p-type epilayer 11) in the unit pixel of the above structure, the photodiode When the ion implantation concentration of the n-type ion implantation region 14 for photodiode and the p-type ion implantation region 16 for photodiode is properly blended, the p-type n-type ion implantation region 14 for photodiode becomes fully depletion As the depletion region extends into the type epi layer 11 and the p-type ion implantation region 16 for the photodiode, more depletion layer expansion occurs into the p-type epi layer 11 having a relatively low dopant concentration. Such a depletion region can accumulate and store photocharges generated by incident light and use the same to reproduce an image.

In the conventional CMOS image sensor, after the gate electrode 13 of the transfer transistor is formed, the n-type ion implantation region 14 for photodiode and the p-type ion implantation region 16 for photodiode are successively formed. The unit pixel was formed by applying the method, and according to this manufacturing method, there was a problem in that the dead zone characteristic was lowered.

The dead zone characteristic refers to a time interval during which the CMOS image sensor does not respond. More specifically, the dead zone characteristic refers to a time interval between the moment when the image sensor is exposed to light and the moment when a corresponding response is output.

According to the conventional manufacturing method, since the p-type ion implantation region is formed immediately after the formation of the n-type ion implantation region, process conditions in which the dose of p-type impurity ions are relatively high are used. Since the relatively high concentration of p-type ion implantation region 16 forms a barrier potential that prevents electrons from being transferred, there is a problem in that the dead zone characteristic is deteriorated because initial photocharge is not transferred.

In order to solve such a problem, the gate electrode 13 of the transfer transistor is formed by changing the process sequence, and then the n-type ion implantation region 14 for photodiode is formed, and then the spacer 15 is formed. Since then, a method of forming the p-type ion implantation region 16 for photodiodes has been proposed.

However, when this method is applied, the dead zone characteristic is improved, but the dark current characteristic is deteriorated. The dark current is generated by electrons moving from the photodiode to the floating diffusion region even in the absence of light. The dark current is mainly distributed at the base of the silicon surface and the edges of the field oxide film (line defects, point defects, etc.) and dangling bonds.

In the unit pixels shown in Fig. 2, the portions 18 and 19 marked with x indicate the boundary between the field oxide film and the active region and the bottom surface of the silicon surface that cause the dark current. This area is a major area where dark currents are induced because of the large number of defects or dangling bonds, and dark currents are one of the main factors that lower the yield of current CMOS image sensors.

The p-type ion implantation region 16 for the photodiode serves to surround the dark current source to improve the dark current characteristics. As described above, the p-type ion implantation region 16 is formed after the formation of the spacer 15. In this case, since the p-type ion implantation region 16 does not exist under the spacer 15, there is a problem that the dark current characteristic is lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a CMOS image sensor and a method of manufacturing the same, which simultaneously improve dead zone characteristics and dark current characteristics.

1 is a circuit diagram showing the configuration of a CMOS image sensor unit pixel according to the prior art;

2 is a cross-sectional view showing a cross-sectional structure centering on a transistor transistor in a unit pixel of a CMOS image sensor formed according to the prior art;

3A to 3C are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to an embodiment of the present invention;

Fig. 4 shows the well potential of the photodiode region when the transfer transistor is turned off.

* Description of the symbols for the main parts of the drawings *

20: p-type substrate

21: p-type epi layer

22: field oxide film

23: gate of the transfer transistor

24: n-type ion implantation area for photodiode

25a, b, c: p-type ion implantation region for photodiode

26: insulating film for spacer

27: floating diffusion area

The present invention for achieving the above object is a gate of the transfer transistor formed on the first conductivity type substrate having a field oxide film and spacers provided on both sidewalls of the gate; A first ion implantation region of a second conductivity type aligned in one side of the field oxide film and one side of the gate and formed in the substrate of the first conductivity type; A second ion implantation region formed on the first ion implantation region and having a low concentration of a first conductivity type formed under the spacer; A third ion implantation region of the first conductivity type formed on the first ion implantation region and having one side aligned with the field oxide film; And a fourth ion implantation region of a second conductivity type, which is formed on the first ion implantation region and is formed between the second ion implantation region and the third ion implantation region.

In addition, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a gate of a transfer transistor and an n-type ion implantation region for photodiodes aligned with the gate of the transfer transistor on a first conductive substrate having a field insulating film formed thereon; Performing a first p-type ion implantation process on the n-type ion implantation region for the photodiode; Applying an insulating film for spacer formation to the epitaxial layer at a predetermined thickness; Performing a second p-type ion implantation process on the n-type ion implantation region for the photodiode; Forming a spacer by full etching the insulating film for forming an additive spacer; And performing a third p-type ion implantation process on the n-type ion implantation region for the photodiode.

The present invention improves the dead zone characteristics and the dark current characteristics simultaneously by forming the p-type ion implantation region by changing the doping profile of the p-type ion implantation region constituting the photodiode by using the insulating film for spacer formation.

More specifically, a relatively low concentration of the first p-type ion implantation region under the spacer, a second p-type ion implantation region of intermediate concentration adjacent to the first p-type ion implantation region, and the second p-type ion implantation region The high concentration of the third p-type ion implantation region adjacent to the p-type ion implantation region for the photodiode can simultaneously improve the dead zone characteristic and the dark current characteristic.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

3A to 3C are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, a low concentration p-type epi layer 21 is formed on a relatively high concentration p-type substrate 20. The reason for forming the low concentration p-type epitaxial layer 21 on the high concentration p-type substrate 20 is to increase the depth of the depletion layer of the photodiode to improve the characteristics, and the high concentration substrate is a cross between unit pixels This is because cross talk can be prevented.

Next, a field oxide film 22 defining an active region and a field region is formed in a predetermined region of the p-type epitaxial layer 21 and the gate electrode 23 of the transfer transistor is formed. Next, the n-type ion implantation region 24 for the photodiode is formed so as to be aligned with the sidewall of the gate electrode 23.

Next, as shown in FIG. 3A, a first p-type ion implantation process is performed to form a p-type ion implantation region 25 for photodiodes. The first p-type ion implantation process is performed using energy having a doze amount of about 2.0 × 10 ¹² to 3.0 × 10 ¹² and an penetration depth Rp of about 300 GPa. Although the ion implantation mask for the first p-type ion implantation process is not shown in FIG. 3A, a conventional ion implantation mask that exposes the photodiode region is used.

The p-type ion implantation region 25 for the photodiode is formed between the n-type ion implantation region 24 for the photodiode and the lower surface of the epi layer 21, one side of which is aligned with the sidewall of the gate electrode 23. , The other side is formed in contact with the field oxide film 22.

As will be described later, the p-type ion implantation regions for photodiodes according to an embodiment of the present invention are formed to have three levels of concentration, and the p-type ion implantation regions for photodiodes having respective concentrations are first to third, respectively. The p-type ion implantation regions 25a, 25b, and 25c for photodiode will be referred to as.

After performing the first p-type ion implantation process as described above, an insulating film 26 for forming a spacer is formed on the epitaxial layer 21 including the field oxide film 22 and the gate electrode 23, as shown in FIG. 3B. Coating is carried out at a thickness of about 1500 to 2000 kPa.

Next, as shown in FIG. 3B, a second p-type ion implantation process is performed. The second p-type ion implantation process is performed using energy having a dose of about 1.0 × 10 ¹² to 1.5 × 10 ¹² and an penetration depth Rp of about 300 Pa.

Although the ion implantation mask for the second p-type ion implantation process is not shown in FIG. 3B, a conventional ion implantation mask that exposes the photodiode region is used. Through this second p-type ion implantation process, a relatively high concentration of the first p-type ion implantation region 25a and a second p-type ion implantation region 25b having a lower concentration than the first p-type ion implantation region are formed. Here, the low concentration second p-type ion implantation region 25b is formed below the spacer formation insulating film 26 having a thick thickness.

Next, the entire surface is etched to form a spacer and a third p-type ion implantation process is performed as shown in FIG. 3C. When the entire surface is etched to form the spacer, the insulating layer 26 for forming the spacer is mostly removed and the spacer 26 is formed only on the sidewall of the gate electrode.

Referring to FIGS. 3B and 3C, it can be seen that the width of the spacer formation insulating layer 26 formed on the sidewall of the gate electrode 23 is reduced through the front surface etching process.

After the entire surface etching process, a third p-type ion implantation process is performed. The third p-type ion implantation process has a dose of about 1.0 × 10 ¹² to 1.5 × 10 ¹² and an penetration depth of about 300 Å. It is carried out using energy enough to have

When the third p-type ion implantation process is performed, the high concentration of the first p-type ion implantation region 25a, the intermediate concentration of the second p-type ion implantation region 25b, and the low concentration of the third p-type ion implantation Region 25c is formed.

That is, p-type ion implantation regions 25a, 25b, and 25c for photodiodes are formed in which the concentration increases gradually from the field oxide film toward the gate electrode of the transfer transistor. Next, the floating diffusion region 27 is formed on the other side of the transfer transistor gate electrode 23.

In the CMOS image sensor formed as described above, when the n-type ion implantation region 24 and the p-type ion implantation regions 25a, 25b, and 25c for the photodiode react to form a depletion layer, Referring to the pinning voltage, the fixed voltage of the first p-type ion implantation region 25a is the smallest, and the fixed voltage 25c of the third p-type ion implantation region is the highest. That is, it has a fixed voltage inversely proportional to the doping concentration of the p-type ion implantation region.

Accordingly, the well potential in the photodiode region has an inclination that is easy to transport the photoelectrons to the floating diffusion region, which is shown in FIG.

4 is a diagram illustrating a well potential of the photodiode region when the transfer transistor is turned off. Referring to this, since the well potential is formed to have an inclination in which the electron potential decreases toward the transfer transistor, When the transistor is turned on, the photoelectron transfer becomes easy.

In the CMOS image sensor according to the exemplary embodiment of the present invention, since the low concentration of the p-type ion implantation region 25c exists under the spacer of the transfer transistor, the dark current characteristic is improved without deterioration of the dead zone characteristic.

That is, although the p-type ion implantation region existing under the spacer forms a barrier potential for photoelectrons, the p-type ion implantation region existing under the spacer is very low concentration p-type implantation according to an embodiment of the present invention. Since it is a region, it does not form a barrier potential enough to deteriorate dead zone characteristics.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

According to the characteristics of the present invention, it is possible to improve the dark current characteristics and dead zone characteristics of the image sensor and improve the charge transport efficiency, thereby improving the quality competitiveness of the product.

Claims (5)

A gate of the transfer transistor formed on the first conductivity type substrate on which the field oxide film is formed and spacers provided on both sidewalls of the gate; A first ion implantation region of a second conductivity type aligned in one side of the field oxide film and one side of the gate and formed in the substrate of the first conductivity type; A second ion implantation region formed on the first ion implantation region and having a low concentration of a first conductivity type formed under the spacer; A third ion implantation region of the first conductivity type formed on the first ion implantation region and having one side aligned with the field oxide film; And A fourth ion implantation region of a second conductivity type, which is formed on the first ion implantation region, and is formed between the second ion implantation region and the third ion implantation region; CMOS image sensor comprising a. The method of claim 1, And the second to fourth ion implantation regions have substantially the same penetration depths. Forming an n-type ion implantation region for a photodiode aligned with a gate of the transfer transistor and a gate of the transfer transistor on a first conductivity type substrate having a field insulating film formed thereon; Performing a first p-type ion implantation process on the n-type ion implantation region for the photodiode; Applying an insulating film for spacer formation to the epitaxial layer at a predetermined thickness; Performing a second p-type ion implantation process on the n-type ion implantation region for the photodiode; Forming a spacer by full etching the insulating film for forming an additive spacer; And Performing a third p-type ion implantation process on the n-type ion implantation region for the photodiode Method of manufacturing a CMOS image sensor comprising a. The method of claim 3, wherein The first to third ion implantation process is a method of manufacturing a CMOS image sensor, characterized in that using the ion implantation energy having the same penetration depth. The method of claim 3, wherein The first p-type ion implantation process uses a dose of 2.0 × 10 ¹² to 3.0 × 10 ¹² , and the second to third p-type ion implantation processes uses a dose of 1.0 × 10 ¹² to 1.5 × 10 ¹² . Method of manufacturing a CMOS image sensor, characterized in that using.