CN106298966B - Semiconductor device, method of manufacturing the same, and electronic apparatus - Google Patents

Semiconductor device, method of manufacturing the same, and electronic apparatus Download PDF

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CN106298966B
CN106298966B CN201510270513.9A CN201510270513A CN106298966B CN 106298966 B CN106298966 B CN 106298966B CN 201510270513 A CN201510270513 A CN 201510270513A CN 106298966 B CN106298966 B CN 106298966B
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well region
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CN106298966A (en
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施森华
胡王凯
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes

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Abstract

The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate; performing first ion implantation by using a first photomask to form a first well region with a first conductivity type in the semiconductor substrate; performing second ion implantation by using a second photomask to form a second well region with the first conductivity type in the semiconductor substrate; forming a first diffusion region of a second conductivity type in the first well region; and forming a second diffusion region of the first conductivity type in the second well region, wherein the second well region is positioned outside the first well region, and the ion concentration of the first conductivity type in the first well region is lower than that in the second well region. The invention also provides the semiconductor device and the electronic device prepared by the method. Compared with the prior art, the semiconductor diode device and the electronic device thereof prepared by the manufacturing method can improve ESD voltage tolerance and current tolerance capability, effectively reduce electric leakage and improve ESD performance of the device.

Description

Semiconductor device, method of manufacturing the same, and electronic apparatus
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes as a result of pursuit of high device density, high performance, and low cost. However, this trend of progress has a negative impact on the reliability of the end product: in the field of semiconductor technology, the electrostatic discharge (ESD) phenomenon is a great threat to integrated circuits, and can break down the integrated circuits and semiconductor elements, promote element aging, and reduce production yield. Accordingly, as semiconductor process dimensions continue to decrease, ESD protection designs become increasingly challenging and difficult in CMOS technologies on the nanometer scale.
In the prior art, the multilayer metal oxide device, the ceramic capacitor and the diode can effectively play a role in ESD protection. Wherein the prior art generally uses a MOS structure diode for ESD protection. But since the withstand current of the MOS structure diode is determined by the channel width, the withstand current thereof is relatively low. Therefore, it is necessary to provide a new method for manufacturing an ESD diode device, which improves the ESD voltage tolerance and current tolerance and reduces the leakage current.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a semiconductor device preparation method, which comprises the following steps:
step 1: providing a semiconductor substrate;
step 2: performing first ion implantation by using a first photomask to form a first well region with a first conductivity type in the semiconductor substrate;
and step 3: performing second ion implantation by using a second photomask to form a second well region with the first conductivity type in the semiconductor substrate;
and 4, step 4: forming a first diffusion region of a second conductivity type in the first well region;
and 5: and forming a second diffusion region of the first conductivity type in the second well region, wherein the second well region is positioned outside the first well region, and the ion concentration of the first conductivity type in the first well region is lower than that in the second well region.
The shapes of the light-transmitting areas of the second photomask and the first photomask are complementary to each other.
Wherein, the sequence of step 3 and step 2 is intermodulation.
The first conductive type is an N type, and the second conductive type is a P type.
Wherein the first diffusion region of the second conductivity type and the first well region of the first conductivity type constitute a diode for an electrostatic discharge protection circuit.
Wherein the concentration of the first ion implantation is 2E 12.
Wherein the first ion implantation comprises two phosphorus ion implantations.
Wherein, the energy of the two times of phosphorus ion implantation is 140 +/-10 Kev and 440 +/-30 Kev respectively, and the dosage is 1E12 +/-0.2E 12 and 1E12 +/-0.2E 12 respectively.
The invention also provides a method for preparing the semiconductor device by using the method.
The invention also provides an electronic device comprising the semiconductor device prepared by the method and an electronic component connected with the semiconductor device.
In summary, the semiconductor device manufacturing method of the present invention includes a semiconductor device, a manufacturing method thereof, and an electronic apparatus. Compared with the prior art, the semiconductor diode device and the electronic device thereof prepared by the manufacturing method can improve ESD voltage tolerance and current tolerance capability, effectively reduce electric leakage and improve ESD performance of the device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 shows a schematic cross-sectional view of a prior art ESD diode structure;
fig. 2 shows the relevant steps of a manufacturing method according to an embodiment of the invention and a cross-sectional schematic view of the obtained ESD diode.
Fig. 3 shows a graph of a simulation of impurity profile concentration for phosphorus and arsenic ions at different junction depths.
Fig. 4 shows a flow chart of a method of preparation according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
Next, a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to fig. 1 and 2.
As shown in fig. 1, the related art semiconductor device includes a semiconductor substrate 100. The semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. The semiconductor substrate is preferably a P-type substrate doped with B or Ga element. An N-well 105 is then formed in the P-type substrate.
N-well 105 may be formed by growing a layer of SiO on the surface of a P-type substrate2In SiO2Coating photoresist thereon for photolithography to form N well doping window, and etching SiO in the window with HF2And removing the photoresist. An N-type impurity may be implanted at the window at this time to form an N-well. The N-type impurity is preferably high-energy phosphorus (P) or arsenic (As) ions. The doping implantation dose refers to the concentration of implantation of impurity atoms, which determines the conductivity of the doped layer, and is, for example, about 2E 13.
Shallow Trench Isolation (STI) structures 101 may also be included on the semiconductor substrate 100. In general, the basic flow of the formation of the STI structure 101 is: at H2O or O2Thermally oxidizing the substrate to form SiO in the presence of a gas2A thin layer with a thickness of about 20 nm. Then on SiO2Depositing silicon nitride with thickness of about 250nm on the thin layer by CVD, etching a trench with a certain depth in the isolation region, performing side wall oxidation, and depositing SiO with thickness of about 0.5-1.0 μm in the trench by Chemical Vapor Deposition (CVD)2Finally, planarization is performed by a Chemical Mechanical Polishing (CMP) method, the surface oxide layer is removed until the silicon nitride layer, and then wet etching such as hot phosphoric acid is performed at 180 ℃ to remove the silicon nitride layer, thereby finally forming the trench isolation region 101 and the active region. It is to be noted that the step of forming the shallow trench isolation structure may precede the step of forming the N-well 200.
Subsequently, N + ion implantation doping and diffusion drive are performed using an N + reticle to form the N diffusion region 102, wherein the N + ions are mainly phosphorus or arsenic. Similarly, a P + mask is used to perform P + ion implantation doping and diffusion drive to form the P diffusion region 103, wherein the P + ions are mainly boron or gallium.
Fig. 2 shows a method for manufacturing an ESD diode according to the present invention. At one endIn one example, first at H2O or O2Thermally oxidizing the semiconductor substrate 200 in a vented condition to form SiO2A thin layer with a thickness of about 20 nm. Then on SiO2Depositing silicon nitride with thickness of about 250nm on the thin layer by CVD, etching a trench with a certain depth in the isolation region, and depositing SiO with thickness of about 0.5-1.0 μm in the trench by Chemical Vapor Deposition (CVD)2Finally, planarization is performed by a Chemical Mechanical Polishing (CMP) method, the surface oxide layer is removed until the silicon nitride layer, and then wet etching such as hot phosphoric acid is performed at 180 ℃ to remove the silicon nitride layer, thereby finally forming the trench isolation region 201 and the active region. It is noted that the step of forming the shallow trench isolation structure may be performed after the subsequent formation of the first well region and the second well region.
Subsequently, the key steps of the ESD diode manufacturing method according to the present invention are performed. As an example, a layer of SiO is grown on the surface of a P-type substrate2In SiO2Covering a first photomask for photoetching, and etching SiO in the window2After removing the photo mask, performing a first ion implantation to form a first well region 205 with a first conductivity type in the semiconductor substrate; cleaning the surface to remove impurities and oxides on the surface; growing another SiO on the surface2Protective layer of SiO2Covering a second photomask for photoetching to etch SiO at the window2After removing the mask, a second ion implantation is performed to form a second well region 210 having the first conductivity type outside the first well region 205 in the semiconductor substrate. It is noted that the first mask is opaque to light at a portion of the surface of region 210 shown in FIG. 2, such that the region 210 is not accessible to the first ion implantation; the second mask is transparent to light at the surface of region 210, and this layer of mask enables region 210 shown in fig. 2 to receive the second ion implantation, forming the second well region 210 shown in fig. 2.
The first photomask and the second photomask (photomask plate and mask plate) mainly comprise quartz glass, metal chromium and photosensitive resist. Wherein, quartz glass is used as a substrate, and a layer of metal chromium and photosensitive resist are plated on the quartz glass to form a photosensitive material. The predefined pattern of the photomask is exposed on the photosensitive adhesive through electronic laser equipment, the exposed area can be developed, the predefined pattern is formed on the metal chromium to form the photomask similar to the exposed negative, then the photomask is applied to projection positioning, the projected predefined pattern is subjected to photoetching through a photoetching machine, and the production and processing procedures are as follows: exposing, developing, removing photoresist, and finally applying to photoetching.
After the first mask is provided, as an example, a first ion implantation is performed on the light-transmitting region to the region 205, and the first implanted ions are N-ions, so as to form a first well region 205 having the first conductivity type in the semiconductor substrate. The doping implantation dose refers to the concentration of impurity atoms implanted, which determines the strength of conduction of the doped layer. The ions of the first ion implantation are typically phosphorus or arsenic ions. By way of example, the first ion implantation comprises two phosphorus ion implantations having energies of 140 ± 10Kev and 440 ± 30Kev, respectively, and doses of 1E12 ± 0.2E12 and 1E12 ± 0.2E12, respectively. Alternatively, the ions used in the ion implantation process may be group V ions such As arsenic (As) ions.
After the second mask is provided, a second ion implantation is performed on the P-type substrate in the light-transmitting region, for example, and the N-type impurity preferably uses high-energy phosphorus (P) or arsenic (As) ions to form a second well region 210 with a different ion concentration from that of the first well region 205 in the semiconductor substrate outside the first well region 205. As an example, the implantation dose of the N-type impurity of the second ion implantation is about 2E 13. Alternatively, the ions used in the second ion implantation process may be group V ions such As arsenic (As) ions.
Note that the ion concentration of the first well region 205 is lower than that of the second well region 210. The first mask and the second mask have a shape complementary to the light-transmissive region, thereby forming a first well region 205 and a second well region 210 contiguous to each other on the semiconductor substrate.
In the ion implantation process, the surface of the silicon wafer is bombarded by high-energy phosphorus or arsenic ion beams, and the photoetching is controlled through the two layers of light masks to form a doping window. Doping in the region of the first well region 205At the impurity window, impurity P or As ions are implanted into the bulk of the silicon, while at other locations, such as region 210, impurity P or As ions are implanted by the protective layer SiO on the surface of the silicon2And shielding to complete the process of selective doping. The impurity phosphorus or arsenic ions entering into the silicon form a certain distribution at a certain position. Generally, the depth (mean range) of the ion implantation is shallow and the concentration is large, and they must be redistributed again. The depth of doping is determined by the energy and mass of the implanted impurity ions, and the concentration of doping is determined by the number (dose) of the implanted impurity ions.
It should be noted that the process of performing the first ion implantation and forming the first well region 205 and the process of performing the second ion implantation and forming the second well region 210 may be reversed, that is, the second ion implantation and forming the second well region 210 may be performed first, and then the first ion implantation and forming the first well region 205 may be performed again.
Subsequently, a first diffusion region 203 of the second conductivity type is formed within the first well region 205; a second diffusion region 202 of the first conductivity type is formed within the second well region 210. The first diffusion region 203 of the second conductivity type and the first well region 205 of the first conductivity type constitute a diode for an electrostatic discharge protection circuit. As an example, the second conductivity type is P-type and the first conductivity type is N-type. Further comprising forming a first electrical contact 204 to said first diffusion region of said second conductivity type and a second electrical contact 208 to said second diffusion region of said first conductivity type on said semiconductor substrate. In addition, the electrostatic discharge protection diode as an electronic device and an electronic component connected with the electronic device can form an electrostatic protection electronic device.
After ion implantation, an annealing step may also be performed. The annealing step is preferably at 600-1000 ℃ H2And heating in the environment, repairing the crystal damage on the surface of the Si caused by ion implantation, electrically activating the implanted impurities, and further diffusing the doped impurities by annealing. The annealing step preferably uses a Rapid Thermal Process (RTP) to reduce impurity diffusion.
In the diode fabrication process, where junction depth X is defined as the distance from the surface in the silicon to where the diffusion layer concentration equals the substrate concentration, it is typically measured in microns. Therefore, on the premise of scaling down the size of the integrated circuit, the junction depth X is required to be reduced by the same factor at the same time by the isoelectric field, while the resistance of the device is required to be as small as possible by the modern technology, so that the requirements of both shallow junction depth and high doping are required to be met at the same time. According to the ion doping concentration of different junction depths, an impurity distribution shape graph (doping profile) can be made to obtain the distribution conditions of different doping ions under different junction depths, so that the doping ions can be selected and optimized according to the process requirements of different junction depths.
Fig. 3 shows a graph of a simulation of impurity profile concentration for phosphorus and arsenic ions at different junction depths according to an embodiment of the present invention. The dopant ions phosphorus and arsenic are implanted into the semiconductor in the form of ion beams, and the impurity concentration produces a peak distribution in the semiconductor, the impurity distribution being determined primarily by the ion mass and implantation energy. In fig. 3, the horizontal axis is the junction depth X measured in microns and the vertical axis is the dopant ion concentration per cubic centimeter, with the dark red curve representing the phosphorous ion doping and the light green curve representing the arsenic ion doping. As can be seen from fig. 3, the doping concentration of arsenic ions is higher at junction depths below about 0.15 μm, while the doping concentration of phosphorus ions is higher at junction depths above about 0.15 μm.
Table 1 below shows leakage simulation data of ESD protection diodes fabricated according to the semiconductor device process of the present invention. As can be seen from the table, the leakage amount of the ESD protection diode prepared according to the semiconductor device process of the present invention is reduced by about 3.6 times compared with the reference case, which effectively reduces the leakage of the diode.
Table 1: diode leakage simulation data
Figure BDA0000723476300000071
Fig. 4 shows a flow chart of a method of preparation according to an embodiment of the invention. Wherein S401 provides a semiconductor substrate; s402, performing first ion implantation by using a first photomask to form a first well region with a first conductivity type in the semiconductor substrate; s403, performing a second ion implantation using a second mask to form a second well region of the first conductivity type outside the first well region in the semiconductor substrate; s404 forming a first diffusion region of the second conductivity type in the first well region; s405 forms a second diffusion region of the first conductivity type within a second well region, wherein an ion concentration of the first conductivity type within the first well region is lower than an ion concentration of the first conductivity type within the second well region.
Example two
Next, a semiconductor device of the present invention will be described in detail with reference to fig. 2.
As shown in fig. 2, the semiconductor device of the present invention includes a semiconductor substrate 200. The semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. The semiconductor substrate is preferably a P-type substrate doped with B or Ga element.
Shallow Trench Isolation (STI) structures 201 may also be included on the semiconductor substrate. In general, the basic flow of the formation of the STI structure 201 is: at H2O or O2Thermally oxidizing the substrate to form SiO in the presence of a gas2A thin layer with a thickness of about 20 nm. Then on SiO2Depositing silicon nitride with thickness of about 250nm on the thin layer by CVD, etching a trench with a certain depth in the isolation region, performing side wall oxidation, and depositing SiO with thickness of about 0.5-1.0 μm in the trench by Chemical Vapor Deposition (CVD)2Finally, planarization is performed by a Chemical Mechanical Polishing (CMP) method, the surface oxide layer is removed until the silicon nitride layer, and then wet etching such as hot phosphoric acid is performed at 180 ℃ to remove the silicon nitride layer, thereby finally forming the trench isolation region 201 and the active region.
The semiconductor device of the present invention includes a first well region 205 having a first conductivity type within the semiconductor substrate; within the semiconductor substrate there is implanted N-ions, typically phosphorous or arsenic ions, within a first well region 205 of the first conductivity type. As an example, the first well region may include phosphorus ions implanted in two times, the energies of the phosphorus ions implanted in two times are 140 ± 10Kev and 440 ± 30Kev, respectively, and the doses are 1E12 ± 0.2E12 and 1E12 ± 0.2E12, respectively. Alternatively, the implanted ions may be group V ions such As arsenic (As) ions.
The semiconductor device of the present invention further includes a second well region 210 formed outside the first well region 205 in the semiconductor substrate and having an ion concentration different from that of the first well region 205. The second well region 210 formed outside the first well region 205 in the semiconductor substrate and having a different ion concentration from the first well region 205 has an N-type impurity therein, and the N-type impurity is preferably high-energy phosphorus (P) or arsenic (As) ions, for example, the implantation dose of the N-type impurity is about 2E 13. Alternatively, the N-type impurity may be a group V ion such As arsenic (As) ion.
Note that the ion concentration of the first well region 205 is lower than that of the second well region 210. And the first well region 205 and the second well region 210 formed on the semiconductor substrate are connected to each other. Also, the order of the steps of forming the first well regions 205 and the second well regions 210 may be interchanged.
In addition, the semiconductor device of the present invention further includes a first diffusion region 203 of the second conductivity type formed in the first well region 205, and a second diffusion region 202 of the first conductivity type formed in the second well region 210. The first diffusion region 203 of the second conductivity type and the first well region 205 of the first conductivity type constitute a diode for an electrostatic discharge protection circuit. As an example, the second conductivity type is P-type and the first conductivity type is N-type.
In another embodiment, a first electrical contact 204 connected to the first diffusion region of the second conductivity type and a second electrical contact 208 connected to the second diffusion region of the first conductivity type are also included, formed on the semiconductor substrate.
The ESD protection diode device formed by the manufacturing method comprises a first well region and a second well region which are positioned in a semiconductor substrate, wherein the first well region and the second well region have different doping concentrations, diffusion regions are also formed in the first well region and the second well region, and the diffusion regions and the well regions form an ESD diode together for electrostatic discharge protection. Compared with the prior art, the first well region has lower doping concentration, and the leakage amount of the device is reduced, so that the semiconductor device formed by the preparation process has stronger ESD protection characteristic and robustness, and can provide better ESD protection performance.
EXAMPLE III
The invention also provides an electronic device which comprises the semiconductor device and an electronic component connected with the semiconductor device.
Wherein the semiconductor device includes: a semiconductor substrate; a first well region having a first conductivity type formed within the semiconductor substrate; a second well region of the first conductivity type formed outside the first well region within the semiconductor substrate; a first diffusion region of a second conductivity type formed in the first well region; and a second diffusion region of the first conductivity type formed in the second well region, wherein the ion concentration of the first conductivity type in the first well region is lower than the ion concentration of the first conductivity type in the second well region. The first diffusion region of the second conductivity type and the first well region of the first conductivity type together constitute a diode for an electrostatic discharge protection circuit. Further, forming a first electrical contact connected to the first diffusion region of the second conductivity type and a second electrical contact connected to the second diffusion region of the first conductivity type on the semiconductor substrate may be included.
Alternatively, the electronic device includes the semiconductor device manufactured by the method described in the first embodiment and an electronic component connected to the semiconductor device.
The electronic device also has the advantages as described above, since the semiconductor device included has better ESD protection performance.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (7)

1. A method of manufacturing a semiconductor device, comprising:
step 1: providing a semiconductor substrate;
step 2: performing a first ion implantation using a first mask to form a first well region of a first conductivity type in the semiconductor substrate, the first ion implantation comprising two phosphorus ion implantations having energies of 140 + -10 Kev and 440 + -30 Kev, respectively, and doses of 1E12 + -0.2E 12atoms/cm, respectively2And 1E 12. + -. 0.2E12atoms/cm2；
And step 3: performing second ion implantation by using a second photomask to form a second well region with the first conductivity type in the semiconductor substrate;
and 4, step 4: forming a first diffusion region of a second conductivity type in the first well region;
and 5: forming a second diffusion region of the first conductivity type in the second well region, wherein the second well region is located outside the first well region, and the ion concentration of the first conductivity type in the first well region is lower than that in the second well region;
the first diffusion region of the second conductivity type and the first well region of the first conductivity type constitute a diode for an electrostatic discharge protection circuit.
2. The method of claim 1, wherein the shapes of the transparent regions of the second mask and the first mask are complementary to each other.
3. The method of claim 1, wherein the steps 3 and 2 are sequentially intermodulated.
4. The production method according to claim 1, wherein the first conductivity type is an N-type, and the second conductivity type is a P-type.
5. The method of claim 1, wherein the first ion implantation concentration is 2E12atoms/cm2。
6. A semiconductor device prepared by the method of any one of claims 1 to 5.
7. An electronic device comprising the semiconductor device according to claim 6 and an electronic component connected to the semiconductor device.
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