JP2004356386A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the uniformity of temperature of a semiconductor wafer upon heat treatment by preventing a conductive film from remaining in the inhibit region of the semiconductor wafer to reduce the strain of the semiconductor wafer. <P>SOLUTION: When a positive type photoresist film R1 is formed on a polycrystalline silicon film which becomes a lower electrode E1 to transfer sequentially the pattern of a photomask onto the chip region of the semiconductor substrate 1, the transfer is applied on the inhibit region OUT of the semiconductor substrate 1. The development of the photoresist film R1 is effected while the polycrystalline silicon film is etched utilizing the remaining photoresist film R1 as a mask to form the lower electrode E1 on the chip region CA and form a pattern (dummy pattern) E1d having a configuration corresponding to the lower electrode in the chip region in the inhibit region OUT. As a result, the polycrystalline silicon film will not remain in the whole of the inhibit region OUT whereby only the strain of the semiconductor wafer (semiconductor substrate 1) is reduced and the uniformity of temperature of the semiconductor wafer upon heat treatment thereafter can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a method of manufacturing a semiconductor device having a conductive film.
[0002]
[Prior art]
A semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a wiring connecting them are formed, for example, by alternately depositing a conductive film and an insulating film.
[0003]
In addition, many semiconductor elements have a diffusion layer or a thermal oxide film, and a thermal load is applied to the semiconductor wafer when these elements are formed.
[0004]
As described above, when stress or thermal stress due to the lamination of the films is applied, the semiconductor wafer is easily distorted, which adversely affects a later processing step.
[0005]
For example, Patent Literature 1 discloses a technique in which a through hole is provided in a central portion of a semiconductor wafer in order to perform heat treatment without causing a film formation defect or thermal distortion.
[0006]
[Patent Document 1]
JP-A-5-47615
[0007]
[Problems to be solved by the invention]
The present inventors are engaged in research and development of semiconductor devices such as microcomputers and system LSIs. Further, these devices are formed using a semiconductor wafer having a large diameter (300 mm or more in diameter).
[0008]
During the above research and development, the occurrence of distortion of the semiconductor wafer and the dispersion of the characteristics of the semiconductor elements in the surface of the semiconductor wafer were observed.
[0009]
As a result of an examination by the present inventors about these causes, it has been found that the influence is due to the deposited film in the peripheral portion of the semiconductor wafer.
[0010]
That is, a plurality of chip regions partitioned by the scribe region exist on the substantially circular semiconductor wafer, and the forbidden region is located so as to surround the plurality of chip regions. This prohibited area is an area where chip acquisition is prohibited.
[0011]
A processed (patterned) conductive film is formed in the chip region, but the conductive film in the forbidden region is not processed and may remain as it is. Note that such a process will be described later in detail with reference to FIGS.
[0012]
As described above, when the conductive film remains in the forbidden region, the semiconductor wafer is deformed by the film stress, which adversely affects a subsequent process. For example, it causes a focus failure in a photolithography process, a suction failure of a semiconductor wafer in various processing apparatuses, and the like.
[0013]
Further, if the heat treatment is performed in a state where the conductive film remains in the forbidden region, the temperature of the forbidden region becomes higher than the central portion of the semiconductor wafer, and the chip region near the forbidden region and the chip region at the central portion of the semiconductor wafer become different. The characteristics of the semiconductor element change. For example, in a MISFET, the threshold value varies, and the depths of diffusion layers such as source and drain regions vary.
[0014]
In particular, large-diameter semiconductor wafers are often subjected to single-wafer processing, and in order to increase the throughput, rapid thermal processing (RTP: rapid thermal anneal, RTO: rapid thermal oxidation) is required. Often applied. Therefore, the temperature of the semiconductor wafer tends to be non-uniform, and distortion and device characteristics are likely to occur.
[0015]
In the case of a large-diameter semiconductor wafer, defects due to the above-described distortion and variations in element characteristics greatly affect the product yield, and there is a great need to improve these.
[0016]
An object of the present invention is to prevent a conductive film from remaining in a forbidden region of a semiconductor wafer and reduce distortion of the semiconductor wafer. Another object of the present invention is to improve the temperature uniformity of the semiconductor wafer during the heat treatment.
[0017]
Another object of the present invention is to improve the characteristics of a semiconductor device. Another object is to improve the yield of semiconductor devices.
[0018]
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0020]
According to the method of manufacturing a semiconductor device of the present invention, there is provided (a) a semiconductor substrate having a plurality of chip regions partitioned by a scribe region and having a forbidden region on an outer peripheral portion not used as the chip region. (B) forming a conductive film on the entire surface of the semiconductor substrate, and (c) forming a first pattern of the conductive film in the chip region by processing the conductive film; Forming a second pattern having a shape corresponding to the first pattern in the forbidden area.
[0021]
The semiconductor device (semiconductor wafer) of the present invention includes: (a) a semiconductor substrate having a plurality of chip regions partitioned by a scribe region, and a prohibition region not used as the chip region on an outer peripheral portion thereof; And (c) a first pattern formed in the forbidden region of the semiconductor substrate and formed of the conductive film and having a shape corresponding to the first pattern. And two patterns.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0023]
(Embodiment 1)
Hereinafter, the present embodiment will be described in detail with reference to FIGS.
[0024]
FIG. 1 is a plan view of a main part of a semiconductor wafer on which the semiconductor device of the present embodiment is formed.
[0025]
As shown in FIG. 1, the semiconductor wafer W is circular and has a plurality of substantially rectangular chip areas CA. A scribe area is formed between the chip areas CA, and the chip area CA is separated by cutting along the area. The outer peripheral portion of the semiconductor wafer W (portion outside the plurality of chip areas CA) is a prohibited area OUT in which formation of semiconductor elements and the like is prohibited. In other words, the prohibited area OUT is an area that is not used as a chip area. The forbidden region is located on the outer peripheral portion of the semiconductor wafer so as to surround the plurality of chip regions. The semiconductor wafer W may be provided with a cutout portion called an orientation flat. The diameter of the semiconductor wafer W is, for example, about 300 mm.
[0026]
Note that the chip area CA and the scribe area need not be apparently clear before manufacturing the semiconductor device. Various semiconductor elements, wirings, and the like are formed in the chip area CA.
[0027]
FIGS. 2 to 5 and FIGS. 8 to 15 are a main part sectional view and a main part plan view of a semiconductor substrate (semiconductor wafer) showing a method of manufacturing a semiconductor device of the present embodiment. CA indicates a chip area, and OUT indicates a prohibited area.
[0028]
As shown in FIG. 2, a semiconductor element is formed on a main surface of a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon. Although there are various types of semiconductor elements, a case where a capacitor C and an n-channel type MISFET (Metal Insulator Semiconductor Effect Transistor) Qn is formed will be described here.
[0029]
First, a groove is formed by etching a semiconductor substrate (semiconductor wafer) 1, and an element isolation 5 is formed by embedding, for example, a silicon oxide film as an insulating film inside the groove.
[0030]
Next, a polycrystalline silicon film 9 is deposited as a conductive film on the entire surface of the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor deposition) method. This polycrystalline silicon film 9 becomes the lower electrode E1 of the capacitive element C. The CVD apparatus used in this step is of a single wafer type, and processes the semiconductor substrates 1 one by one.
[0031]
Next, the capacitor insulating film 13 is formed on the polycrystalline silicon film 9. This capacitive insulating film is formed of, for example, a laminated film of a thin silicon oxide film, a thin silicon nitride film, and a thin silicon oxide film. For example, after the surface of the polycrystalline silicon film 9 is thermally oxidized to form a silicon oxide film, A silicon nitride film is deposited by a method, and the surface of the silicon nitride film is oxidized to form the uppermost silicon oxide film. Such a film is called an ONO film.
[0032]
Next, a photoresist film R1 is formed on the polycrystalline silicon film 9 and the capacitor insulating film 13. This photoresist film is of a positive type, and a region irradiated with light (exposed) is easily dissolved in a developing solution. A positive photoresist film is suitable for fine processing.
[0033]
Next, using a photomask (resist mask, reticle) FM, an area other than the area where the polycrystalline silicon film 9 or the like is to be left is exposed. For example, the semiconductor substrate 1 is mounted on a stage of an exposure apparatus (stepper), and the mask pattern of the photomask FM disposed thereon is sequentially transferred to a chip region of the semiconductor substrate 1. The stage is movable in XY directions.
[0034]
At this time, the transfer is also performed to the prohibited area OUT of the semiconductor substrate 1. FIG. 3 shows the relationship between the semiconductor substrate (wafer W) 1 and the area where the photomask has been transferred. The white square in the figure is the area where the photomask was transferred. The transfer may be repeated for each of a plurality of chip areas (including the prohibited area).
[0035]
Next, as shown in FIG. 4, the photoresist film R1 is developed, and the polysilicon film 9 and the like are etched using the remaining photoresist film R1 as a mask to form the lower electrode E1 and the capacitor insulating film 13. Note that the exposure and development steps of the photoresist film are referred to as a photolithography step.
[0036]
At this time, since the mask pattern is also transferred to the photoresist film R1 on the forbidden region OUT, a pattern (dummy pattern) E1d having a shape corresponding to the lower electrode E1 of the chip region CA is also formed on the forbidden region OUT. You. Of course, in the forbidden region OUT, the same area as the single chip region is not ensured. Therefore, in some places, the same pattern as the lower electrode E1 may be formed in some places, but a pattern in which a part thereof is missing is formed. In some places.
[0037]
As described above, according to the present embodiment, since the photomask is transferred also in the forbidden region OUT in the same manner as the chip region CA, a dummy pattern E1d having a shape corresponding to the lower electrode E1 in the chip region CA is formed. . FIG. 5 schematically shows a cross-sectional view of the semiconductor substrate (semiconductor wafer) of the present embodiment.
[0038]
On the other hand, when the photomask is transferred only to the chip area CA, as shown in FIGS. 6 and 7, the polycrystalline silicon film 9 and the like remain over the entire forbidden area OUT. FIG. 6 is a cross-sectional view schematically showing a semiconductor substrate during a manufacturing process of a semiconductor device for explaining the effect of the present embodiment, and FIG. 7 is a plan view. Note that the description of the pattern of the lower electrode E1 in the chip area CA in FIG. 7 is omitted.
[0039]
As described above, when the polycrystalline silicon film 9 remains over the entire forbidden region OUT, the semiconductor wafer (semiconductor substrate) W is deformed due to the film stress, which adversely affects a later process. For example, this may cause a focus failure in a subsequent photolithography process or a suction failure of a semiconductor wafer in various processing apparatuses. Further, as the deformation of the semiconductor wafer progresses, it may cause cracking. In addition, deformation (strain) of the semiconductor wafer causes dislocations and crystal defects of atoms (for example, Si) constituting the semiconductor wafer, which causes a leak current and deteriorates device characteristics.
[0040]
Further, if the heat treatment is performed in a state where the conductive film remains in the forbidden region, the temperature of the forbidden region becomes higher than the central portion of the semiconductor wafer, and the chip region near the forbidden region and the chip region at the central portion of the semiconductor wafer become different. The characteristics of the semiconductor element change. For example, variations in the characteristics of the MISFET occur in a step of forming a gate oxide film 15 described later, a step of thermally diffusing impurities forming the source and drain regions, and the like.
[0041]
On the other hand, in the present embodiment, since the photomask is transferred also in the forbidden region OUT in the same manner as in the chip region CA, the deformation (distortion) of the semiconductor wafer is reduced, and the temperature of the semiconductor wafer during the heat treatment is made uniform. Can be enhanced. As a result, characteristics of the semiconductor device can be improved, and the yield of the semiconductor device can be improved. Further, stable production of semiconductor devices can be achieved.
[0042]
Next, the photoresist film R1 is removed, and as shown in FIG. 8, a p-type impurity is ion-implanted into the semiconductor substrate 1, and then the impurity is diffused by heat treatment to form a p-type well 7. Further, an impurity for adjusting the threshold value of the MISFET is ion-implanted into the surface of the p-type well 7 (channel implantation).
[0043]
Next, a gate oxide film (gate insulating film) 15 is formed on the surface of the p-type well 7 by, for example, thermal oxidation (RTO). This thermal oxidation device (RTO device) is also a single wafer type, and processes the semiconductor substrate 1 one by one. For example, the temperature is raised in about 2 to 3 seconds after the semiconductor substrate is set in the apparatus, the temperature in the apparatus is set to about 1000 ° C., and then heat treatment is performed for about 1 minute. As described above, according to the RTO apparatus, the temperature inside the apparatus can be rapidly increased using a lamp or the like. As a result, the time required for processing one semiconductor substrate can be reduced to about 2 minutes, and the processing throughput can be improved.
[0044]
Further, in this step, since the same dummy pattern E1d as that of the chip area CA is merely formed in the forbidden area OUT, it is possible to prevent the temperature of the semiconductor wafer from becoming non-uniform, and to prevent the semiconductor wafer from being deformed or deformed. Variation in element characteristics (for example, the impurity already implanted, for example, the impurity concentration of channel implants or wells, and, although not shown, the variation in the characteristics of various elements formed before forming the lower electrode E1) ) Can be prevented.
[0045]
For example, a substance having a small specific heat (c) tends to warm. The specific heat (c) is the amount of heat required to raise a substance having a mass of 1 g by 1 ° C., and the unit is [J / g · K]. For example, the specific heat of silicon (Si) is 0.71, which is almost the same for polycrystalline silicon. In contrast, aluminum (Al) is 0.90. Therefore, Si is easier to warm than Al. The specific heat of water is 4.22.
[0046]
On the other hand, the heat capacity (Q) can be represented by the product of the specific heat (c) and its mass (M). Therefore, as the number of films remaining in the forbidden area increases, the heat capacity increases and the temperature of the film increases.
[0047]
Therefore, as described with reference to FIG. 6 and FIG. 7, when the polycrystalline silicon film 9 remains over the entire forbidden region OUT, its mass becomes larger than that of the chip region CA, so that the heat capacity becomes larger. Become. Therefore, the temperature of the forbidden area OUT increases. In particular, a semiconductor wafer having a large diameter (for example, a diameter of 300 mm) has a larger circumference, so that more films remain in the forbidden area. As a result, the temperature of the forbidden area of the semiconductor wafer increases.
[0048]
On the other hand, according to the present embodiment, since the mask pattern is also transferred to the photoresist film on the forbidden region OUT, the heat capacity per unit area is substantially the same for the forbidden region and the chip region. As a result, unevenness in the temperature of the semiconductor wafer can be suppressed.
[0049]
Next, as shown in FIG. 9, a polycrystalline silicon film 17 is deposited as a conductive film on the entire surface of the semiconductor substrate 1 including the upper portion of the gate oxide film 15 by, for example, a CVD method. This polycrystalline silicon film 17 becomes the gate electrode G of the n-channel MISFET Qn and the upper electrode E2 of the capacitive element C. The CVD apparatus used in this step is also a single wafer type, and processes the semiconductor substrates 1 one by one.
[0050]
Next, a positive photoresist film R2 is formed on the polycrystalline silicon film 17, and a region other than the region where the polycrystalline silicon film is to be left is exposed using a photomask. At this time, the transfer is also performed on the prohibited area of the semiconductor substrate 1 (see FIG. 3).
[0051]
Next, the photoresist film R2 is developed, and the polycrystalline silicon film 17 is etched using the remaining photoresist film R2 as a mask to form a gate electrode G and an upper electrode E2 (FIG. 10).
[0052]
At this time, since the mask pattern is also transferred to the photoresist film R2 on the forbidden region OUT, a pattern (dummy pattern) Gd having a shape corresponding to the gate electrode G in the chip region and the upper electrode E2 are also formed on the forbidden region OUT. A pattern (dummy pattern) E2d having a shape corresponding to the above is formed. Of course, in the forbidden region OUT, the same area as the single chip region is not ensured, and there are some places where exactly the same pattern as the gate electrode G and the upper electrode E2 is formed, but a part thereof is missing. There are also places where patterns are formed.
[0053]
As described above, according to the present embodiment, the photomask is transferred also in the forbidden region OUT in the same manner as in the chip region CA, so that the dummy pattern Gd having a shape corresponding to the gate electrode G and the upper electrode E2 in the chip region, E2d is formed.
[0054]
As described above, since the photomask was transferred to the forbidden region OUT in the same manner as the formation of the gate electrode G in the same manner as in the formation of the chip region CA, the deformation (distortion) of the semiconductor wafer was similar to the formation of the lower electrode E1 and the like. ), And the temperature uniformity of the semiconductor wafer during the heat treatment can be improved. As a result, characteristics of the semiconductor device can be improved, and the yield of the semiconductor device can be improved. Further, stable production of semiconductor devices can be achieved.
[0055]
Through the steps so far, the capacitive element C including the lower electrode E1, the capacitive insulating film 13, and the upper electrode E2 is formed in each chip area CA. In the forbidden region OUT, a dummy capacitance element Cd composed of the dummy pattern E1d, the capacitance insulating film 13, and the dummy pattern E2d is formed.
[0056]
Next, the photoresist film is removed, an n-type impurity is ion-implanted into the p-type well 7 on both sides of the gate electrode G, and thermal diffusion described later is performed to perform n-type impurity. ⁻ A type semiconductor region 21 is formed.
[0057]
Next, after a silicon nitride film 19 is deposited as an insulating film on the entire surface of the semiconductor substrate 1 including the upper portion of the gate electrode G and the capacitor C by, for example, a CVD method, anisotropic etching is performed as shown in FIG. As a result, the side wall film 19s is formed on the side wall of the gate electrode G and the like.
[0058]
Next, an n-type impurity is ion-implanted into the p-type well 7 and the impurity is thermally diffused by RTA to thereby form n-type impurity. ⁺ The type semiconductor region 23 (source, drain) is formed. Here, in the forbidden region OUT, ion implantation of impurities is not performed.
[0059]
The heat diffusion device (RTA device) used at this time is also a single wafer type, and processes the semiconductor substrates 1 one by one.
[0060]
Also in this step, since the same dummy pattern E1d and the same dummy patterns Gd and E2d as the chip area CA are formed in the forbidden area OUT, the temperature of the semiconductor wafer can be prevented from becoming uneven, and the semiconductor wafer can be prevented from becoming uneven. And variations in element characteristics (for example, variations in the impurity concentration already implanted and the characteristics of various elements) can be prevented.
[0061]
Through the steps so far, an n-channel MISFET Qn having a source and a drain having an LDD (Lightly Doped Drain) structure is formed. Note that a p-channel MISFET may be formed in addition to the n-channel MISFET Qn. The p-channel MISFET can be formed in the same manner as the n-channel MISFET Qn except that the conductivity type of the impurity to be implanted is different, and therefore the description thereof is omitted.
[0062]
Next, as shown in FIG. 12, after a silicon oxide film 25 is deposited as an insulating film on the n-channel MISFET Qn and the capacitor C by, for example, a CVD method, the surface of the silicon oxide film 25 is subjected to chemical mechanical polishing (CMP; Chemical). The surface is flattened by polishing by a mechanical polishing method.
[0063]
Then, n ⁺ Etching the silicon oxide film 25 on the semiconductor region 23 using photolithography ⁺ A contact hole C1 is formed on the mold semiconductor region 23.
[0064]
Next, after a titanium nitride (TiN) film is deposited as a barrier film on the silicon oxide film 25 including the inside of the contact hole C1, a tungsten (W) film is deposited as a conductive film. The plug P1 is formed in the contact hole C1 by polishing by a CMP method until the metal is exposed. At this time, the dummy plug P1d is similarly formed in the forbidden region OUT.
[0065]
Next, as shown in FIG. 13, a W film is deposited as a conductive film on the silicon oxide film 25 including the plug P1, and the first layer wiring M1 is formed by etching using a photolithography technique.
[0066]
At this time, also in the prohibited area OUT, the dummy wiring M1d is formed as in the chip area CA. As a result, similarly to the formation of the lower electrode E1 and the like, the deformation (strain) of the semiconductor wafer can be reduced, and the temperature uniformity of the semiconductor wafer during the heat treatment can be increased.
[0067]
Next, as shown in FIG. 14, a silicon oxide film 27 is deposited as an insulating film on the first layer wiring M1 and the like by, for example, a CVD method, and the upper part is planarized by polishing by a CMP method.
[0068]
Next, a contact hole C2 is formed on the first layer wiring M1, and a plug P2 is formed therein. The plug P2 is formed, for example, similarly to the plug P1.
[0069]
Next, a TiN film, for example, is deposited as a barrier film on the plug P2, and an aluminum (Al) film is deposited thereon as a conductive film. Next, the second layer wiring M2 is formed by etching these films using photolithography technology.
[0070]
Further, as shown in FIG. 15, a silicon oxide film 29, a plug P3 and a third layer wiring M3 are formed, and further, a silicon oxide film 31, a plug P4 and a fourth layer wiring M4 are formed. The silicon oxide films 29 and 31 can be formed similarly to the silicon oxide film 27 and the like, and the plugs P3 and P4 can be formed similarly to the plug P1 and the like. Also, the third and fourth layer wirings M3 and M4 can be formed in the same manner as the second layer wiring M2.
[0071]
Here, in the prohibited area OUT, the plugs P2, P3, P4 and the wirings M2, M3, M4 are not formed.
[0072]
Needless to say, in the forbidden region OUT, ion implantation of impurities, formation of plugs and wiring, and the same processing as in the chip region may be performed.
[0073]
However, these processes involve a photolithography process, and repetition of exposure (shot) even in the prohibited area lowers the throughput of the process.
[0074]
Therefore, it is desirable to perform the minimum necessary processing in the prohibited area OUT. Therefore, the ion implantation step is not performed. Further, in the steps after the second layer wiring M2 containing Al as a main component, a high-temperature heat treatment step is not performed, and thus, in this embodiment, the processing of the prohibited region OUT is not performed.
[0075]
In particular, a process that requires processing of the forbidden region OUT is a processing step of the polycrystalline silicon film. As described above, the polycrystalline silicon film has a low specific heat and thus tends to be heated to a high temperature, and the semiconductor substrate is likely to be distorted. Further, in particular, the processing of the gate electrode using the polycrystalline silicon film also requires the processing of the forbidden region OUT. After the processing of the gate electrode, there is a step of thermally diffusing the impurities constituting the source and drain regions and the like, which tends to cause a variation in the temperature of the semiconductor substrate.
[0076]
As described above, it is desirable to appropriately select the presence or absence of the processing in the forbidden region OUT based on the stress and specific heat of the formed film itself, the presence or absence of the subsequent heat treatment step, and the like.
[0077]
Thereafter, a multilayer wiring may be formed on the fourth-layer wiring M4 by repeating the formation of the insulating film, the plug, and the wiring.
[0078]
In addition, a protective film is formed on the uppermost layer wiring, and after a semiconductor substrate in a wafer state is diced along the scribe area, individual chips are mounted and a product is completed. Illustration is omitted.
[0079]
In this embodiment, the case where the MISFET and the capacitor C are formed has been described in detail. In addition, a DRAM memory cell including an information transfer MISFET and an information storage capacitor connected in series to the MISFET is described. Etc. may be formed.
[0080]
In this case, for example, an information storage capacitor is formed between the first layer wiring M1 and the second layer wiring M2. A thermal load is also applied during annealing (heat treatment) of the capacitive insulating film of the information storage capacitor element, which causes distortion of the semiconductor wafer and variation in element characteristics. Therefore, by forming a dummy pattern in the forbidden area as in the present embodiment, the above-mentioned problem can be solved.
[0081]
FIG. 16 is a plan view schematically showing a semiconductor substrate of the semiconductor device of the present embodiment. As shown, a dummy chip DC on which a dummy pattern is formed is formed in the prohibited area OUT.
[0082]
(Embodiment 2)
In the first embodiment, when the lower electrode E1 is formed, the photomask is transferred to the forbidden region OUT in the same manner as the chip region CA to form the dummy pattern E1d. However, the photomask is not transferred to the forbidden region OUT. The polycrystalline silicon film located at a predetermined distance from the edge of the semiconductor wafer in the prohibited area may be removed.
[0083]
Note that detailed description of the same steps as those in Embodiment 1 is omitted.
[0084]
As shown in FIG. 17, similar to the first embodiment, an element isolation 5 is formed, a polycrystalline silicon film 9 is deposited as a conductive film over the entire surface of the semiconductor substrate 1 by, for example, a CVD method, and then ONO is formed as an insulating film. A capacitive insulating film 13 made of a film is formed, a positive photoresist film R1 is formed on these films, and the pattern of the photomask FM is sequentially transferred to the chip area CA of the semiconductor substrate 1.
[0085]
At this time, if the reticle pattern is not transferred to the photoresist film R1 on the forbidden region OUT, the polycrystalline silicon film 9 remains on the entire forbidden region OUT as described with reference to FIGS. Resulting in.
[0086]
Therefore, after the exposure of the chip area CA is completed, for example, as shown in FIG. 18, the semiconductor wafer W is rotated while irradiating the end of the photoresist film on the forbidden area OUT with exposure light, thereby forming the forbidden area. The photoresist film located at a predetermined distance from the edge of the semiconductor wafer (the outer peripheral portion of the prohibited area) is exposed. For example, in the case of a semiconductor wafer having a diameter of 300 mm, at least 3 mm from the end of the semiconductor wafer is a prohibited area, so that exposure can be performed with a width of 3 mm.
[0087]
As a result, the photoresist film R1 at the end of the forbidden region OUT is removed (see FIG. 17), and the polysilicon film 9 and the like are etched using the photoresist film R1 as a mask. By this etching, as shown in FIGS. 19 and 20, the polycrystalline silicon film 9 and the like are removed with a width of about 3 mm from the end of the forbidden region OUT, and the film stress is reduced. Further, it is possible to reduce the temperature variation of the semiconductor wafer in the subsequent step of forming a gate oxide film, the step of diffusing impurities, and the like. FIG. 18 is a perspective view schematically showing a state of exposure of the forbidden area of the semiconductor device of the present embodiment. FIG. 19 is a cross-sectional view schematically showing a semiconductor substrate in a manufacturing process of the semiconductor device of the present embodiment, and FIG. 20 is a plan view thereof.
[0088]
Also, when the upper electrode E2 and the gate electrode G are formed, the reticle pattern is not transferred to the forbidden region OUT, and the polycrystalline silicon film located on the outer peripheral portion of the forbidden region is removed in the same manner as when the lower electrode E1 is formed. Is also good. In other words, the polycrystalline silicon film may be left only in the forbidden region other than the outer peripheral portion.
[0089]
(Embodiment 3)
In the present embodiment, a polycrystalline silicon film or the like is deposited on the back surface of a semiconductor wafer to reduce film stress and variations in the temperature of the semiconductor wafer. Note that detailed description of the same steps as those in Embodiment 1 is omitted.
[0090]
FIG. 21 is a cross-sectional view schematically showing a semiconductor substrate during a manufacturing process of the semiconductor device of the present embodiment.
[0091]
As shown in the figure, for example, after a polycrystalline silicon film PS is formed on the front surface of the semiconductor wafer W, the polycrystalline silicon film PS is also formed on the back surface.
[0092]
Specifically, after forming the polycrystalline silicon film 17 for forming the gate electrode G and the upper electrode E2 of the first embodiment, the reticle pattern is sequentially transferred to the chip region of the semiconductor substrate 1. At this time, the reticle pattern is not transferred to the photoresist film on the prohibited area OUT.
[0093]
Thereafter, as shown in FIG. 22, the polysilicon film 17 is etched to form the gate electrode G and the upper electrode E2, and the silicon nitride film 19 serving as the sidewall film 19s is formed as in the first embodiment. It is formed on the entire surface of the semiconductor substrate 1.
[0094]
Next, a polycrystalline silicon film 17R is formed on the back surface of the semiconductor wafer, with the surface (front surface) of the semiconductor wafer on which the silicon nitride film 19 is formed facing downward.
[0095]
Thereafter, the silicon nitride film 19 is anisotropically etched with the formation surface (front surface) of the silicon nitride film 19 of the semiconductor wafer facing upward to form a sidewall film 19s on the side wall of the gate electrode G and the like (FIG. 23). . 22 and 23 are cross-sectional views of main parts of a semiconductor substrate (semiconductor wafer) illustrating the method of manufacturing a semiconductor device according to the present embodiment.
[0096]
As described above, according to the present embodiment, since the polycrystalline silicon film 17R is also formed on the back surface of the semiconductor wafer, the difference in film stress between the front surface and the back surface of the semiconductor wafer can be reduced. For example, also in the thermal oxidation process and the thermal diffusion process, the temperature variation of the semiconductor wafer can be reduced by the polycrystalline silicon film 17R on the back surface. As a result, it is possible to reduce the distortion of the semiconductor wafer and the variation in element characteristics formed on the main surface.
[0097]
In the single-wafer processing, since it is difficult to form a film on the back surface, the film needs to be formed with the back surface of the semiconductor wafer facing upward.
[0098]
Further, the formation of the polysilicon film 17R may be performed before the formation of the polysilicon film 17 or may be performed immediately after the formation of the polysilicon film 17. However, since the polycrystalline silicon film 17 is a film that becomes the gate electrode G and the upper electrode E2, the surface may be contaminated if the processing is performed with the formed surface on the lower side. Therefore, as described above, it is desirable to form the polycrystalline silicon film 17R at the timing when the surface is covered with the insulating film or the like.
[0099]
Further, when the lower electrode E1 is formed, the photomask may not be transferred to the forbidden region OUT, and a polycrystalline silicon film may be formed on the back surface of the semiconductor wafer as in the case of forming the gate electrode G.
[0100]
(Embodiment 4)
In the third embodiment, the polycrystalline silicon film is formed on the back surface of the semiconductor wafer. However, this film may be processed in the same manner as the polycrystalline silicon film on the front surface. Note that detailed description of the same steps as those in Embodiment 3 and the like is omitted.
[0101]
FIG. 24 is a cross-sectional view schematically showing a semiconductor substrate (semiconductor wafer) during a manufacturing process of the semiconductor device of the present embodiment.
[0102]
As shown in the drawing, for example, a polycrystalline silicon film is formed on the front surface of the semiconductor wafer W, and after forming a pattern P, a polycrystalline silicon film is also formed on the back surface. Patterning is performed similarly to the polycrystalline silicon film. In other words, the dummy pattern DP is formed at a position corresponding to the chip region on the back surface of the semiconductor wafer. Note that PS indicates a polycrystalline silicon film remaining in the forbidden region OUT.
[0103]
Specifically, as described in the third embodiment, after the polycrystalline silicon film 17R is formed, the reticle pattern is sequentially transferred to the chip region on the back surface of the semiconductor substrate 1. At this time, the reticle pattern is not transferred to the photoresist film on the prohibited area OUT. Thereafter, the photoresist film is developed, and the polysilicon film 17R is etched using the photoresist film as a mask to form a dummy pattern DP.
[0104]
As described above, according to the present embodiment, since the pattern (DP) having the same shape as the front surface is formed on the back surface of the semiconductor wafer, the difference in film stress between the front surface and the back surface of the semiconductor wafer can be reduced. In a subsequent heat treatment step (for example, a thermal oxidation step or a thermal diffusion step), the temperature variation of the semiconductor wafer can be reduced by the pattern (DP) on the back surface. As a result, it is possible to reduce the distortion of the semiconductor wafer and the variation in element characteristics formed on the main surface. In order to further reduce the temperature variation of the semiconductor wafer, it is better to transfer the reticle pattern to the photoresist film on the prohibited area OUT.
[0105]
In the single-wafer processing, since it is difficult to form a film on the back surface, it is necessary to intentionally form a pattern (DP) with the back surface of the semiconductor wafer facing upward.
[0106]
Also, when forming the lower electrode E1, as described above, a dummy pattern made of a polycrystalline silicon film may be formed on the back surface of the semiconductor wafer.
[0107]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0108]
In particular, in the above-described embodiment, a polycrystalline silicon film has been described as an example. However, the present invention can be widely applied to other films (especially, conductive films) in which film stress and heat capacity increase. In addition, the thermal oxidation process and the thermal diffusion process have been described as examples of the heat treatment process, but the present invention can be widely applied to processes in which a thermal load is applied.
[0109]
Further, in the above-described embodiment, the same pattern as the chip area is used as the dummy pattern, but a different pattern having the same film stress and heat capacity may be used.
[0110]
In the above embodiment, the MISFET has been described as an example. However, the present invention can be applied to a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) using the MISFET. Further, the present invention can be widely applied to a semiconductor device using a film (especially, a conductive film) having a large film stress or heat capacity, such as a nonvolatile memory.
[0111]
Further, a semiconductor device having a plurality of layers of conductive films may be applied in combination with each embodiment.
[0112]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0113]
The distortion of the semiconductor wafer can be reduced by reducing the remaining conductive film in the prohibited area of the semiconductor wafer. Further, the temperature uniformity of the semiconductor wafer during the heat treatment can be improved.
[0114]
Further, characteristics of the semiconductor device can be improved. Further, the yield of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a main part plan view of a semiconductor wafer on which a semiconductor device according to a first embodiment of the present invention is formed;
FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a plan view of a main part of a semiconductor substrate (semiconductor wafer) illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 6 is a cross-sectional view schematically showing a semiconductor substrate during a manufacturing process of the semiconductor device for describing the effect of the first embodiment of the present invention.
FIG. 7 is a plan view schematically showing a semiconductor substrate during a manufacturing process of the semiconductor device, for describing an effect of the first embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate (semiconductor wafer) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 16 is a plan view schematically showing a semiconductor substrate of the semiconductor device according to the first embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate (semiconductor wafer) for illustrating a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention;
FIG. 18 is a perspective view schematically showing a manner of exposing a forbidden region of the semiconductor device according to the second embodiment of the present invention;
FIG. 19 is a cross-sectional view schematically showing a semiconductor substrate during a manufacturing process of the semiconductor device according to the second embodiment of the present invention;
FIG. 20 is a plan view schematically showing a semiconductor substrate during a manufacturing process of the semiconductor device according to the second embodiment of the present invention;
FIG. 21 is a cross-sectional view schematically showing a semiconductor substrate during a manufacturing process of the semiconductor device according to the third embodiment of the present invention;
FIG. 22 is an essential part cross sectional view of a semiconductor substrate (semiconductor wafer) for illustrating a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention;
FIG. 23 is a fragmentary cross-sectional view of a semiconductor substrate (semiconductor wafer) for illustrating a method of manufacturing a semiconductor device according to Third Embodiment of the present invention;
FIG. 24 is a cross-sectional view schematically showing a semiconductor substrate during a manufacturing step of the semiconductor device according to the fourth embodiment of the present invention;
[Explanation of symbols]
1 semiconductor substrate
5 Element separation
7 p-type well
9 Polycrystalline silicon film
13 Capacitive insulating film
15 Gate oxide film
17 Polycrystalline silicon film
17R Polycrystalline silicon film
19 Silicon nitride film
19s Side wall film
21 n ⁻ Type semiconductor region
23 n ⁺ Type semiconductor region
25 Silicon oxide film
27 Silicon oxide film
29 Silicon oxide film
31 Silicon oxide film
C capacitance element
C1 contact hole
C2 contact hole
CA chip area
Cd dummy capacitance element
DC dummy chip
DP dummy pattern
E1 Lower electrode
E1d dummy pattern
E2 Upper electrode
E2d dummy pattern
FM photo mask
G gate electrode
Gd dummy pattern
M1 First layer wiring
M1d dummy wiring
M2 Second layer wiring
M3 Third layer wiring
M4 4th layer wiring
OUT prohibited area
P pattern
P1 plug
P1d dummy plug
P2 plug
P3 plug
P4 plug
PS Polycrystalline silicon film
Qn n-channel type MISFET
R1 photoresist film
R2 photoresist film
FM photo mask
W semiconductor wafer

Claims (22)

(A) preparing a semiconductor substrate having a plurality of chip regions partitioned by a scribe region and having a forbidden region not used as the chip region on an outer peripheral portion thereof;
(B) forming a conductive film on the entire surface of the semiconductor substrate;
(C) forming a first pattern of the conductive film in the chip region by processing the conductive film, and forming a second pattern having a shape corresponding to the first pattern in the forbidden region; When,
A method for manufacturing a semiconductor device, comprising: The step (c) includes: (c1) a step of forming a positive photoresist film on the conductive film; and (c2) after the step (c1), using a predetermined photomask to form the chip region and (C3) after the step (c2), developing the photoresist film; and (c4) after the step (c3), 2. The method according to claim 1, further comprising the step of etching the conductive film using a photoresist film as a mask. 2. The method according to claim 1, further comprising (d) a heat treatment step after the step (c). 2. The method according to claim 1, wherein the step (d) is a step of processing the semiconductor substrates one by one. 2. The method according to claim 1, wherein the conductive film is a silicon film or a film having a lower specific heat than silicon. The conductive film is a polycrystalline silicon film, and the step (d) is a step of forming a gate oxide film of a MISFET or a step of diffusing impurities forming source and drain regions of the MISFET. The method for manufacturing a semiconductor device according to claim 3. 2. The method according to claim 1, wherein the conductive film is a polycrystalline silicon film, and the first pattern is a gate electrode of a MISFET. 2. The method according to claim 1, wherein the semiconductor substrate has a substantially circular shape and a diameter of 300 mm or more. (A) preparing a semiconductor substrate having a plurality of chip regions partitioned by a scribe region and having a forbidden region not used as the chip region on an outer peripheral portion thereof;
(B) forming a conductive film on the entire surface of the semiconductor substrate;
(C) forming a first pattern of the conductive film in the chip region by processing the conductive film, and forming the first pattern at a predetermined distance from an end of the semiconductor substrate on the forbidden region; Removing the film;
A method for manufacturing a semiconductor device, comprising: The step (c) includes (c1) a step of forming a positive photoresist film on the conductive film, and (c2) after the step (c1), using a predetermined photomask to form the chip region. Transferring a mask pattern onto the photoresist film; (c3) exposing the photoresist film located at the predetermined distance from an end of the semiconductor substrate on the forbidden area; (c4) exposing the ( after the steps c2) and (c3), a step of developing the photoresist film; and (c5) after the step (c4), etching the conductive film using the photoresist film as a mask. The method for manufacturing a semiconductor device according to claim 9, wherein: The method according to claim 9, further comprising: (d) a heat treatment step after the step (c). (A) preparing a semiconductor substrate having a plurality of chip regions partitioned by a scribe region and having a forbidden region not used as the chip region on an outer peripheral portion thereof;
(B) forming a first conductive film over the entire surface of the semiconductor substrate;
(C) forming a first pattern in the chip region by processing the first conductive film;
(D) forming a second conductive film on the entire back surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: 13. The method according to claim 12, further comprising (d) a heat treatment step after the step (c). The first conductive film is a polycrystalline silicon film, the first pattern is a gate electrode of a MISFET,
A step of forming an insulating film on the semiconductor substrate including on the gate electrode, between the steps (c) and (d);
13. The method according to claim 12, further comprising, after the step (d), forming a side wall film made of the insulating film on a side wall of the gate electrode by anisotropically etching the insulating film. A method for manufacturing a semiconductor device. 15. The method according to claim 12, further comprising: forming a second pattern having a shape corresponding to the first pattern on the back surface of the semiconductor substrate by processing the second conductive film. 13. The method for manufacturing a semiconductor device according to the above item. (A) a semiconductor substrate having a plurality of chip regions partitioned by a scribe region, and a forbidden region on the outer periphery that is not used as the chip region;
(B) a first pattern formed in the chip region of the semiconductor substrate and made of a conductive film;
(C) a second pattern formed in the forbidden region of the semiconductor substrate, made of the conductive film, and having a shape corresponding to the first pattern;
A semiconductor device comprising: 17. The semiconductor device according to claim 16, wherein the conductive film is a silicon film or a film having a lower specific heat than silicon. 17. The semiconductor device according to claim 16, wherein the conductive film is a polycrystalline silicon film, and the first pattern is a gate electrode of a MISFET. 17. The semiconductor device according to claim 16, wherein the semiconductor substrate is substantially circular and has a diameter of 300 mm or more. (A) a semiconductor substrate having a plurality of chip regions partitioned by a scribe region, and a forbidden region on the outer periphery that is not used as the chip region;
(B) a first pattern formed in the chip region of the semiconductor substrate and made of a conductive film;
(C) the conductive film formed in the forbidden region of the semiconductor substrate and formed on the forbidden region and in a region other than the outer peripheral portion at a predetermined distance from an end of the semiconductor substrate;
A semiconductor device comprising: (A) a semiconductor substrate having a plurality of chip regions partitioned by a scribe region, and a forbidden region on the outer periphery that is not used as the chip region;
(B) a first pattern formed in the chip region on the surface of the semiconductor substrate and made of a first conductive film;
(C) a second conductive film formed on the back surface of the semiconductor substrate;
A semiconductor device comprising: 22. The semiconductor device according to claim 21, wherein the second conductive film is a second pattern having a shape corresponding to the first pattern.

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