CN103632950A - A method for forming nitride films among polycrystalline silicon in a groove-type double layer grid MOS - Google Patents
A method for forming nitride films among polycrystalline silicon in a groove-type double layer grid MOS Download PDFInfo
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- CN103632950A CN103632950A CN201210297570.2A CN201210297570A CN103632950A CN 103632950 A CN103632950 A CN 103632950A CN 201210297570 A CN201210297570 A CN 201210297570A CN 103632950 A CN103632950 A CN 103632950A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 84
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 96
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000001259 photo etching Methods 0.000 claims abstract description 15
- 239000011241 protective layer Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 76
- 230000003628 erosive effect Effects 0.000 claims description 24
- 230000012010 growth Effects 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 15
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 3
- 238000006263 metalation reaction Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 230000026267 regulation of growth Effects 0.000 claims description 3
- 230000007773 growth pattern Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000000227 grinding Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000000428 dust Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for forming nitride films among polycrystalline silicon in a groove-type double layer grid MOS. The method comprises the following steps: 1), groove etching is carried out; 2), a dielectric layer grows; 3), a first layer of polycrystalline silicon grows; 4) a first step of reverse etching is carried out on the first layer of the polycrystalline silicon; 5), photoetching and a second step of reverse etching are carried out on the first layer of the polycrystalline silicon; 6), a nitride film is deposited; 7), after an HDP oxide-film is deposited, chemically mechanical polishing is carried out; 8), P-cover photoetching is carried out; 9), HDP oxide-film reverse etching is carried out; 10), the nitride film above a protective layer of the nitride film is removed; 11), a protective layer of the nitride film and the dielectric layer above the nitride film are removed; 12) a grid oxide layer grows; 13) a second layer of polycrystalline silicon is deposited and reverse etching is carried out; 14), a base electrode and a source electrode form; 15) contact apertures, metal and a passivation layer form. According to the invention, a problem that the dielectric layer between two layers of polycrystalline silicon is hard to control is solved, and the stability of a double-layer grid power MOS device is raised.
Description
Technical field
The present invention relates to form in a kind of semiconductor applications the method for nitride film dielectric layer, particularly relate to the formation method of the nitride film dielectric layer between the two-layer polysilicon in a kind of groove type double-layer grid MOS.
Background technology
In power device, groove type double-layer grid power MOS device has the characteristic that puncture voltage is high, conducting resistance is low, conversion efficiency is high, switching speed is fast.Conventionally, ground floor polysilicon electrode is as bucking electrode and source shorted or logically draw separately, and second layer polysilicon electrode is as grid.Oxidated layer thickness between two-layer polysilicon electrode needs strict control, otherwise can form electric leakage or lower puncture voltage.
At present, the preparation method of the oxide layer between the two-layer polysilicon electrode in existing technique, it is growing high density plasma oxide film (HDP) oxide-film after ground floor polysilicon anti-carves, the HDP oxide-film of growth is wanted enough thick groove (Trench) can being filled up, carry out again CMP(cmp), photoetching, HDP oxide-film anti-carve, the HDP that finally leaves 2500 dusts on ground floor polysilicon is as the dielectric layer between two-layer polysilicon.Wherein, concrete technological process is as follows:
1) trench etching;
2) dielectric layer deposit;
3) ground floor polysilicon deposit;
4) the ground floor polysilicon first step anti-carves erosion;
5) ground floor polysilicon photoetching, ground floor polysilicon second step anti-carve erosion;
6) high-density plasma oxide-film (HDP) deposit;
7) HDP CMP(cmp) to remaining 3000 dusts;
8) wet etching makes to remain on the ground floor polysilicon in groove 2500 dust HDP;
9) growth of gate oxide layer, the deposit of second layer polysilicon, second layer polysilicon anti-carve erosion;
10) dielectric layer growth under metal;
11) contact hole dielectric layer etching, contact hole silicon etching;
12) source metal growth and etching.
Wherein, ground floor polysilicon two steps in existing technique anti-carve the primitive unit cell of the cell(MOSFET after erosion) district's sectional drawing, as shown in Figure 1; Cell district sectional drawing after HDP oxide growth, as shown in Figure 2; Cell district sectional drawing after HDP oxide film wet etching, as shown in Figure 3.
For existing technique, ground floor polysilicon is when etching depth is the following 1.15 μ m of silicon face for the second time, HDP silicon oxide deposition thickness approximately 1.5 μ m, HDP silica CMP amount of grinding approximately 1.2 μ m, due to HDP oxide growth thickness and CMP grinding thickness all very large, so the remaining thickness fluctuation after CMP is very large.In addition, CMP grinding rate there are differences between diverse location and silicon chip in silicon chip face, and this has also caused the homogeneity of the remaining thickness after CMP very poor.Above 2 cause the homogeneity of the deielectric-coating thickness between two-layer polysilicon and stability all very poor.
Because the residual thickness after CMP of the HDP oxide-film in existing technique exists, rise and fall and fluctuation, cause HDP oxide-film to anti-carve residual thickness afterwards and be difficult to control, can make like this performance of groove type double-layer grid power MOS device very unstable.Therefore, need to solve the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, to improve the stability of groove type double-layer grid power MOS device performance.
Summary of the invention
The technical problem to be solved in the present invention is to provide the formation method of the nitride film dielectric layer between the two-layer polysilicon in a kind of groove type double-layer grid MOS.By utilizing nitride film as spacer medium, can solve the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, improve the stability of groove type double-layer grid power MOS device performance.
For solving the problems of the technologies described above, the formation method of the nitride film dielectric layer between the two-layer polysilicon in groove type double-layer grid MOS of the present invention, comprises step:
1) on silicon chip, carry out etching groove;
2) inwall and the silicon chip surface at groove carries out dielectric layer growth;
Wherein, dielectric layer is oxide-film, and thickness is 500～3000 dusts; The growth pattern of dielectric layer, comprising: hot oxygen or low-pressure chemical vapor deposition mode;
3) on the dielectric layer in groove, growth regulation one deck polysilicon;
4) ground floor polysilicon is carried out to the first step and anti-carve erosion;
5) ground floor polysilicon is carried out to photoetching and second step anti-carves erosion;
Ground floor polysilicon is carried out to photoetching, protect the position that need to pick out source electrode polysilicon, remaining ground floor polysilicon position carries out that second step polysilicon is counter to be etched to below silicon face;
6) on dielectric layer and ground floor polysilicon, deposit nitride film;
7), in groove, after deposit high-density plasma (HDP) oxide-film, carry out chemico-mechanical polishing (CMP) to nitride film surface;
8) P-cover photoetching;
By in a region of definition, source electrode polysilicon extraction location limit, make ground floor polysilicon and second layer polysilicon lateral isolation in groove;
9) HDP oxide-film anti-carves erosion, exposes the nitride film of groove top and sidewall, and at channel bottom, reserve part HDP oxide-film is as the protective layer of channel bottom nitride film;
10) etching (comprising wet etching) is removed the nitride film of protective layer (the part HDP the oxide-film retaining) top of nitride film;
11) remove the protective layer (the part HDP oxide-film retaining) of nitride film and the dielectric layer of nitride film top;
Wherein, the mode of removal, can comprise: wet etching;
12) gate oxidation layer growth;
13) deposit of second layer polysilicon with anti-carve erosion;
14) form base stage (BODY) and source electrode (Source);
15) form contact hole, metal and passivation layer.
In described step 6), the method for deposit comprises: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; The material of nitride film comprises: silicon nitride; The thickness of nitride film is 500～3000 dusts.
In described step 9), anti-carve erosion for wet etching; The thickness of part HDP oxide-film is 500～2000 dusts.
The present invention is after the deposit of ground floor polysilicon, and at ground floor polysilicon surface growth one deck nitride film, this layer of nitride film is the most at last as the dielectric layer between two-layer polysilicon.Then, do the deposit of HDP oxide-film, with CMP, surperficial HDP oxide-film is polished, be parked on nitride film.Then, HDP oxide film wet etching, trench sidewall HDP oxide-film etching is clean, in bottom, leave approximately 1000 dust oxide-films as bottom nitride film protective layer.Utilize wet etching to remove groove top and sidewall nitride film, then remove top and side wall oxide film, as the bottom nitride film formation of dielectric layer between two-layer polysilicon.Owing to utilizing silicon nitride as spacer medium, isolation performance improves greatly, and does not have the unmanageable risk of HDP oxide-film; In addition, therefore silicon nitride can also, solve the unmanageable problem of thickness of dielectric layers between two-layer polysilicon as the suspension layer (stop layer) of CMP, improves the stability of groove type double-layer grid power MOS device performance.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is that ground floor polysilicon two steps in existing technique anti-carve erosion cell district sectional drawing afterwards;
Fig. 2 is cell district sectional drawing after the HDP oxide growth in existing technique;
Fig. 3 is cell district sectional drawing after the HDP oxide film wet etching in existing technique;
Fig. 4 is the cell district sectional drawing after the ground floor polysilicon surface nitride film growth in the present invention;
Fig. 5 is the cell district sectional drawing that after the HDP oxide growth in the present invention, CMP is milled to nitride film surface
Fig. 6 is cell district sectional drawing after the HDP oxide film wet etching in the present invention;
Fig. 7 is cell district sectional drawing after removal groove top in the present invention and sidewall nitride film;
Fig. 8 is cell district sectional drawing after removal groove top in the present invention and side wall medium floor and HDP oxide-film.
Embodiment
The formation method of the nitride film dielectric layer between the two-layer polysilicon in the groove type double-layer grid MOS in the present invention, comprises step:
1) on silicon chip, carry out etching groove;
2) adopt hot oxygen or low-pressure chemical vapor deposition mode, at trench wall and silicon chip surface, carry out oxide film dielectric layer growth, thickness is 500～3000 dusts;
3) on the dielectric layer in groove, by low-pressure chemical vapor deposition, growth regulation one deck polysilicon, wherein, the thickness of ground floor polysilicon is enough to fill up groove inside;
4) ground floor polysilicon is carried out to the first step and anti-carve erosion, until be etched to silicon face;
5) ground floor polysilicon is carried out to photoetching, protect the position that need to pick out source electrode polysilicon, all the other positions are carried out second step and are anti-carved erosion, until be etched to the following desired depth of silicon face (certain depth);
Wherein, above-mentioned steps 1)-5) can carry out according to existing technique, the cell district sectional drawing that ground floor polysilicon two steps anti-carve after erosion can be as shown in Figure 1;
6) on dielectric layer and ground floor polysilicon, by as the mode of low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, deposit nitride film, i.e. silicon nitride (as shown in Figure 4), thickness is 500～3000 dusts;
7) in groove, deposit high-density plasma (HDP) oxide-film (silica), fills up after groove completely, carries out chemico-mechanical polishing (CMP) to silicon nitride surface (as shown in Figure 5);
This step utilizes silicon nitride as CMP suspension layer, and CMP can accurately rest on flute surfaces;
8) P-cover photoetching, by a region of definition, source electrode polysilicon extraction location limit, makes ground floor polysilicon (source electrode polysilicon) and second layer polysilicon (grid polycrystalline silicon) lateral isolation in groove;
9) HDP oxide-film anti-carves erosion (wet etching), the silicon nitride that exposes groove top and sidewall, and at channel bottom, reserve part HDP oxide-film (thickness of part HDP oxide-film can be 500～2000 dusts) is as the protective layer (as shown in Figure 6) of channel bottom silicon nitride, and the silicon nitride of channel bottom is by HDP oxide film protection;
Wherein, HDP oxide-film anti-carves in erosion, and etch amount is fixed, and can accurately control HDP thickness on channel bottom silicon nitride, to protect bottom nitride film.
10) wet etching, removes the silicon nitride (as shown in Figure 7) of the protective layer top of silicon nitride, and the silicon nitride of flute surfaces sidewall is all etched totally, and the silicon nitride on ground floor polysilicon surface is because the HDP oxide film protection of bottom is stayed;
11) wet etching, removes the protective layer (being HDP oxide-film) of silicon nitride and the dielectric layer (as shown in Figure 8) of silicon nitride top, thereby forms the silicon nitride medium layer of channel bottom;
12), according to existing technique, utilize thermal oxide growth grid oxic horizon;
13) according to existing technique, carry out the deposit of second layer polysilicon and anti-carve erosion, utilize low-pressure chemical vapor deposition growth second layer polysilicon, be etched to silicon face;
14), according to existing technique, by Implantation, form base stage (BODY) and source electrode (Source).
15) according to existing technique, form contact hole, metal and passivation layer, utilize mask plate etching to form contact hole, deposited metal etching form contact electrode, and deposit etching form passivation layer.
According to above-mentioned steps; by after ground floor polysilicon electrode etching; at polysilicon surface growth one deck nitride film; and then growth HDP oxide-film; carrying out CMP, photoetching, HDP oxide-film anti-carves again; remove groove top and sidewall nitride film, utilize bottom HDP oxide film protection to live bottom nitride film as separator between double-deck grid MOS structure two-layer polysilicon.Owing to utilizing nitride film as spacer medium, improved isolation performance, solved the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, make integrated artistic control difficulty and effectively reduce, improve the stability of groove type double-layer grid power MOS device performance.
Claims (10)
1. a formation method for the nitride film dielectric layer between the two-layer polysilicon in groove type double-layer grid MOS, is characterized in that, comprises step:
1) on silicon chip, carry out etching groove;
2) at trench wall and silicon chip surface, carry out dielectric layer growth;
3) on the dielectric layer in groove, growth regulation one deck polysilicon;
4) ground floor polysilicon is carried out to the first step and anti-carve erosion;
5) ground floor polysilicon is carried out to photoetching and second step anti-carves erosion;
6) on dielectric layer and ground floor polysilicon, deposit nitride film;
7), in groove, after deposit high-density plasma oxide-film, be chemically mechanically polished to nitride film surface;
8) P-cover photoetching;
9) high-density plasma oxide-film anti-carves erosion, exposes the nitride film of groove top and sidewall, and at channel bottom, reserve part high-density plasma oxide-film is as the protective layer of channel bottom nitride film;
10) etching is removed the nitride film of the protective layer top of nitride film;
11) remove the protective layer of nitride film and the dielectric layer of nitride film top;
12) gate oxidation layer growth;
13) deposit of second layer polysilicon with anti-carve erosion;
14) form base stage and source electrode;
15) form contact hole, metal and passivation layer.
2. the method for claim 1, is characterized in that: described step 2), dielectric layer is oxide-film, and thickness is 500～3000 dusts;
The growth pattern of dielectric layer, comprising: hot oxygen or low-pressure chemical vapor deposition mode.
3. the method for claim 1, is characterized in that: in described step 3), the thickness of ground floor polysilicon is for being enough to fill up groove inside.
4. the method for claim 1, is characterized in that: in described step 4), when the first step anti-carves erosion, until be etched to silicon face.
5. the method for claim 1; it is characterized in that: described step 5) ground floor polysilicon is carried out to photoetching and second step anti-carves in erosion; ground floor polysilicon is carried out to photoetching; protect the position that need to pick out source electrode polysilicon; remaining ground floor polysilicon position is carried out second step polysilicon and is anti-carved erosion, until be etched to the following desired depth of silicon face.
6. the method for claim 1, is characterized in that: in described step 6), the method for deposit comprises: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition;
The material of nitride film comprises: silicon nitride; The thickness of nitride film is 500～3000 dusts.
7. method as claimed in claim 5, is characterized in that: in the P-cover photoetching of described step 8), by a region of definition, source electrode polysilicon extraction location limit, make ground floor polysilicon and second layer polysilicon lateral isolation in groove.
8. the method for claim 1, is characterized in that: in described step 9), anti-carve erosion for wet etching; The thickness of part high-density plasma oxide-film is 500～2000 dusts.
9. the method for claim 1, is characterized in that: in described step 10), etching comprises: wet etching.
10. the method for claim 1, is characterized in that: in described step 11), the mode of removal, comprising: wet etching.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104517824A (en) * | 2014-08-01 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of groove type bilayer gate |
| CN105914234A (en) * | 2016-06-28 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Separating gate power MOS transistor structure and manufacturing method therefor |
| CN113745337A (en) * | 2021-07-19 | 2021-12-03 | 四川遂宁市利普芯微电子有限公司 | Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) with shielded gate trench |
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| CN113745337B (en) * | 2021-07-19 | 2022-11-11 | 深圳利普芯微电子有限公司 | Manufacturing method of shielded gate trench MOSFET |
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