CN102130003A - Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device - Google Patents
Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device Download PDFInfo
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- CN102130003A CN102130003A CN2010100273180A CN201010027318A CN102130003A CN 102130003 A CN102130003 A CN 102130003A CN 2010100273180 A CN2010100273180 A CN 2010100273180A CN 201010027318 A CN201010027318 A CN 201010027318A CN 102130003 A CN102130003 A CN 102130003A
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- contact hole
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- longitudinal groove
- nitrogen ion
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Abstract
The invention discloses a preparation method of a vertical trench MOS (Metal Oxide Semiconductor) device. The preparation method comprises the following steps of: after a trench of the vertical trench MOS device is formed, carrying out ion implantation so as to implant nitrogen ions into the lateral wall of the upper part of the trench; and after a contact hole of the vertical groove MOS device is etched, carrying out ion implantation to form a contact hole implantation region below the contact hole, wherein the contact hole implantation region extends into a drift region from a body region, and the conduction type of the contact hole implantation region is same as the conduction type of the body region. Through adopting the preparation method, the breakdown voltage of the prepared vertical trench MOS device can be improved.
Description
Technical field
The present invention relates to a kind of longitudinal groove MOS preparation of devices method.
Background technology
Longitudinal groove MOS is popular at present power device, and the forward conduction resistance of trying one's best low and the high puncture voltage of trying one's best are designs and make the target of pursuing.Existing a kind of longitudinal groove MOS device architecture as shown in Figure 1, its trenched side-wall bottom and bottom gate oxide thickness are greater than the gate oxide thickness of two upper lateral parts.Groove preparation method in this device is first etching groove, and in groove growing silicon oxide and silicon nitride successively; Then etching is removed the silicon nitride and the silica of channel bottom; Then further carry out etching groove, make the gained groove darker; And then be the part trench wall localized oxidation of silicon of institute's etching second time, form thick silicon oxide layer at channel bottom and bottom, two side; Remove silicon nitride and partial oxidation silicon at last.Have the puncture voltage height of the puncture voltage of this structure trench device than the trenched mos transistor of general structure.
Summary of the invention
Technical problem to be solved by this invention provides a kind of longitudinal groove MOS preparation of devices method, and it can improve the puncture voltage of longitudinal groove MOS device.
For solving the problems of the technologies described above, longitudinal groove MOS preparation of devices method of the present invention for after the groove formation of longitudinal groove MOS device, is carried out the nitrogen ion and is injected the sidewall surfaces that the nitrogen ion is injected into described groove top; And after the contact hole etching of longitudinal groove MOS device, carry out ion implantation technology and below contact hole, form the contact hole injection region, described contact hole injection region extends in the drift region from the tagma, and the conduction type of contact hole injection region is identical with the conduction type in tagma.
In the method for the present invention, nitrogen is injected into groove top, make when carrying out gate oxidation, the groove upper portion side wall is because the existence of nitrogen generates silicon oxynitride, rather than the silicon dioxide in the existing structure, nitrification dangling bonds at the interface, make interfacial state tail off, improve carrier mobility, thereby reduce forward conduction resistance.By the existence of contact hole injection region, mean in drift region and introduce PN junction simultaneously, utilize the PN junction depletion region to share more pressure drop, thereby reach the purpose that improves device electric breakdown strength.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of traditional longitudinal groove MOS device;
Fig. 2 is for adopting the structural representation of the prepared longitudinal groove MOS device of method of the present invention;
Fig. 3 is for implementing the schematic diagram that the nitrogen ion injects in the method for the present invention;
Fig. 4 is for implementing the structural representation after the oxidation in the method for the present invention;
Fig. 5 is for implementing the structural representation behind the formation grid polycrystalline silicon in the method for the present invention;
Fig. 6 is for implementing the structural representation behind the formation contact hole injection region in the method for the present invention.
Embodiment
Longitudinal groove MOS preparation of devices method of the present invention, after the longitudinal groove etching is finished, before photoresist is peeled off, increase and carry out nitrogen ion injection (see figure 3), make the nitrogen ion be injected into the sidewall surfaces on groove top, and trenched side-wall bottom and channel bottom do not have the nitrogen ion and inject.The degree of depth of the trenched side-wall that the nitrogen ion injects is preferably more than the degree of depth in the tagma of follow-up formation.Inject at this step nitrogen ion, the dosage that the nitrogen ion injects is for being 10
11～10
16Atom/cm
2, the injection energy is: 1～2000KeV, the angle of nitrogen ion beam and substrate vertical axis is 0～90 °.After the nitrogen ion injects, peel photoresist off, carry out gate oxidation.Because groove upper portion side wall surface has nitrogen to exist, when gate oxidation, groove top oxidation rate is slower, formation be silicon oxynitride; And groove lower sides and channel bottom do not have the existence of nitrogen, and oxidation rate can be fast, formation be silicon dioxide.The silicon oxynitride layer that final formation groove top forms is thinner, and groove bottom and channel bottom form the thicker (see figure 4) of silicon dioxide layer.Afterwards groove is carried out polysilicon and fill, form grid polycrystalline silicon lines (see figure 5), as the grid of MOS.
Then form tagma and source region by common process by photoetching and ion injection, film between illuvium then forms contact hole by photoetching and etching again, carries out ion beam then and is infused in contact hole below formation contact hole injection region (see figure 6).For NMOS, the doping of N type is carried out in the source region, and the doping of P type is carried out in the tagma, and the doping of P type is carried out in the contact hole injection region, and the drift region is a N type extension, and silicon substrate is a N type heavy doping epitaxial silicon chip.For PMOS, the doping of P type is carried out in the source region, and the doping of N type is carried out in the tagma, and the doping of N type is carried out in the contact hole injection region, and the drift region is a P type extension, and silicon substrate is a P type heavy doping epitaxial silicon chip.The ionic species that is injected can be: phosphorus (P), boron (B), boron difluoride (BF2), arsenic (As); The dosage that injects ion is 10
11～10
16Atom/cm
2, the injection energy is: 1～2000KeV, the angle of nitrogen ion beam and substrate vertical axis is 0～90 °.
The integrated circuit postchannel process of employing standard forms the source metal electrode of wafer frontside.The wafer rear depositing metal forms the drain metal electrode behind the chemical wet etching, the final longitudinal groove MOS device that forms as shown in Figure 2.This longitudinal groove MOS device has low forward conduction resistance, and therefore the power MOS (Metal Oxide Semiconductor) device of high-breakdown-voltage has more improved the overall performance of circuit.
Claims (4)
1. a longitudinal groove MOS preparation of devices method is characterized in that: after the groove of described longitudinal groove MOS device forms, carry out the nitrogen ion and inject the sidewall surfaces that the nitrogen ion is injected into described groove top; And after the contact hole etching of described longitudinal groove MOS device, carry out ion implantation technology and below contact hole, form the contact hole injection region, described contact hole injection region extends in the drift region from the tagma, and the conduction type of described contact hole injection region is identical with the conduction type in described tagma.
2. longitudinal groove MOS preparation of devices method according to claim 1 is characterized in that: the sidewall degree of depth that described nitrogen ion injects is greater than the degree of depth in the tagma of follow-up formation.
3. longitudinal groove MOS preparation of devices method according to claim 1 and 2 is characterized in that: the step that described nitrogen ion injects, the implantation dosage of described nitrogen ion is 10
11～10
16Atom/cm
2, the injection energy is: 1～2000KeV, the angle of nitrogen ion beam and substrate vertical axis is 0～90 °.
4. longitudinal groove MOS preparation of devices method according to claim 1 and 2 is characterized in that: in the step of described formation contact hole injection region, the dosage that injects ion is 10
11～10
16Atom/cm
2, the injection energy is: 1～2000KeV, the angle of nitrogen ion beam and substrate vertical axis is 0～90 °.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100273180A CN102130003A (en) | 2010-01-20 | 2010-01-20 | Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100273180A CN102130003A (en) | 2010-01-20 | 2010-01-20 | Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device |
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|---|---|
| CN102130003A true CN102130003A (en) | 2011-07-20 |
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| CN2010100273180A Pending CN102130003A (en) | 2010-01-20 | 2010-01-20 | Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632950A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A method for forming nitride films among polycrystalline silicon in a groove-type double layer grid MOS |
| CN104900704A (en) * | 2015-05-15 | 2015-09-09 | 四川广义微电子股份有限公司 | Longitudinal DMOS device |
| CN105655246A (en) * | 2016-01-04 | 2016-06-08 | 株洲南车时代电气股份有限公司 | Manufacturing method of groove-type IGBT grid electrode |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1032331A (en) * | 1996-07-15 | 1998-02-03 | Nec Corp | Semiconductor device and its manufacturing method |
-
2010
- 2010-01-20 CN CN2010100273180A patent/CN102130003A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1032331A (en) * | 1996-07-15 | 1998-02-03 | Nec Corp | Semiconductor device and its manufacturing method |
Non-Patent Citations (1)
| Title |
|---|
| P.MOENS等: "Record-low on Resistance for 0.35μm based integrated XtreMOS Transistors", 《PROCEEDING OF THE 19TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632950A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A method for forming nitride films among polycrystalline silicon in a groove-type double layer grid MOS |
| CN103632950B (en) * | 2012-08-20 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | Nitride film formation method between polysilicon in groove type double-layer grid MOS |
| CN104900704A (en) * | 2015-05-15 | 2015-09-09 | 四川广义微电子股份有限公司 | Longitudinal DMOS device |
| CN105655246A (en) * | 2016-01-04 | 2016-06-08 | 株洲南车时代电气股份有限公司 | Manufacturing method of groove-type IGBT grid electrode |
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Application publication date: 20110720 |