CN110164967B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN110164967B CN110164967B CN201810139717.2A CN201810139717A CN110164967B CN 110164967 B CN110164967 B CN 110164967B CN 201810139717 A CN201810139717 A CN 201810139717A CN 110164967 B CN110164967 B CN 110164967B
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- 238000002955 isolation Methods 0.000 claims abstract description 136
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- 238000005530 etching Methods 0.000 claims abstract description 31
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- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a substrate; forming a plurality of grooves in the substrate; forming an isolation oxide layer in the trench and over the substrate; depositing a mask polysilicon in the trench and on the isolation oxide layer on the substrate; performing a first etching process to remove a first part of the mask polysilicon and expose a part of the surface of the isolation oxide layer in the trench; performing a first removal process to remove a first portion of the isolation oxide layer; performing a second etching process to remove a second part of the mask polysilicon and expose the other part of the surface of the isolation oxide layer in the trench; performing a second removal process to remove a second portion of the isolation oxide layer; and forming an inter-poly oxide layer (inter-poly oxide layer) on the remaining mask poly and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface. The invention also provides a semiconductor device.
Description
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can reduce a gate-drain capacitance (Cgd) and suppress a gate leakage current.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Advances in integrated circuit materials and design have produced many generations of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than previous generations of integrated circuits.
In a split-gate trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) device, a gate-drain capacitance (Cgd) can be reduced by applying a sss masked gate trench (SGT) structure to increase the switching speed of the device. The mask polysilicon in the mask gate trench is electrically connected to the source electrode to electrically insulate the trench gate polysilicon from the drain electrode. The gate polysilicon and the shield polysilicon are electrically insulated from each other by an inter-polysilicon oxide (IPO) therebetween.
However, with the shrinking of device dimensions, in the process of split gate trench mosfet devices, the technique of using backfill oxide as inter-poly oxide (IPO) to insulate gate poly and mask poly is limited by the aspect ratio of the trench during backfill oxide, so that the ability to control the thickness and quality of the inter-poly oxide is limited, resulting in a higher gate to source leakage current (gate to source leakage current) of the device. Furthermore, the ability of the masked gate trench (SGT) structure to reduce the gate-drain capacitance (Cgd) is also limited.
Accordingly, there is a need in the art for an improved split gate trench mosfet device and method of making the same.
Disclosure of Invention
An embodiment of the present invention provides a method of manufacturing a semiconductor device. The method comprises the following steps: providing a substrate; forming a plurality of grooves in the substrate; forming an isolation oxide layer in the trench and over the substrate; depositing a shield polysilicon (shield polysilicon) in the trench and on the isolation oxide layer on the substrate; performing a first etching process to remove a first part of the mask polysilicon and expose a part of the surface of the isolation oxide layer in the trench; performing a first removal process to remove a first portion of the isolation oxide layer; performing a second etching process to remove a second part of the mask polysilicon and expose the other part of the surface of the isolation oxide layer in the trench; performing a second removal process to remove a second portion of the isolation oxide layer; and forming an inter-poly oxide layer on the remaining mask poly and the remaining isolation oxide layer. Wherein the inter-polysilicon oxide layer has a concave top surface.
Another embodiment of the present invention provides a semiconductor device. The semiconductor device includes: a substrate including a plurality of trenches; an isolation oxide layer in the trench; a mask polysilicon in the trench and surrounded by the isolation oxide layer; and an inter-polysilicon oxide layer on the isolation oxide layer and the mask polysilicon. Wherein the inter-polysilicon oxide layer has a concave top surface.
The method for manufacturing the semiconductor device has the advantages that the two-stage etching process is carried out on the mask oxide, and the two-stage removing process is carried out on the isolation oxide layer, so that the sinking degree of the isolation oxide generated between the side wall of the groove and the side wall of the mask oxide in the past process is reduced, and the interlayer polycrystalline silicon oxide filled in the subsequent process can be well deposited on the mask polycrystalline silicon and the isolation oxide layer without generating pores (void). Moreover, the recess degree of the isolation oxide layer between the trench sidewall and the mask polysilicon sidewall is reduced, and the inter-polysilicon oxide layer (IPO) filled in the subsequent process has no void (void). Providing good electrical insulation between the gate polysilicon and the mask polysilicon. Moreover, since there is no void, the inter-polysilicon oxide (IPO) provides a good isolation effect to suppress the gate-to-source leakage current, thereby improving the performance of the semiconductor device. In addition, the concave top surface of the inter-poly oxide (IPO) exhibits an upward curvature at a portion near the trench sidewall, which corresponds to an increase in the thickness of the oxide layer between the gate poly and the drain, thereby reducing the gate-drain capacitance (Cgd) of the semiconductor device.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1-10 are schematic cross-sectional views illustrating various stages in the processing of a semiconductor device according to some embodiments of the present invention.
Reference numerals:
10-device;
100 to a substrate;
102-groove;
104. 104' -isolation oxide layer
104 "-remaining isolation oxide layer;
104a, 104 b-surface portion;
104S-1-first top surface portion
104S-2 to a second top surface portion;
106. 106' -masking the polysilicon;
106 "-the remaining masked polysilicon;
106 'S, 106' S-side wall;
108-polycrystalline silicon interlayer oxide;
108' -polycrystalline silicon interlayer oxide layer;
106S, 108S-top surface;
110-gate oxide layer;
112-grid polysilicon;
d1 and D2;
h-height difference;
p1, P2-profile;
t1, T2, T3-thickness;
w1, W2-concave part.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by persons skilled in the art without any inventive step based on the embodiments of the present invention, belong to the protection scope of the present invention.
The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The particular elements and arrangements of parts in the present invention are provided for simplicity and clarity and are not intended to be limiting. For example, the description of forming a first element over a second element can include embodiments in which the first and second elements are in direct contact, as well as embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, the present invention may be represented in different examples by repeated symbols and/or letters without necessarily implying any particular relationship between such embodiments and/or structures. It is emphasized that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of discussion.
As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Some embodiments of the invention are described below. Fig. 1-10 are cross-sectional views illustrating various stages in the processing of a semiconductor device 10 according to some embodiments of the present invention. Additional operations may be provided before, during, and/or after the stages described in fig. 1-10. In various embodiments, some of the operations described above may be removed, deleted, or replaced. Additional features may be added to the semiconductor device. In various embodiments, some of the features described below may be removed, deleted, or replaced.
The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. In some embodiments of the present invention, the semiconductor device is a split gate trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The invention improves the process, carries out two-stage etching process on shield polysilicon (shield polysilicon) and carries out two-stage removal process on the isolation oxide layer to slow down the sinking degree of the isolation oxide generated between the side wall of a groove and the side wall of the shield polysilicon in the prior process, so that inter-polysilicon oxide (inter-poly oxide) filled in the subsequent process does not generate (or does not substantially generate) pores (void), thereby improving the control capability of the thickness and the quality of the inter-polysilicon oxide layer and achieving the purpose of inhibiting grid leakage current.
An embodiment of the present invention provides a method of manufacturing a semiconductor device. As shown in fig. 1, according to some embodiments, a substrate 100 is provided. In some embodiments, the substrate 100 may be a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate 100 is a silicon wafer. The substrate 100 may comprise silicon or other elemental semiconductor material, such as germanium. In some embodiments, the substrate 100 may comprise a sapphire substrate, a silicon substrate, or a silicon carbide substrate. In some embodiments, the substrate 100 may include one or more layers of semiconductor materials, insulator materials, conductor materials, or combinations thereof. For example, the substrate 100 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In another embodiment, the substrate 100 may also include a Silicon On Insulator (SOI). The SOI substrate may be formed using a separation by oxygen implantation (SIMOX) process, a wafer bonding process, other applicable approaches, or a combination of the preceding. In another embodiment, the substrate 100 may also be composed of multiple layers of materials, such as: Si/SiGe, Si/SiC. In another embodiment, the substrate 100 may comprise an insulator material, such as: an organic insulator, an inorganic insulator, or a combination thereof. In another embodiment, the substrate 100 may also include conductive materials, such as: polysilicon, metal, alloy, or a combination thereof.
As shown in fig. 1, according to some embodiments, a plurality of trenches (or recesses) 102 are formed in a substrate 100. In some embodiments, the trench 102 may be formed using, for example, one or more photolithography and etching processes. It should be understood that the size, shape, and location of the trench 102 shown in fig. 1 are merely exemplary, and are not intended to limit the present invention.
Next, as shown in fig. 2, an isolation oxide layer 104 is formed in the trench 102 and on the substrate 100, according to some embodiments. In some embodiments, the isolation oxide layer 104 may be conformally formed on the sidewalls and bottom of the trench 102 and on the top surface of the substrate 100 using, for example, thermal oxidation, or other suitable deposition process. The thickness T1 of the isolation oxide layer 104 may be adjusted according to the device size and design requirements of the semiconductor device. In some embodiments, the thickness T1 of the isolation oxide layer 104 on the sidewalls and bottom of the trench 102 and on the top surface of the substrate 100 may be, for example, 70nm to 150 nm.
As shown in fig. 2, according to some embodiments, a mask polysilicon 106 is deposited in the trench 102 and on the isolation oxide layer 104 on the substrate 100. In some embodiments, the masking polysilicon 106 may be filled in the trench 102 and deposited on the isolation oxide layer 104 on the substrate 100 using, for example, Chemical Vapor Deposition (CVD), or other suitable polysilicon deposition techniques. In some embodiments, the mask polysilicon 106 may be formed of undoped polysilicon or in-situ doped polysilicon.
As shown in fig. 3, according to some embodiments, a first etching process is performed to remove a first portion of the mask polysilicon 106 and expose a portion of the surface 104a of the isolation oxide layer 104 in the trench 102. In some embodiments, the first etch process may include, for example, an etch-back process. In some embodiments, the mask polysilicon 106 may be recessed into the trench 102 by removing the first portion of the mask polysilicon 106 until a desired depth is reached. For example, as shown in fig. 3, in one embodiment, the top surface of the mask polysilicon 106' may be lower than the top surface of the substrate 100. The surface 104a is a portion of the surface of the isolation oxide layer 104 formed on the sidewalls of the trench 102, exposed by removing a first portion of the masking polysilicon 106. In some embodiments, the masked polysilicon 106' after the first portion is removed has a depth D1 in the trench 102, as shown in fig. 3. It should be noted that in some embodiments, the depth D1 of the masked polysilicon 106' is not the depth required for the masked polysilicon in the final semiconductor device. In some embodiments, the depth D1 of the masked polysilicon 106' is greater than the depth required for the masked polysilicon in the final semiconductor device.
In some embodiments, a chemical planarization process, such as a chemical mechanical planarization polishing (CMP) process, may be performed on the mask polysilicon 106 until the isolation oxide layer 104 is exposed, before the first etching process is performed to remove the first portion of the mask polysilicon 106. Alternatively, in some embodiments, the chemical mechanical planarization polishing (CMP) process may be omitted, and the first etching process may be performed directly to recess the mask polysilicon 106 into the trench 102 until a desired depth is reached.
As shown in fig. 4, according to some embodiments, a first removal process is performed to remove a first portion of the isolation oxide layer 104. In some embodiments, the first removal process may include, for example, a wet etch process, an oxide etch process, or other suitable process. In some embodiments, after the first removal process, the portion of the isolation oxide layer 104' of the removed first portion exposed to the trench 102 (corresponding to the portion of fig. 3 having the surface 104 a) has a thinner thickness T2, as shown in fig. 4. In some embodiments, after the first removal process, the isolation oxide layer 104' on the substrate 100 also has a thinner thickness T2. In some embodiments, thickness T2 is less than thickness T1. In some embodiments, after the first removal process, the removed first portion of the isolation oxide layer 104 'forms a recessed portion W1 adjacent to the portion of the mask polysilicon 106' and exposes a portion of the sidewall 106 'S of the mask polysilicon 106'. As shown in fig. 4, in some embodiments, the recessed portion W1 extends between the sidewalls of the mask polysilicon 106 'and the isolation oxide layer 104' having a thickness T2.
Although the recessed portion W1 is depicted in fig. 4 as having a flat upper surface, it is understood that the illustration in fig. 4 is merely exemplary and that in some embodiments the upper surface of the recessed portion W1 of the isolation oxide layer 104' may have a concave curvature.
As shown in fig. 5, according to some embodiments, a second etching process is performed to remove a second portion of the mask polysilicon 106 and expose another portion of the surface 104b of the isolation oxide layer 104 in the trench 102. In some embodiments, the first etch process may include, for example, an etch-back process. In some embodiments, the mask polysilicon 106 may be recessed further into the trench 102 by removing the second portion of the mask polysilicon 106 until a desired depth is reached. For example, as shown in fig. 5, in one embodiment, the top surface of the mask polysilicon 106 "may be lower than the upper surface of the recessed portion W1 of the isolation oxide layer 104'. The surface 104b is another portion of the surface of the isolation oxide layer 104 formed on the sidewalls of the trench 102, exposed by removing a second portion of the masking polysilicon 106. In some embodiments, the masked polysilicon 106 "after the second portion is removed has a depth D2 in the trench 102, as shown in fig. 5. It should be noted that in some embodiments, the depth D2 of the masked polysilicon 106 "is the desired depth of the masked polysilicon in the final semiconductor device. In some embodiments, depth D2 is less than depth D1.
As shown in fig. 5, since the portion of the isolation oxide layer 104 exposed in the trench 102 (i.e., the portion having the surface 104 b) by the second etching process is not removed but protected by the masking polysilicon 106' during the first removal process, the portion of the isolation oxide layer 104 ″ having the surface 104b still has the same thickness as the thickness T1 after the second etching process. That is, since the embodiment of the invention performs the two-stage etching process (the first etching process and the second etching process) on the mask oxide 106, during the first removing process of the isolation oxide 104, a portion of the isolation oxide 104 can be protected by the mask oxide 106' having the depth D1 after the first etching process, so that the original thickness T1 is remained. Therefore, after the second etching process, the isolation oxide layer 104' exposed in the trench 102 has different thicknesses (T1 and T2), and a subsequent second removal process is then performed in this state (as shown in fig. 5).
As shown in fig. 6, according to some embodiments, a second removal process is performed to remove a second portion of the isolation oxide layer 104. In some embodiments, the second removal process may include, for example, a wet etch process, an oxide etch process, or other suitable process. In some embodiments, the second removal process may be the same as the first removal process. In some embodiments, the second removal process may be different from the first removal process. The first and second removal processes can be selected and adjusted according to the different process conditions such as the element size of the semiconductor device, the depth of the polysilicon mask in the two-stage etching process, and the like. It should be noted that the final top surface profile of the isolation oxide layer may be determined by controlling the conditions of the first removal process and the second removal process, thereby affecting the top surface profile of the inter-polysilicon oxide layer 108' in the final semiconductor device 10.
As shown in fig. 6, in some embodiments, after the second removal process, the portion of the second portion of the isolation oxide layer 104 "(also sometimes referred to herein as the remaining isolation oxide layer 104") that is removed that is exposed to the trench 102 (corresponding generally to the portion of fig. 3 having the surface 104 a) has a thinner thickness T3. In some embodiments, the remaining isolation oxide layer 104 "on the substrate 100 after the second removal process also has a thinner thickness T3. In some embodiments, thickness T3 is less than thickness T2. In other embodiments, after the second removal process, the portion of the isolation oxide layer 104 'corresponding to the surface 104a in fig. 3 may be completely removed, and the isolation oxide layer 104' on the substrate 100 may be completely removed.
As shown in fig. 6, in some embodiments, after the second removal process, the removed second portion of the isolation oxide layer 104 "further forms another recessed portion W2 in the area adjacent to the mask polysilicon 106" and exposes a portion of the sidewall 106 "S of the mask polysilicon 106". As shown in fig. 6, in some embodiments, the recessed portion W2 extends between the sidewalls of the mask polysilicon 106 "and the isolation oxide layer 104" having a thickness T3.
It should be noted that during the second removal process, since the protected isolation oxide layer 104 "(the portion having the surface 104 b) illustrated in fig. 5 still has the same thickness as the thickness T1, the dishing caused by the second removal process for the portion of the isolation oxide layer 104 ″ is reduced. As shown in fig. 6, in some embodiments, after performing the second removal process to remove the second portion of the isolation oxide layer 104, the top surface of the remaining isolation oxide layer 104 ″ extends substantially gently upward from the sidewalls of the mask polysilicon 106 toward the sidewalls of the trench 102. In some embodiments, the recessed portion W2 formed after the second removal process has a top surface that is not smooth (or discontinuous).
As shown in fig. 6, in some embodiments, the top surface 104S of the recessed portion W2 formed after the second removal process may be composed of a first top surface portion 104S-1 and a second top surface portion 104S-2. Although the first and second top surface portions 104S-1 and 104S-2 of the recessed portion W2 are depicted in fig. 6 as flat surfaces, it is understood that the drawing depicted in fig. 6 is merely an example and that in some embodiments, the first and second top surface portions 104S-1 and 104S-2 of the recessed portion W2 of the isolation oxide layer 104 ″ may each have a concave curvature.
More specifically, as shown in fig. 6, in some embodiments, after performing the second removal process to remove the second portion of the isolation oxide layer 104, a first top surface portion 104S-1 of the remaining isolation oxide layer 104 "adjacent to the sidewall of the mask polysilicon 106" has a first curvature, and a second top surface portion 104S-2 of the remaining isolation oxide layer 104 "adjacent to the sidewall of the trench 102 has a second curvature. In some embodiments, the first curvature is different from the second curvature. In some embodiments of the present invention, the,the first curvature is greater than the second curvature. In some embodiments, the first curvature may be, for example, 0.06 to 0.1nm-1. In some embodiments, the second curvature may be, for example, 0.02 to 0.025nm-1。
As shown in fig. 6, in some embodiments, after performing the second removal process to remove the second portion of the isolation oxide layer 104, a height difference H between a lowest point of the remaining isolation oxide layer 104 "adjacent to the first top surface portion 104S-1 of the mask polysilicon 106" and the top surface 106S of the remaining mask polysilicon 106 "may be less than a thickness T1 of the isolation oxide layer 104 above the substrate 100 as shown in fig. 2.
It is worth mentioning that such smaller height differences result from the process improvements of the present invention. In the past, to remove the isolation oxide layer on the trench sidewalls and on the substrate, the prior art processes typically over-etch the isolation oxide layer, thereby causing the isolation oxide layer to form a significant recess between the sidewalls of the mask polysilicon and the sidewalls of the trench, resulting in a significant height difference between the isolation oxide layer and the top surface of the mask polysilicon. However, since the embodiment of the present invention performs the two-stage etching process on the mask polysilicon and the two-stage removal process on the isolation oxide layer, the dishing of the isolation oxide between the sidewall of the mask polysilicon and the sidewall of the trench is reduced, and the height difference between the isolation oxide layer and the top surface of the mask polysilicon is also reduced. This results in no (or substantially no) voids (void) being created in the inter-polysilicon oxide that is subsequently filled into the trench 102. Since the interpoly oxide can be well deposited, the formation of the interpoly oxide layer can be better controlled, improving the performance of the final semiconductor device.
As shown in fig. 6, in some embodiments, after a second removal process is performed to remove the second portion of the isolation oxide layer 104, the remaining first and second top surface portions 104S-1 and 104S-2 of the isolation oxide layer 104 "and the top surface 106S of the mask polysilicon 106" form a profile P1. In some embodiments, the profile P1 may be generally considered a concave curve.
As shown in fig. 7, an inter-poly oxide 108 is deposited in the trench 102 and over the substrate 100, according to some embodiments. In some embodiments, inter-polysilicon oxide 108 may be deposited using, for example, High Density Plasma Chemical Vapor Deposition (HDPCVD), or other suitable deposition process. As described above, in some embodiments, the inter-polysilicon oxide 108 may completely cover the isolation oxide layer 104 and the mask polysilicon 106 without creating (or substantially creating) voids (void). This results in improved control over the thickness and quality of the inter-poly oxide layer, improving the performance of the final semiconductor device, such as reducing the gate-to-drain capacitance (Cgd) and suppressing the gate-to-source leakage current (gate-to-source leakage current).
As shown in fig. 8, according to some embodiments, a third etch process is performed to remove a portion of the inter-polysilicon oxide 108 and expose a portion of the sidewalls of the trench 102. In some embodiments, the third etching process may include, for example, a dry etching process, a wet etching process, a back etching process, other suitable etching processes, or a combination of the foregoing. In some embodiments, as shown in fig. 8, the inter-poly oxide 108 may be etched to a target depth using, for example, an etch-back process to form an inter-poly oxide 108' over the remaining mask poly 106 "and the remaining isolation oxide layer 104". For example, as shown in fig. 8, in one embodiment, the top surface 108S of the inter-polysilicon layer 108' may be lower than the top surface of the substrate 100. In some embodiments, after the third etching process, the remaining isolation oxide layer 104 ″ on the sidewalls of the trench 102 and on the substrate 100 may be completely removed together. In some embodiments, the inter-polysilicon layer oxide 108' may be used to electrically isolate the mask polysilicon 106 ″ from the gate polysilicon that is subsequently formed thereover. In some embodiments, the average thickness of the inter-poly oxide layer 108' may be, for example, 90nm to 170 nm.
Fig. 8 is a cross-sectional view of a semiconductor device after the second removal process of fig. 6, wherein the portion of the isolation oxide layer 104 'exposed in the trench 102 (substantially corresponding to the portion of fig. 3 having the surface 104 a) and the isolation oxide layer 104' on the substrate 100 are completely removed, according to some embodiments. In other embodiments, fig. 8 also shows a cross-sectional view (shown by a dotted line) of the semiconductor device in which the portion of the remaining isolation oxide layer 104 ″ exposed to the trench 102 (substantially corresponding to the portion of fig. 3 having the surface 104 a) has a thinner thickness T3 after the second removal process described in fig. 6. However, for the sake of brevity, the dashed portions are omitted below and in the description relating to fig. 9, 10.
It is noted that, as shown in fig. 8, according to some embodiments, the top surface of the inter-poly oxide layer 108' is a concave top surface 108S. The concave top surface 108S has a profile P2. In some embodiments, the profile P2 can be considered to have a concave curve and exhibit an upward curved curvature at portions near the sidewalls of the trench 102. As shown in fig. 8, in some embodiments, the profile P2 of the recessed top surface 108S of the inter-polysilicon layer oxide 108' is substantially the same as the profile P1 formed by the first top surface portion 104S-1, the second top surface portion 104S-2 of the remaining isolation oxide layer 104 ", and the top surface 106S of the remaining masking polysilicon 106". That is, in some embodiments, profile P2 and profile P1 are substantially the same, and may be considered to have substantially the same concave curve.
In some embodiments, the angle between the concave top surface 108S of the inter-polysilicon layer oxide 108' and the sidewalls of the trench 102 may be, for example, 110 ° to 120 °. In some embodiments, the curvature of the concave top surface 108S of the inter-polysilicon layer oxide 108' may be, for example, 0.045 to 0.055nm-1. In some embodiments, the curvature of the concave top surface 108S is the curvature of the profile P2. In some embodiments, the curvature of profile P2 is substantially equal to the curvature of profile P1. In some embodiments, the greater the angle between the concave top surface 108S of the inter-polysilicon layer oxide 108 'and the sidewalls of the trench 102, or the greater the curvature of the concave top surface 108S of the inter-polysilicon layer oxide 108', the greater the degree to which the gate-drain capacitance (Cgd) of the final semiconductor device decreases.
According to an embodiment, in the semiconductor device 10 provided by the embodiment of the present invention, in the case where the angle between the concave top surface 108S of the inter-polysilicon layer oxide 108 'and the sidewall of the trench 102 is 120 °, and the curvature of the concave top surface 108S of the inter-polysilicon layer oxide 108' (i.e., the curvature of the profile P2) is 120 °, the gate-drain capacitance (Cgd) of the semiconductor device 10 is 2.5E-9 to 3E-9 coulombs.
It is worth mentioning that, since the concave top surface 108S of the inter-poly oxide layer 108 'exhibits an upward curvature at a portion close to the sidewall of the trench 102, which corresponds to an increase in the thickness of the oxide layer (e.g., the inter-poly oxide layer 108' and the remaining isolation oxide layer 104 ") between the subsequently formed gate poly and the drain, the gate-drain capacitance (Cgd) of the final semiconductor device can be reduced.
In some embodiments, the height difference between the highest point of the remaining isolation oxide layer 104 "adjacent to the second top surface portion 104S-2 of the trench 102 and the lowest point of the first top surface portion 104S-1 adjacent to the mask polysilicon 106" may be, for example, 30nm to 40 nm. In some embodiments, the height difference from the highest point of the concave top surface 108S of the inter-polysilicon layer oxide 108' to the lowest point of the concave top surface 108S may be, for example, 32nm to 38 nm.
As shown in fig. 9, according to some embodiments, a gate oxide layer 110 is formed on the inter-polysilicon oxide layer 108'. In some embodiments, the gate oxide layer 110 may be formed using, for example, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a thermal oxidation process, a Physical Vapor Deposition (PVD) process, a photolithographic patterning process, an etching process, other applicable processes, or a combination of the foregoing. In some embodiments, the gate oxide layer 110 may be formed of silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum oxide alloy, hafnium silicon dioxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high-dielectric constant (high-k) dielectric materials, or combinations thereof.
As shown in fig. 10, according to some embodiments, a gate polysilicon 112 is formed on the gate oxide layer 110. In some embodiments, the gate polysilicon 112 may be formed using, for example, Chemical Vapor Deposition (CVD), or other suitable polysilicon deposition techniques. Thus, the semiconductor device 10 according to the embodiment of the present invention is completed.
Subsequent steps may be performed in accordance with techniques well known to those skilled in the art, such as forming an insulating layer over the semiconductor device 10, such as by Chemical Vapor Deposition (CVD), or other suitable deposition process, and forming a metal layer, such as by forming a borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borosilicate glass (BSG). For the sake of brevity, it is not described herein in detail.
Another embodiment of the present invention provides a semiconductor device formed by the above semiconductor manufacturing method. As shown in fig. 10, the semiconductor device 10 includes a substrate 100 having a plurality of trenches 102, and an isolation oxide layer 104 "disposed in the trenches 102. The material of the substrate 100 can refer to the related paragraphs, and will not be repeated here. In some embodiments, an isolation oxide layer 104 "may be conformally formed on the sidewalls and bottom of the trench 102 and on the top surface of the substrate 100.
In some embodiments, the semiconductor device 10 also includes a masking polysilicon 106 ". In some embodiments, the mask polysilicon 106 "may be formed of undoped polysilicon or in-situ doped polysilicon. In some embodiments, the mask polysilicon 106 "is located in the trench 102 and is partially surrounded by the isolation oxide layer 104".
In some embodiments, a top surface of the isolation oxide layer 104 "extends upward from the sidewalls 106" S of the mask polysilicon 106 "toward the sidewalls of the trench 102. In some embodiments, a top surface of the isolation oxide layer 104 "has two different curvatures. In some embodiments, a first top surface portion 104S-1 of the isolation oxide layer 104 "adjacent to the sidewall 106" S of the mask polysilicon 106 "has a first curvature and a second top surface portion 104S-2 of the isolation oxide layer 104" adjacent to the sidewall of the trench 102 has a second curvature. In some embodiments, the first curvature is greater than the second curvature. In some embodiments, the isolation oxide layer 104 "has a top surface that is not smooth (or discontinuous).
In some embodiments, the height difference between the first top surface portion 104S-1 of the isolation oxide layer 104 "adjacent to the mask polysilicon 106" and a top surface 106S of the mask polysilicon 106 "is less than 50 nm. This results in no (or substantially no) voids (void) being created in the inter-polysilicon oxide that is subsequently filled into the trench 102. Since the interpoly oxide can be well deposited, the formation of the interpoly oxide layer can be better controlled, improving the performance of the final semiconductor device, e.g., reducing the gate-drain capacitance (Cgd) and suppressing the gate-to-source leakage current.
In some embodiments, the height difference of the isolation oxide layer 104 "from the highest point of the second top surface portion 104S-2 adjacent to the trench 102 to the lowest point of the first top surface portion 104S-1 adjacent to the mask polysilicon 106" may be, for example, 30nm to 40 nm.
In some embodiments, the semiconductor device 10 further includes an inter-poly oxide layer 108'. In some embodiments, the inter-polysilicon layer oxide 108' may be, for example, a High Density Plasma Chemical Vapor Deposition (HDPCVD) oxide. An inter-poly oxide 108' is located over the isolation oxide 104 "and the masking poly 106". In some embodiments, the inter-polysilicon layer oxide 108' completely covers the isolation oxide 104 "and the mask polysilicon 106" without (or substantially without) voids (void). The inter-polysilicon oxide layer 108' has a concave top surface 108S.
In some embodiments, the profile of the recessed top surface 108S of the inter-polysilicon layer oxide 108 ' is substantially the same as the profile P1 formed by the top surfaces (the first top surface portion 104S-1 and the second top surface portion 104S-2) of the isolation oxide 104 ' and a top surface 106S of the mask polysilicon 106 '.
It should be noted that since the concave top surface 108S of the inter-poly oxide layer 108 'exhibits an upwardly curved curvature at a portion near the sidewall of the trench 102, which corresponds to an increase in thickness of the oxide layers (e.g., the inter-poly oxide layer 108' and the remaining isolation oxide layer 104 ") between the subsequently formed gate poly and the drain, the gate-drain capacitance (Cgd) of the final semiconductor device may be reduced. In some embodiments, the average thickness of the inter-poly oxide layer 108' may be, for example, 90nm to 170 nm.
In some embodiments, the angle between the concave top surface 108S of the inter-polysilicon layer oxide 108' and the sidewalls of the trench 102 may be, for example, 110 ° to 120 °. In some embodiments, the curvature of the concave top surface 108S of the inter-polysilicon layer oxide 108' may be, for example, 0.045 to 0.055nm-1. In some embodiments, the greater the angle between the concave top surface 108S of the inter-polysilicon layer oxide 108 'and the sidewalls of the trench 102, or the greater the curvature of the concave top surface 108S of the inter-polysilicon layer oxide 108', the greater the degree to which the gate-drain capacitance (Cgd) of the final semiconductor device decreases.
In some embodiments, the semiconductor device 10 further includes a gate oxide layer 110 on the inter-polysilicon layer oxide 108', and a gate polysilicon 112 on the gate oxide layer 110. The materials of the gate oxide layer 110 and the gate polysilicon 112 can be referred to the related paragraphs, and thus will not be repeated here. It is understood that the semiconductor device 10 may also include other elements not shown in the drawings, such as insulating layers, metal layers, and the like, such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borosilicate glass (BSG), located over the semiconductor device 10. Since the above structure is well known to those skilled in the art, it is not described herein for brevity.
The semiconductor device manufacturing method provided by the embodiment of the invention reduces the sinking degree of the isolation oxide generated between the side wall of the groove and the side wall of the mask oxide in the past process by performing the two-stage etching process on the mask oxide and performing the two-stage removing process on the isolation oxide layer, so that the interlayer polycrystalline silicon oxide filled in the subsequent process can be well deposited on the mask polycrystalline silicon and the isolation oxide layer without generating pores (void).
The semiconductor device obtained by the method for manufacturing the semiconductor device provided by the embodiment of the invention has the following advantages. Compared with the semiconductor device provided by the prior art, the semiconductor device provided by the embodiment of the invention has the advantages that the recess degree of the isolation oxide layer between the side wall of the groove and the side wall of the mask polysilicon is reduced, and the inter-polysilicon oxide layer (IPO) filled in the subsequent process has no void (void). Therefore, the inter-poly oxide (IPO) of the semiconductor device according to the embodiment of the present invention can provide a good electrical insulation effect between the gate polysilicon and the mask polysilicon. Moreover, since there is no void, the inter-polysilicon oxide (IPO) provides a good isolation effect to suppress the gate-to-source leakage current, thereby improving the performance of the semiconductor device.
In addition, the isolation oxide layer of the semiconductor device provided by the embodiment of the invention has an improved profile at the recessed portion between the sidewall of the trench and the sidewall of the mask polysilicon due to the two-stage etching process performed on the mask oxide and the two-stage removal process performed on the isolation oxide layer. In addition, since the profile of the inter-poly oxide (IPO) of the semiconductor device provided by the embodiment of the present invention is substantially the same as that of the recessed portion of the isolation oxide, the inter-poly oxide (IPO) of the semiconductor device provided by the embodiment of the present invention has a concave top surface. The concave top surface of the inter-poly oxide (IPO) exhibits an upward curvature near the trench sidewalls, which corresponds to an increased thickness of the oxide between the gate poly and the drain, thereby reducing the gate-drain capacitance (Cgd) of the semiconductor device.
Although the present invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (18)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming a plurality of trenches in the substrate;
forming an isolation oxide layer in the trenches and on the substrate;
depositing a mask polysilicon in the trenches and on the isolation oxide layer on the substrate;
performing a first etching process to remove a first portion of the masked polysilicon and expose a portion of the surface of the isolation oxide layer in the trenches;
performing a first removal process to remove a first portion of the isolation oxide layer;
performing a second etching process to remove a second portion of the masked polysilicon and expose another portion of the surface of the isolation oxide layer in the trenches;
performing a second removal process to remove a second portion of the isolation oxide layer; and
forming a polysilicon interlayer oxide layer on the rest of the mask polysilicon and the rest of the isolation oxide layer;
wherein the inter-polysilicon oxide layer has a concave top surface.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
forming a gate oxide layer on the inter-polysilicon oxide layer; and
forming a gate polysilicon on the gate oxide layer.
3. The method of claim 1, wherein forming the inter-polysilicon oxide layer over the remaining mask polysilicon and the remaining isolation oxide layer comprises:
depositing an inter-poly oxide in the trenches and over the substrate;
a third etching process is performed to remove a portion of the inter-polysilicon oxide and expose a portion of the sidewalls of the trenches.
4. The method of claim 3, wherein said inter-poly oxide completely covers said isolation oxide and said masking polysilicon.
5. The method of manufacturing a semiconductor device according to claim 1, further comprising:
before the first etching process is performed to remove the first portion of the mask polysilicon, a chemical mechanical planarization polishing process is performed on the mask polysilicon until the isolation oxide layer is exposed.
6. The method of claim 1, wherein a top surface of the remaining isolation oxide layer extends upward from the sidewalls of the masked polysilicon toward the sidewalls of the trench after the second removal process is performed to remove the second portion of the isolation oxide layer.
7. The method of claim 1, wherein a first top surface portion of the isolation oxide layer remaining adjacent to sidewalls of the mask polysilicon has a first curvature and a second top surface portion of the isolation oxide layer remaining adjacent to sidewalls of the trench has a second curvature after the second removal process is performed to remove the second portion of the isolation oxide layer, wherein the first curvature is greater than the second curvature.
8. The method according to any of claims 1-7, wherein a profile of the top surface of the recess of the inter-poly oxide is substantially the same as a profile of a top surface of the remaining isolation oxide and a top surface of the remaining mask poly.
9. The method of claim 1, wherein a height difference between a lowest point of a portion of the remaining isolation oxide layer adjacent to a first top surface of the mask polysilicon and a top surface of the remaining mask polysilicon is less than a thickness of the isolation oxide layer on the substrate.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the gate electrode is performed in a step of forming a gate electrodeWherein an angle between the concave top surface of the inter-poly oxide layer and the sidewall of the trench is 110 DEG to 120 DEG and/or a curvature of the concave top surface of the inter-poly oxide layer is 0.045 to 0.055nm-1。
11. A semiconductor device, comprising:
a substrate including a plurality of trenches;
an isolation oxide layer in the trenches;
a mask polysilicon in the trenches and partially surrounded by the isolation oxide, wherein a first top surface portion of the isolation oxide adjacent to the sidewalls of the mask polysilicon has a first curvature, and a lowest point of the first top surface portion abuts the mask polysilicon, a second top surface portion of the isolation oxide adjacent to the sidewalls of the trenches has a second curvature, the first curvature being greater than the second curvature; and
an inter-polysilicon layer oxide layer on the isolation oxide layer and the mask polysilicon;
wherein the inter-polysilicon oxide layer has a concave top surface.
12. The semiconductor device of claim 11, further comprising:
a grid oxide layer located on the inter-polysilicon oxide layer; and
a gate polysilicon on the gate oxide layer.
13. The semiconductor device of claim 11, wherein said inter-poly oxide completely covers said isolation oxide and said mask poly.
14. The semiconductor device of claim 11, wherein a top surface of said isolation oxide layer extends upward from said sidewall of said mask polysilicon toward said sidewall of said trench.
15. The semiconductor device according to any of claims 11-14, wherein a profile of the recessed top surface of the inter-poly oxide is substantially the same as a profile formed by a top surface of the isolation oxide and a top surface of the mask poly.
16. The semiconductor device of claim 11, wherein a height difference between a first top surface portion of said isolation oxide layer adjacent to said mask polysilicon and a top surface of said mask polysilicon is less than 50 nm.
17. The semiconductor device of claim 11, wherein a height difference between a highest point of a second top surface portion adjacent to the trench and a lowest point of a first top surface portion adjacent to the mask polysilicon is 30nm to 40nm and/or an average thickness of the inter-poly oxide layer is 90nm to 170 nm.
18. The semiconductor device of claim 11, wherein an angle between the concave top surface of the inter-poly oxide layer and the sidewall of the trench is 110 ° to 120 ° and/or a curvature of the concave top surface of the inter-poly oxide layer is 0.045 to 0.055nm-1。
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| TWI731753B (en) * | 2020-07-21 | 2021-06-21 | 新唐科技股份有限公司 | Semiconductor structure and method of forming the same |
| CN114388438A (en) * | 2020-10-22 | 2022-04-22 | 无锡华润上华科技有限公司 | Manufacturing method of split gate trench MOSFET |
| CN112133637B (en) * | 2020-11-30 | 2021-02-12 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
| CN113013028A (en) * | 2021-03-24 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
| CN113013027A (en) * | 2021-03-24 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
| CN114284149B (en) * | 2021-12-22 | 2023-04-28 | 瑶芯微电子科技(上海)有限公司 | Preparation method of shielded gate trench field effect transistor |
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