CN1809928A - Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses - Google Patents

Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses Download PDF

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CN1809928A
CN1809928A CN03817927.XA CN03817927A CN1809928A CN 1809928 A CN1809928 A CN 1809928A CN 03817927 A CN03817927 A CN 03817927A CN 1809928 A CN1809928 A CN 1809928A
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electrode
well region
region
bucking electrode
semiconductor device
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CN100514672C (en
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克里斯托弗·B.·库肯
艾伦·艾本海威
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Fairchild Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

Disclosed is a semiconductor gate structure which comprises a shield electrode and a switch electrode. Each part of the shield electrode is positioned above the drain region and the trap region; a first dielectric layer is arranged among the shield electrode, the drain region and the trap region; each part of the switch electrode is positioned above the trap region and the source region; a second dielectric layer is arranged among the switch electrode, the trap region and the source region; a third dielectric layer is arranged between the shield electrode and the switch electrode.

Description

Thereby be used to improve the method and apparatus that the mos gate control reduces miller capacitance and switching losses
The related application reference
Present patent application requires to obtain U.S. Provisional Patent Application series No.60/405,369 benefit of priority, and it was filed an application on August 23rd, 2002.
Technical field
The present invention relates to semiconductor, more particularly, relate to mos field effect transistor (MOSFET).
Background technology
MOSFET is widely used in field of switches, and for example Switching Power Supply is used the transistor of other types hardly.It is because the power that they have higher relatively switching speed and needs is lower that MOSFET is suitable for this switch application.Yet the dynamic loss among the MOSFET has occupied bigger percentage in the DC-DC converter total losses.Dynamic loss was directly proportional with the rising and the falling time (rise and fall time) of device, and the grid-drain capacitance of the rising of device and falling time and device, just miller capacitance (C GDPerhaps Q GD) proportional.
As shown in Figure 3, miller capacitance also can cause " smooth " district in the conventional MOS FET grid curve.This flat region is known as Miller region, and the expression device carries out the transition to conducting state from blocked state, perhaps carries out the transition to blocked state from conducting state.Most switching losses occurs in Miller region just, because device current and voltage are higher.Reduce miller capacitance and can reduce device from being conducting to the required time of obstruction, perhaps vice versa, reduces switching losses whereby.
Can reduce miller capacitance by the overlapping region that reduces between grid region and the drain region.Formerly in the device of technology, this overlapping region comprises the bottom of gate groove.Therefore, many prior arts of attempting to reduce miller capacitance all concentrate on the width that the width that shrinks this raceway groove reduces trench bottom whereby, thereby reduce overlapping region.Yet the ability that further reduces channel width is subjected to the restriction of etch narrow trenches ability, and correspondingly needs and can enough gate material fill this narrow raceway groove.
Therefore, need to make MOSFET to have lower miller capacitance technically, thereby reduce switching losses.
And, need to make MOSFET under given channel width, to have lower miller capacitance technically.
Summary of the invention
The present invention provides a kind of grid structure for semiconductor device.
A kind of form of the present invention comprises a switch electrode and a bucking electrode.The various piece of bucking electrode is positioned on described drain region and the described well region.First dielectric layer is between bucking electrode and drain region and well region.The various piece of switch electrode is positioned on described well region and the described source region.Second dielectric layer is between switch electrode and well region and source region.The 3rd dielectric layer is between bucking electrode and switch electrode.
An advantage of the present invention is that for given channel width, the miller capacitance of semiconductor device is littler than prior art device.
The further advantage of the present invention is that the switching time of device and switching losses are still less.
Description of drawings
Above-mentioned and other the feature and advantage of the present invention, and the mode that obtains them will become apparent and easier to understand by the explanation with reference to the one embodiment of the invention of following connection with figures, wherein:
Fig. 1 is the generalized section of prior art trench Mosgate (mos gate control) structure;
Fig. 2 is the generalized section of an embodiment of mos gate control structure of the present invention;
Fig. 3 is the curve chart of the door switch waveform of conventional MOS gate modulation structure and Fig. 2 mos gate control structure;
Fig. 4 is the curve chart of typical net doping section of the trap of Fig. 2 mos gate control structure;
Fig. 5 is the generalized section of an embodiment of planar MOSFET of the present invention;
Fig. 6 is the generalized section of planar MOSFET second embodiment of the present invention;
Fig. 7 is the generalized section of an embodiment of side MOSFET of the present invention;
Fig. 8 is the generalized section of MOSFET second embodiment in side of the present invention;
Fig. 9 is the generalized section of an embodiment of channel MOS gate modulation structure of the present invention; With
Figure 10 is the procedure chart that an embodiment of device processing shown in Figure 2 is made in diagram.
Among these figure, use corresponding reference numerals to represent corresponding part.The example that this paper proposes illustrates a kind of form of a preferred embodiment of the present invention, and this example not will be understood that scope of the present invention is had any restriction.
Embodiment
With reference now to accompanying drawing Fig. 1 particularly,, it has shown the generalized section of prior art trench grid-control MOSFET device.MOSFET device 10 comprises drain region 12, well region 14, tagma 16, source region 18, grid region 20 and raceway groove 24, and all these forms on substrate 26.
Say that more clearly N+ type substrate 26 comprises upper strata 26a, wherein in the upper strata, formed N-drain region 12.P-type well region 14 is positioned at 12 tops, drain region.In the part of the upper surface (not indicating) of upper strata 26a and well region 14, define heavy doping P+ tagma 16.In the part of the upper surface of upper strata 26a and well region 14 and near raceway groove 24, formed heavy doping N+ source region 18.The sidewall of raceway groove 24 and bottom (not pointing out) lining is with dielectric substance 28, for example oxide.Grid region 20 is formed by electric conducting material 30, and doped polycrystalline silicon for example is near it is deposited in the raceway groove 24 and extends to the upper surface of upper strata 26a continuously from the bottom of raceway groove 24.Therefore, grid 20 with respect to channel region 32 continuously or by channel region 32.Interlayer dielectric (interleveldielectric layer) 34, for example boron phosphoric silicate (borophosphosilicate) glass (BPSG) is positioned at above the part in grid region 20 and source region 18.Source metal level 36 is positioned on the upper surface of upper strata 26a and with tagma 16 and contacts with source region 18.
With reference now to Fig. 2,, it has shown the generalized section of an embodiment of raceway groove grid-control MOSFET device of the present invention.Even many characteristics of MOSFET 100 are not exclusively alike also similar to MOSFET 10 basically with structure.Similar to MOSFET 10, MOSFET 100 comprises leakage 112, trap 114, body 116, source 118, grid structure 120 and raceway groove 124, and all these forms on substrate 126.Yet different with the grid structure 20 of MOSFET 10, the grid structure 120 of MOSFET 100 comprises that double cross folds (dual overlapping) grid structure, and it has reduced miller capacitance and has improved switching speed, and this will make an explanation hereinafter especially.
MOSFET 100 forms on N+ type substrate 126, and N+ type substrate 126 is included in the upper strata 26a that has wherein formed N-drain region 112.P-type well region 114 is positioned at 12 tops, drain region.In the part of the upper surface (not indicating) of upper strata 126a and well region 114, define heavy doping P+ tagma 116.In the part of the upper surface of upper strata 126a and well region 114 and near raceway groove 124, also formed heavy doping N+ source region 118.Bottom (not pointing out) lining that is positioned near lower sidewall branch of bucking electrode 120b and raceway groove 24 is with dielectric substance 128, for example oxide.
Be a single and monolithic electrode of continuously and not being interrupted the grid structure 120 of MOSFET 100 does not resemble in MOSFET 10, but be divided into isolating switch and the bucking electrode that overlaps each other.Say that more clearly grid structure 120 comprises gate electrode 120a and gate electrode 120b.Interlayer dielectric 134 is positioned at above the gate electrode 120a, is positioned partially at above the source region 118.Each of electrode 120a and 120b all forms with electric conducting material, doped polycrystalline silicon for example, and it is deposited in the raceway groove 124.First or top electrode 120a that is formed by conductive metal layer and the about level of upper surface of upper strata 126a perhaps are recessed into and are lower than this upper surface.First/top electrode 120a from the upper surface of the upper strata 126a of source region 118 horizontal coplanes near extend predetermined distance to the bottom of raceway groove 124, thereby the bottom of first/top electrode 120a and well region 114 horizontal coplanes.
Second or the bottom electrode 120b that are formed by second conductive material layer extend near the bottom of raceway groove 124.The horizontal coplane of binding (not indicating) of the part of the second electrode 120b (descending) and drain region 112 and well region 118, another part of second/hearth electrode 120b (on) and source region 118 and the horizontal coplane of the first electrode 120a.Therefore, the first and second electrode 120a and 120b overlap each other with respect to the degree of depth of raceway groove 124 respectively.The side wall upper part of proximity switches electrode 120a is divided and the top of bucking electrode 120a is capped with dielectric substance 138, for example oxide.Therefore, dielectric substance 138 is between gate electrode 120a and 120b.
As mentioned above, bucking electrode 120b and switch electrode 120a overlap to small part each other along the degree of depth of raceway groove 124.More clearly say, in the embodiment shown in Figure 2, near the surface of gate electrode 120a it is positioned at bucking electrode 120b defines a depression 140, and it is between sidewall 142 and/or surround sidewall 142, and the top cap portion 144 of bucking electrode 120b is arranged in this depression.The sidewall 142 of switch electrode 120a and the top cap portion 144 of bucking electrode 120b overlap to small part axially or on the depth direction each other raceway groove 124.Thereby provide the gate electrode structure that overlaps.Further, as what will illustrate more comprehensively hereinafter, the top cap portion 144 of bucking electrode 120b and ledge 146 are that the part by corrosion dielectric layer 128 forms, this part of dielectric layer 128 be positioned at the conductive material layer that constitutes bucking electrode 120b upper surface (not indicating) neighbouring, on and under.
Substantially, grid or switch electrode 120a work to switch electrode, and open and/or close MOSFET 100, and grid or bucking electrode 120b play a part to produce to small part passage 132.For MOSFET 100 is set to conduction mode, the end/bucking electrode 120b must suitably be setovered and/or be opened.The end or bucking electrode 120b or be biased to continuously opens or conducting state, is set to conducting state by it device is got ready thereby perhaps can just be biased before translation activity.When the end/when bucking electrode 120b opens, controlled by grid/hearth electrode 120a by the electric current of MOSFET.
As above in the face of the explanation of prior art MOSFET 10, as shown in Figure 1, the crossover region OL between grid region 20 and the drain region 12 comprises the bottom of gate groove 24.Relatively, grid switch electrode 120a does not overlap with drain region 112.Unique overlapping region between grid switch electrode 120a and the drain region 112 is that width is the channel region 132 of W, and it typically has only the hundreds of dust wide.Produce passage 132 by bias shield electrode 120b.Channel region 132 112 extends through well region 114 along raceway groove 124 and bucking electrode 120b from the drain region.Therefore the effective grid among the MOSFET 100-leakages overlaps (width of passage 132 just) with respect to significantly minimizing of MOSFET 10 (just the bottom section of raceway groove 124, it typically is about 0.3-1.0 micron).Therefore, the miller capacitance of MOSFET 100 significantly reduces with respect to the miller capacitance of MOSFET 10, because as mentioned above, miller capacitance is proportional with grid-leakage crossover region substantially.
The miller capacitance of MOSFET 100 has schematic diagram with respect to the improvement (just reducing) of MOSFET 10 in Fig. 3, wherein drawn the gate voltage waveform of each device.The gate voltage oscillogram Vg of MOSFET 10 10Zone with a flat, grid charge Q in this zone GateBe increased to about 2.00 * 10 from about 0.0 (zero) -15Coulomb/micron, and the gate voltage waveform Vg of MOSFET 100 100Almost there is not corresponding general planar zone.Therefore, visible miller capacitance has been reduced basically and significantly.
Should pay special attention to, produce any significant reaction for fear of electric current to MOSFET 100, when device from the status transition that has only shielding electric capacity 120b and be biased to main or when switching the state that grid 120b also is biased, channel region 132 must exist and be open always.The threshold voltage of this transition and final driving voltage level take place to be determined by intersection (cross-over) doping content at the tie point place in P-type well region 114 and source region 118.
Fig. 4 has drawn the net doping section that is positioned at various degree of depth place under the source region 118 in the well region 114 and has distributed.Therefore the vertical pivot of Fig. 4 is designated as the depth zero value of well region 114 corresponding to the interface (" top " of well region 114 just) of source region 118 with well region 114.The degree of depth of bucking electrode 120b is about 0.6-0.8 micron under the depth zero, and it is about 0.7-0.9 micron under the depth zero that well region leaks side.Therefore, the net doping in the visible well region 114 is higher relatively, for example is about 1.0 * 10 near source region 118 17, in the part of well region 114, be reduced to about 3.0 * 10 near bucking electrode 120b and drain region 112 -16-about 1.5 * 10 -16Doping content.Well region 114 has minimum concentration of dopant with the interface in drain region 112, and it is positioned at 0.84-0.86 micron under the depth zero.
Because threshold value and driving voltage are directly proportional with oxide thickness and net doping level, so above-mentioned doping section (profile) can use much thick oxide skin(coating) near drain region 112, about 100-1500 dust for example.The increase of oxide skin(coating) thickness makes it possible to carry out the transition to switch gate 120a from shield grid 120b, and has continuous electric current in channel region 132.
In operation, bucking electrode 120b is enhanced or is biased to the electromotive force that is enough to support the driving voltage level.In fact, bucking electrode 120b is to grid-leakage crossover region charging, and this zone is the above-mentioned zone that produces miller capacitance in traditional devices.Opened and/or closed in case grid-leakage crossover region conductively-closed electrode 120a charging, MOSFET 100 just can easily change by the less relatively voltage that imposes on switch electrode 120a.
The handling process realization of Figure 10 institute best image is passed through in the manufacturing that is built into the MOSFET 100 of vertical-channel MOSFET.Handling process 300 is until the processing of formation grid 120 all is the conventional process flow that is used to form raceway groove grid-control MOSFET.Say that more clearly raceway groove 124 forms processing 302 by traditional raceway groove and corroded.At the sidewall and the bottom deposit dielectric layer 128 of raceway groove 124, this also is by known tradition first dielectric layer deposition process 304 then.Afterwards, the manufacturing that is used to make MOSFET 100 is handled 300 different with traditional handling process.
By after the first dielectric layer deposition step, 304 dielectric layer deposition 128, in the oxidized raceway groove 124 of sidewall, deposit the part of first conductive material layer as deposition shield electrode step 306.In bucking electrode corrosion step 308, first conductive material layer is eroded to the thickness of expectation by for example reactive ion isotropic etch then.Then, etched in gate dielectric layer 128 in gate dielectric layer corrosion step 310.Gate dielectric corrosion step 310, isotropic etch is for example also removed the electric conducting material 130b of predetermined quantity near dielectric substance 128, form top cap 144 and the ledge 146 of bucking electrode 120b whereby.Can select to carry out one or more additional corrosion steps 312 so that remove edge sharp-pointed among the bucking electrode 120b and/or turning.Then by the second dielectric layer deposition step, 314 deposition of gate dielectric layers 138.Dielectric layer 138 is deposited on the top cap 144 of bucking electrode 120b and the upper surface (not indicating) of ledge 146, and raceway groove 124 is positioned on the sidewall on the bucking electrode 120b.In raceway groove 124, deposit the part of second conductive material layer then as deposition switch electrode step 316.All the other treatment steps 318 comprise traditional processing and polishing step, and are known technically.
With reference now to Fig. 5,, it has shown second embodiment of MOSFET of the present invention.MOSFET 400 is surperficial grid-control vertical MOSFET, and it comprises a double cross stacked gate structure similar substantially to MOSFET 100.Many characteristics of MOSFET 400 are similar substantially to MOSFET 100 with structure.Similar with MOSFET 100, MOSFET400 comprises leakage 412, trap 414, body 416, source 418 and grid structure 420, and all these forms on substrate 426.Compare with MOSFET 100, MOSFET 400 is built into surperficial grid-control vertical MOSFET.Yet similar to grid structure 120, grid structure 420 comprises that a double cross folds gate modulation structure, and it can reduce miller capacitance and switching losses with respect to traditional MOSFET device.
MOSFET 400 forms on N+ type substrate 426, and N+ type substrate 426 is included in the upper strata 426a that has wherein formed N-drain region 412.P-type well region 414 is positioned at above the drain region 412.In the appropriate section of the upper surface (not indicating) of upper strata 426a and well region 414, define heavy doping P+ tagma 416.In the appropriate section of the upper surface of upper strata 426a and well region 414, also formed source region 418.Near source region 418 formation tagma 416, thus source region 418 is between tagma 416.Deposition of gate dielectric layer 428, for example oxide on the upper surface of upper strata 416a.Gate dielectric layer 428 parts cover well region 414 and source region 418.
The same with the grid structure 120 of MOSFET 100, the grid structure 420 of MOSFET 400 is divided into isolating switch and the bucking electrode that overlaps each other.Grid structure 420 comprises pair of switches electrode 420a and a pair of bucking electrode 420b, and they are positioned at the top and/or top of dielectric layer 428,434 and 438, and will carry out more particularly bright hereinafter.
Switch electrode 420a is formed by conductive material layer, doped polycrystalline silicon for example, and it is deposited on above the gate dielectric layer 428, and is corroded and forms the switch electrode 420a of two isolation.The various piece of each switch electrode 420a is positioned at corresponding source region 418 and the top of well region 414 and/or vertical with it coplane.Use second dielectric layer 438 then, for example oxide covers switch electrode 420a and gate dielectric layer 428.Remove second dielectric layer 438 by corrosion step then and cover the part of regional dielectric layer 428 between the switch electrode 420a, and the part that makes second dielectric layer 438 cover switch electrode 420a self remains intact.
By deposition second conductive material layer on first and second dielectric layers 428 and 438, for example doped polycrystalline silicon forms bucking electrode 420b then.This second conductive material layer is corroded and forms bucking electrode 420b.The various piece of each bucking electrode 420b is positioned at the top and/or vertical with it coplane of the adjacent part in corresponding well region 414 and drain region 412, forms whereby and covers double-gated structure 420.Say that more clearly the predetermined portions that corrosion bucking electrode 420b makes second conductive material layer be positioned at switch electrode top (just covering switch electrode 420a) remains intact.Thereby each bucking electrode 420b part is positioned at the top of respective switch electrode 420a and overlaps with it, forms the folded surperficial gate modulation structure 420 of double cross whereby, and it has reduced miller capacitance and improved switching times with respect to traditional MOSFET device.On grid structure 420 and dielectric layer 428 and 438, deposit interlayer dielectric 434 then.
With reference now to Fig. 6,, it has shown another embodiment of MOSFET of the present invention.MOSFET 500 also is built into a surperficial grid-control vertical MOSFET, and it comprises a folded gate modulation structure 520 of the double cross similar to the grid structure 420 of MOSFET 400.Yet, in grid structure 420, the part of each bucking electrode 420b overlaps with corresponding switch electrode 420a, and each switch electrode 520a of grid structure 520 comprises the various piece (not indicating) of overlapping (just cover or deposit) respective shield electrode 420a in the above.The remainder of MOSFET 500 is similar basically to MOSFET 400, therefore no longer goes through.
With reference now to Fig. 7,, it has shown the further embodiment of MOSFET of the present invention.MOSFET 600 is built into a side MOSFET, and it is traditional structure substantially except overlapping gate structure 620.The grid structure 620 of MOSFET 600 is divided into switch electrode 620a and the bucking electrode 620b that overlaps each other, and they are positioned at the top or top of dielectric layer 628,634 and 638, and more clearly illustrate hereinafter.
Conductive material layer, for example doped polycrystalline silicon is deposited on above the gate dielectric 628, is corroded then to form bucking electrode 620a, and the various piece of bucking electrode 620a is positioned at well region 614 and drain region 612 top and/or vertical with it coplanes at least in part.Bucking electrode 620a and gate dielectric layer 628 are by second dielectric layer 638 then, and for example oxide covers.Carry out corrosion treatment, stay top and the side of the bucking electrode 620b that is covered by second dielectric layer 638, also remove second dielectric layer 638 from gate dielectric layer 628.
By deposition second conductive material layer on first and second dielectric layers 628 and 638, for example doped polycrystalline silicon forms switch electrode 620a then.Corrode this second conductive material layer then and form switch electrode 620a, wherein the various piece of switch electrode 620a is positioned at well region 614 and source region 618 top and/or vertical with it coplanes, forms overlapping double-gated structure 620 whereby.Say that more clearly the part of switch electrode 620a is positioned at above second dielectric layer 638, and cover bucking electrode 620b that form overlapping gate structure 620 whereby, it has reduced miller capacitance and improved the switch number of times with respect to traditional MOSFET device.
With reference now to Fig. 8,, it has shown further embodiment of MOSFET of the present invention.MOSFET 700 is built into a side MOSFET similar substantially to MOSFET 600.Yet in MOSFET 600, the part of switch electrode 620a covers and overlapping bucking electrode 620b, and MOSFET 700 comprises that a part covers and/or the bucking electrode 720b of overlapping switch electrode 720a.All the other structures of MOSFET 700 are similar basically to MOSFET 600, therefore no longer go through.
With reference now to Fig. 9,, it has shown further embodiment of MOSFET of the present invention.MOSFET 800 is built into a raceway groove grid-control MOSFET, and it is similar substantially to MOSFET 100 except the CONSTRUCTED SPECIFICATION of overlapping gate structure 820.Substantially, MOSFET800 be not resemble above-mentioned with reference to by forming depression and top cap the grid structure being overlapped the overlapping gate structure 120, but by forming switch and the relative of bucking electrode or the surperficial in opposite directions overlapping gate structure 820 that realizes, wherein switch and bucking electrode have complementary substantially depression and projection respectively.
Say that more clearly MOSFET 800 comprises an overlapping gate structure 820, it has switch electrode 820a and the bucking electrode 820b that is formed in the raceway groove 824.The lobed lower surface 821a of switch electrode 820a, and bucking electrode 820b has the upper surface 821b of depression.The deposit dielectric material layer 838 in the above, so the concavity of the upper surface of dielectric material layer 838 is identical substantially with concave upper surface 821b.Switch electrode 820a is positioned at above the recessed layer of dielectric substance 838, so the shape of the convex lower surface 821a of switch electrode 820a and convexity and concave upper surface 821b complementation basically.Thereby the concavity of concave upper surface 821b guarantees that switch and bucking electrode 820a and 820b overlap separately from each other with respect to the direction or the degree of depth of raceway groove 824.Therefore, the formation of overlapping trench-gated structure 820 has reduced the miller capacitance of MOSFET 800 and has improved switch speed.
Should pay special attention to, in shown in Figure 9 and the above embodiments, switch electrode 820a has convex lower surface 821a, and bucking electrode 820b has concave upper surface 821b, and the convexity of the concavity of concave upper surface 821b and convex lower surface 821 makes switch and bucking electrode 820a and 820b overlap separately from each other with respect to the direction and the degree of depth of raceway groove 824.Yet, be to be understood that, MOSFET 800 can additionally be made up, for example make switch electrode 820a have recessed lower surface 821a, and bucking electrode 820b has protruding upper surface 821b, the convexity of projection upper surface 821b and the concavity of recessed lower surface 821 make switch and bucking electrode 820a and 820b overlap separately from each other with respect to the direction and the degree of depth of raceway groove 824, form the overlapping trench-gated structure whereby.
In the embodiment shown in Figure 2, the sidewall 142 of switch electrode 120a and the top cap portion 144 of bucking electrode 120b each other to the small part overlapping, provide the overlapping gate electrode structure whereby on the axial or depth direction of raceway groove 124.Yet, the grid that should be appreciated that MOSFET 100 can additionally be made up, and for example make switch electrode tool crown cap or ledge and bucking electrode has depression, improve similar overlapping gate electrode structure whereby, just the form of grid 120 turned upside down of MOSFET 100 substantially.
Although the present invention is illustrated by its decision design, the present invention can further revise in its disclosed spirit and scope.Therefore, present patent application intention covers any modification of the present invention, application or repacking, its use be General Principle disclosed herein.Further, present patent application intention covers following modification of the present disclosure, and it comes from known or traditional engineering practice, and wherein the present invention is suitable for this practice and belongs to the scope of appended claims.

Claims (23)

1. the grid structure of a semiconductor device, described semiconductor device has drain region, well region and source region, and described grid structure comprises:
A bucking electrode, the various piece of described bucking electrode and described drain region and described well region coplane, first dielectric layer is between described bucking electrode and described drain region and well region;
A switch electrode, the various piece of described switch electrode and described well region and described source region coplane, second dielectric layer is between described switch electrode and described well region and source region; With
The 3rd dielectric layer, it is between described bucking electrode and described switch electrode.
2. according to the grid structure of claim 1, wherein said second is identical dielectric material layer with the 3rd dielectric layer.
3. according to the grid structure of claim 1, wherein said first and second dielectric layers are identical dielectric material layers.
4. according to the grid structure of claim 1, a part of coplane of the part of wherein said switch electrode and described bucking electrode.
5. according to the grid structure of claim 1, a part of coplane of the part of wherein said switch electrode, the part of described bucking electrode and described well region.
6. according to the grid structure of claim 5, wherein said common sides is substantially horizontal.
7. according to the grid structure of claim 5, wherein said common sides is vertical substantially.
8. according to the grid structure of claim 1, each of wherein said switch electrode and described bucking electrode comprises conductive material layer separately.
9. according to the grid structure of claim 1, wherein said first, second comprises oxide with the 3rd dielectric.
10. semiconductor device with substrate, described semiconductor device comprises:
A well region, it has first conduction type and is positioned on the described substrate;
A source region, it is limited in the described well region, and described source region has second conduction type;
A drain region, it is adjacent with described well region, and described drain region has described second conduction type;
A grid structure, it comprises a bucking electrode and a switch electrode, the various piece of described bucking electrode and described drain region and described well region coplane, first dielectric layer is between described bucking electrode and described drain region and well region, the various piece of described switch electrode and described well region and described source region coplane, second dielectric layer is between described switch electrode and described well region and source region, and the 3rd dielectric layer is between described bucking electrode and described switch electrode.
11. semiconductor device according to claim 10, wherein said device is built into vertical MOSFET, and further comprise a raceway groove, and it is limited by described well region at least in part and is adjacent with described source region, and described grid structure is positioned at described raceway groove at least in part.
12. according to the semiconductor device of claim 10, wherein said bucking electrode and described switch electrode overlap each other along the part of described channel depth size.
13. semiconductor device according to claim 12, wherein said bucking electrode comprises a top cap portion, described switch electrode has sidewall, this described sidewall defines a depression, described top cap portion is arranged in described depression at least in part, thereby described sidewall is along a part and the described top cap portion overlapping of the depth dimensions of described raceway groove.
14., overlap with described top cap portion on the preset range of wherein said sidewall degree of depth in described raceway groove according to the semiconductor device of claim 13, the preset range of the described degree of depth corresponding to and contiguous described well region.
15. semiconductor device according to claim 12, wherein said bucking electrode has a protruding upper surface, described switch electrode has a recessed lower surface, described recessed lower surface substantially with described protruding upper surface complementation, thereby described switch electrode and described bucking electrode overlap each other along the part of described channel depth size.
16. according to the semiconductor device of claim 15, wherein said switch electrode and described bucking electrode overlap each other on the preset range of described channel depth, the preset range of the described degree of depth is corresponding to also contiguous described well region.
17. semiconductor device according to claim 12, wherein said bucking electrode has a concave upper surface, described switch electrode has a convex lower surface, described convex lower surface substantially with described concave upper surface complementation, thereby described switch electrode and described bucking electrode overlap each other along the part of described channel depth size.
18. according to the semiconductor device of claim 15, wherein said switch electrode and described bucking electrode overlap each other on the preset range of described channel depth, the preset range of the described degree of depth is corresponding to also contiguous described well region.
19. according to the semiconductor device of claim 10, wherein said device is built into vertical MOSFET, described switch electrode is positioned on described source region and the well region at least in part, and described bucking electrode is positioned on described well region and the drain region at least in part.
20. according to the semiconductor device of claim 19, wherein said bucking electrode and described switch electrode overlap each other on described well region.
21. according to the semiconductor device of claim 10, wherein said device is built into side MOSFET, described switch electrode is positioned on described source region and the well region at least in part, and described bucking electrode is positioned on described well region and the drain region at least in part.
22. according to the semiconductor device of claim 21, wherein said bucking electrode and described switch electrode overlap each other on described well region.
23. a technology of making semiconductor device comprises:
Erode away a raceway groove in semi-conductive well region, described raceway groove is adjacent with semi-conductive source region;
Wall and bottom with the first dielectric layer liner raceway groove;
Deposit first conductive material layer;
Thereby corrode first conductive material layer and form a bucking electrode;
Corrode first dielectric layer;
Depositing second layer dielectric layer on the bucking electrode and on the wall of raceway groove; And
Switch electrode of deposition on described second dielectric in described raceway groove.
CNB03817927XA 2002-08-23 2003-08-20 Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses Expired - Fee Related CN100514672C (en)

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