TWI301698B - Improved mos gating method for reduced miller capacitance and switching losses - Google Patents

Description

1301698 Mei, invention description: The case file 60/405, 369 proposed by the State is based on the application of priority in the US application on August 23, 2002. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductors, and is particularly related to metal oxide semiconductor field effect transistors. [Prior Art] Metal oxide semiconductors have a wide range of applications in the field of switches (for example) Power supply t, should be switched) 'and surface oxide transfer field effect transistor _ other types of transistors are not applicable, metal oxide transfer field effect transistor can be applied to;;: or main 疋Because of our high-speed switching capability and extremely low power demand, however, the loss of meaning in the metal oxygen recording field effect transistor wipes accounted for the total loss of the dragon's position - most of the loss. The kinetic energy loss is proportional to the number of times the device is lightly raised and lowered, and is proportional to the drain gate capacitance, that is, the Miller capacitance of the device or (6). The Miller Valley, which is not shown in Figure 3, is effective in the conventional metal oxide semiconductor field. The area of the gate or curve of the transistor is "flat". This area, called the Miller area, represents that the device is being converted from a heterogeneous state to a conducting state, or is being converted from a conducting state to a domain state. Cut the main secret in the life of the county, the electricity and electricity in the county to report the reduction of Miller Valley can reduce the time it takes for the device to switch between conduction and junction state, thus reducing switching losses. The way to reduce Miller's electrical disease is to reduce the range of _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The width of the lin, the width of the m division and the reduction of the overlap IB, however, the ability to reduce the width of the ditch is limited by the ability to engrave the narrow ditch and the need to fill the narrow face with the material. Therefore, what is needed in this technology is to reduce the Miller capacitance of the metal oxide semiconductor field effect transistor _ less switching loss, and more specifically, it is a metal oxide semiconductor with a sag The Miller capacitance of the field effect transistor. SUMMARY OF THE INVENTION The present invention proposes a gate structure suitable for use in a semiconductor device. The form of the invention is composed of the type (4) and the shielding electrode, and the parts of the shielding electrode are disposed on the ship pole Wei, the _ electric age part of the county is placed in the well area and the source is in the switching electrode, the well The second dielectric layer between the region and the source, and the dielectric layer is installed between the shielding electrode and the switching electrode. An advantage of the present invention is that the Miller capacitance of the attack is smaller than that of the prior device. The greater advantage of the present invention is that the wire leakage is switched __ and the city is worn out. [Embodiment] Referring now to the drawings, in particular, in the figure, a schematic cross-sectional view of a sluice gate gate type metal oxide semiconductor field effect transistor device is shown.

The body device 10 includes a drain 12, a well region 14, a body F body & 16, a primary electrode 18' gate electrode 2 and a trench 24, all of which are located on the substrate 26. 1301698 The ocean and field 4 N+ type substrate 26 includes the upper layer coffee constituting the N_dipole 12, the p-type well area extends to the bungee 12, and the upper surface of the upper layer (not edged) and the well area 14 - A highly doped P+ body region 16 is formed in the portion, and a portion of the upper layer and the well region and adjacent trenches 24 form a highly doped N+ source 18, and the side and bottom of the trench ^P (not,曰 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) The upper surface of the upper layer 26a is such that the gate electrode can be connected and the dielectric layer 34 (such as a fine glass) of the beryllium channel region 32 is extended to the portion of the gate electrode 20 and the source 18 The source metal layer 36 extends to the upper surface of the upper layer and contacts the body region 16 and the source μ. Now, the surface Η 2 'the towel shows a schematic cross-sectional view of the lion type of the trench type metal oxide semiconductor field effect electric field device of the present invention, and the metal oxide semiconductor field effect transistor 1 package and more A metal oxide semiconductor field effect transistor has substantially or substantially similar characteristics and structures as a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor includes a immersion 112, a well region 114, and a body. 116, source ι8, gate structure 120 and trench 124, the foregoing are all located on the substrate 126, however, different from the gate electrode 2〇 of the metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect The gate electrode 12() of the transistor (10) includes a dual-gate structure that can reduce the Miller capacitance and increase the switching speed, which will be described in detail. The metal oxide semiconductor field effect transistor 1 is located above the N+ type substrate 126, which comprises an upper layer 126a constituting the N-drain 112, on the upper surface of the upper layer 126a (not 1301698) and the well region 114. The heart constitutes the doped p+ body region, the upper surface of the upper plate, the well region 114 and the adjacent trench 124 and constitute a highly doped N+ source U8, and the lower portion of the side is adjacent to the shielding electrode. The bottom of the trench 124 (not shown) is lined with a dielectric material 128, such as an oxide. The gate electrode (10) of the metal oxide semiconductor field effect transistor (10) is not a single-continuous, uninterrupted single-circuit electrode in the metal oxide semiconductor field effect transistor 10, but is divided into two separate and overlapping switchings. Electrode and shielding electrode, more precisely, the door is connected to the side of the package, please a-axis, please b, the inner dielectric layer is placed over the gate electrode structure, and extended to the source 118, electrode and electrode It consists of a conductive material, such as doped polycrystalline seconds, and is placed in the trench 124. The first or top electrode 120a consisting of a layer of conductive material is horizontally or inwardly recessed into the upper surface of the upper layer 126a. The first/top electrode is started from the first surface of the immediately adjacent upper layer 126a, and extends a certain distance from the bottom of the trench m in a coplanar extension with the source 118, so that the first/top electrode 12〇a and the well 114 are horizontally surface. The second or bottom electrode (4) consisting of the second layer of conductive material is formed by the bottom of the trench 124. The second (electrically) b (lower) part and the bungee ιΐ2 and the well area are knotted. Horizontally coplanar, the other (upper) portion of the first (bottom) electrode 120b is coplanar with the source electrode-electrode 12Ga. Thus, the first electrode is at the depth of the trench 124. Covering each other, the side is adjacent to the switching pen pole 120a and the shielding electrode 12, and the upper portion of the flip is covered with a dielectric material 138, such as the mouth TM, so that the dielectric material 138 will be configured in the _ pole pass and 1301698 as As described above, at least a portion of the shielding electrode 120b and the switching electrode i20a overlap each other with the depth of the trench 124. Particularly in the specific representation of FIG. 2, since the gate electrode 120a is located on the surface, the adjacent shielding electrode 12 is disposed. 〇a constitutes an alcove 丨, between the recessed side 142 and the shielded electrode leg cover portion 144, and surrounded by the side 142, switching the electrode; the side 142 of the 〇a and the shielding electrode 12〇 The top cover portion of b is Μ* in the axial direction or relative to the depth of the trench 丨24 At least some of the directions overlap, thus providing an overlap_door structure. The following will be further advanced, the cover portion 144 of the shield electrode and its ledge 146 are etched to form the shield electrode 丨2〇b The dielectric layer 128 is partially formed on the side, upper and lower sides of the upper surface (not green) of the conductive material layer. Basically, the function of the gate or switching electrode 12A is to switch the electrode to switch the metal oxide semiconductor field effect transistor, and the function of the gate or the shielding electrode (10)b is to form part of the channel 132' in order to make the metal oxide semiconductor field The effect transistor 100 enters the conduction mode, and the bottom/shielding electrode i must be properly pressurized and/or turned on, and the bottom or the shielding electrode can be transferred to the job or material state, or can be pressurized before the event. In order to make it into the man-made job, please prepare #, t bottom / pro-ceremony open, will be controlled by the gate H / bottom electrode thief through the metal oxide semiconductor field effect transistor _ current. As described in the prior art metal oxide semiconductor field effect transistor 10, no, the overlap region 0L between the gate 20 and the drain 12 includes the gate trench 24, and the cymbal ^ π ', under the scoop The gate switching electrode 120a is not overlapped with the drain 112. The gate switching slightly 1301698 is the only overlap between the pole 120a and the drain 112, which is the width w of the channel region 132, and the width is usually several hundred angstroms. The channel 132 is fabricated by applying a voltage to the shielding electrode 120b. The channel 132 is penetrated by the drain 112 along the trench 124 and the shielding electrode 12〇b to the well region 114. Therefore, the metal oxide semiconductor field effect transistor The drain gate overlap (i.e., 1 degree of channel region 132) overlaps the drain gate in the metal oxide semiconductor field effect transistor 1 (i.e., the bottom of the trench 24, typically between 〇.3 and 1 微米 micron) The reason is greatly reduced, so that the Miller capacitance which is substantially proportional to the overlap area of the drain gate is also higher than that of the metal oxide semiconductor field effect transistor 100 in the metal oxide semiconductor field effect transistor 100. Greatly reduced. The improvement (ie, reduction) of the Miller Valley in the MOSFET 1 (10) relative to the MOSFET 10 is shown in Figure 3, which plots the gate voltage of each device. Waveform. The gate voltage waveform of the metal oxide semiconductor field effect transistor VVglQ has a close-to-flat area when the gate voltage Qgate is close to 〇〇(zero) to close to 2 〇〇χ i (rl5 coulombs per micron). The gate voltage waveform Vg(10) of the gold compound semiconductor field effect transistor 100 has almost no such flat area, and therefore, the figure shows a dramatic reduction in the Miller capacitance. It is necessary to pay special attention to avoiding The money in the metal oxide semiconductor field effect transistor 100 causes any significant singularity, and the channel region 132 is when the device is changed from a state in which only the electrode is pressurized to a state in which the gate electrode is pressurized or 12% of the switching gate is also pressurized. Must be present and maintained in the on state, the threshold voltage at which this transition occurs and the final drive voltage strength are determined by the cross-doping concentration at the junction of P-type ray 114 and source 118. Figure 4 shows source 118 at the well The net change stimulation analysis at different depths in zone 114, 1301698 The vertical axis of Figure 4 corresponds to the interface of source 118 and well 114 (i.e., the "top" of well 114), so it will be designated as phase At a value of zero depth at well 114, shield electrode 120b is located at 0.6 to 0.8 microns below zero depth, and the drain side of the well region is located approximately 0.7 to 0.9 microns below zero depth, thus, net doping in well region 114 Quite high, for example, source 118 is approximately 1 〇X, and is reduced by this value to 3. 〇χ 1〇-16 to 15 χ 1 near the portion of well region 114 of shield electrode 120b and drain 112 The doping concentration of 〇-16, the interface between well region 114 and drain 112 can be found by the minimum doping concentration, which is approximately below zero depth 〇·84 to 0.86 μm. Direct and oxidized due to critical and driving voltage The thickness of the material is proportional to the degree of net doping. The aforementioned swarf is used to ensure the use of an oxide layer of sufficient thickness, for example, a thickness of 100 to 1500 angstroms near the pole 112. The increased oxide layer ensures the shadow gate. 12〇b is converted into the switching gate 120a, and the current in the channel region 132 is maintained. During the operation, the shielding electrode 12〇b is boosted or pressurized to a voltage sufficient to maintain the driving voltage potential, in effect, The shielding electrode 120b will place the drain gate overlap region Charging, in part, in the region where the Miller capacitance is generated in the conventional device towel, after the drain gate overlap region is charged by the shield electrode 12Ga, the metal oxide semiconductor field effect transistor should be applied to the switching electrode 12A. The minimum voltage is easily turned on and/or off. The fabrication of the metal oxide semiconductor field effect transistor 100 designed as a vertical trench metal oxide semiconductor field effect transistor can be completed by the bribery process depicted in Figure 1G. _ Until the manufacture of the gate 120, the manufacturing process of the traditionally fabricated trench gate metal oxide semiconductor field effect transistor was used. More specifically, the trench 124 12 1301698 was made by the traditional foot w 3G2 _ shouting 128 (four) cover at the side and the bottom of the ditch 124, this process is more traditional than the first dielectric layer, here

After that, the process of manufacturing a metal oxide semiconductor field effect transistor is different from that of a conventional process. X After the dielectric layer 128 is placed in the first dielectric layer, the first layer of the _ _ will be placed in the side oxidized trench 124, which becomes the part of the shimming step _, and then - The layer conductive material will be laterally the desired thickness at the masking electrode, for example, using reactive ions, etc. Next, the gate dielectric layer 128 is fined in the idle dielectric layer _step 31G. The electrical_step (eg, using the isotropic side) also removes the capping structure 144 of the shielding electrode 12〇b from the specified number of conductive material legs adjacent to the dielectric material 128 and its ledge 146, which may take an additional one or several surnames The engraving step 312 removes sharp edges and/or sharp corners in the shading electrode legs. Next, a gate dielectric layer 138 is disposed in the second dielectric layer placement step 314, and the dielectric layer 138 is applied to the subsequent layer b. The upper surface of the cover 144 _ 146 (the object and the side of the trench 124 above the electrode, then, in the step of placing the switching electrode, the second conductive material is placed in the trench 124, and the remaining step 318 includes the technique Traditional steps and end steps used in . Now please refer to Figure 5, Figure In the second embodiment of the present invention, the gold-based conductor field effect transistor is - 雠 (10) straight metal oxide semiconductor field effect == which contains a metal oxide semiconductor field effect transistor (10) Similar and heavy-duty structure, the metal oxide semiconductor field effect transistor contains many features and structures similar to those of the gold oxide oxide field-effect transistor (10), and the metal oxide semiconductor field effect transistor. Similarly, the metal oxide semiconductor field effect transistor side includes a drain 412, a well region 414, a body, a source 418, and a gate structure 42A, each of which is located on the substrate 426 as compared to the metal oxide. Semiconductor field effect transistor 1〇〇, metal. The oxide semiconductor field effect transistor shed is assembled into a surface-gate vertical metal oxide semiconductor field effect transistor. However, just like the gate structure 12〇, the gate electrode structure is still It includes a double-overlap gate structure that can reduce the capacitance of the conventional metal oxide semiconductor field device and the switching loss. _ Metal oxide semiconductor field effect transistor 4〇〇 is located at N+ The substrate 4 is sunk, the substrate is encased in N; and the upper layer 426a in the pole 412, the P-well region 414 extends to the region of the drain 412, on the upper surface of the upper layer 426a (not shown) and the well region 414 The associated locations form a highly doped P+ body region 416, and the source 418 is also formed by the upper surface of the upper layer and the opposing portion of the well region 414. The source 418 is formed adjacent to and/or connected to the body region 416. The pole 418 is disposed between the body regions 416, and a gate dielectric layer 428, such as an oxide, is applied over the upper surface of the upper layer, and the gate dielectric layer 428 covers a portion of the well region and the source (10) φ. The gate structure 42 of the semiconductor field effect transistor 4 is like the gate electrode structure 120 of the metal oxide semiconductor field effect transistor 100, and is divided into switching electrodes and shielding electrodes which overlap each other, and the gate structure includes a pair of switching electrodes 4 A pair of shield electrodes 420b are applied that are disposed over and/or over dielectric layers 428, 434, and 438. The switching electrode 420a is composed of a layer of conductive material, such as a doped polysilicon, and the electrode is placed on the gate dielectric layer 428, and through the frame, two separate switching electrodes 420a' each switching electrode 42 are formed. Portions of a are disposed above and/or perpendicular to respective source 418 and well region 414, and then switching electrode 420a and gate dielectric layer 428 are covered by second dielectric layer 438, such as The oxide, the portion of the second dielectric layer extending to the gate dielectric layer 428 in the region of the switching electrode 420a is removed in the -way side procedure, and the engraving procedure covers the switching electrode 42〇a, but does not affect the second Dielectric layer side. Next, the second layer of conductive material is formed by placing a second layer of conductive material, such as doped polycrystalline stone, over the first dielectric layer 428 and the second dielectric layer 438. The shield electrodes 42Gb' portions of each of the shield electrodes Na are disposed above and/or perpendicular to the corresponding well regions 4U and adjacent poles 412 to form overlapping double gate structures. In particular, the ship electrode ___ 换 4 4 applies (ie overlaps with it) a predetermined second layer of conductive material, and does not affect the switching electrode, so that each shielding electrode will be placed in the phase The corresponding switching electrode 420a is over and overlapped to form a double overlap table-gate junction which can reduce the Miller capacitance in the conventional metal oxide semiconductor field effect transistor device and improve the switching speed. Next, the inner dielectric layer 434 is applied to the gate structure 42 and the dielectric layer. Referring now to FIG. 6 'more specific embodiment of the present invention, a metal oxide semi-floating semiconductor field effect transistor, which comprises a similar structure to the gate structure of the metal oxide semiconductor field effect transistor side. Double licking the lion. In the _ structure called by the - part of each shielding electrode 42 〇 b covered the corresponding switching electrode she, but in the gate lion, 15 1301698 each switching electrode to listen to the money (also extended or placed above) The opposite portion (not shown) of the electrode 42a should be shielded, and the remaining structure of the MOSFET 50 is substantially similar to that of the MOSFET, and is not described. Now, please refer to phase 7, which is the specific implementation of the metal oxide semiconductor field effect transistor of the present invention. The metal oxide recording circuit is designed to be a side metal oxide semiconductor field effect. The crystal, except for the overlapping gate structure 620, is structurally identical to the conventional metal oxide semiconductor field effect transistor, and the gate structure 62 of the metal oxide semiconductor field effect transistor is divided into a switching electrode 6 and a shielding electrode. The enamel overlaps each other and is particularly disposed on the dielectric layers 628, 634, and 638 and/or above. A layer of conductive material is placed over the gate dielectric layer 628, such as a push-type polysilicon 矽' which is then etched by the surname to mask the electrode. At least some of the components are placed above and/or perpendicular to the well region 614 and the drain 612, and the shielding dielectric 1 620a and the gate dielectric layer 628 are covered with the second dielectric layer. For example, an oxide is then implanted, so that the top and sides of the shield electrode _ are covered by the second dielectric layer 638, and the second dielectric layer 6 is removed from the gate dielectric layer 628. Then, a second layer of conductive material is placed over the first dielectric layer 628 and the second dielectric layer 638, for example, doped polycrystalline sap to make a switch tt620a, and the second layer of conductive material is smashed. The read electrode (4) a, each portion of which is sharply located in the well region 614 and the chic 6= square 'or/or perpendicularly coplanar with it to form an overlapping double Lang structure (10), in particular, a portion of the switching electrode 620a is placed On the second dielectric layer 638, and extending to the shielding electrode 620b to form a reintegration, the Miller capacitance in the bulk of the conventional gold-based semiconductor field-effect transistor 16 1301698 is reduced and the switching speed is accelerated. Now please refer to phase 8, which is still a further embodiment of the present invention. The metal oxide semiconductor field effect transistor 7〇〇 is designed with a metal emulsion half-transfer transistor _ Her __ metal oxide recording semiconductor field effect transistor, but in the metal oxide semiconductor field effect transistor _, the switching electrode gamma knives extend and is heavily shielded by the electrode, in the metal oxide semiconductor field effect transistor 7〇 In the crucible, the structure of the mask electrode 2〇b metal oxide semiconductor field effect transistor surface including the -partial extension and/or overlap with the switching electrode 72〇a is similar to the metal oxide semiconductor field effect transistor 600 I will not repeat them. Referring now to FIG. 9 'This is another embodiment of the present invention _ metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor _ is designed as a trench gate metal oxide semiconductor field effect transistor In addition to the details of the overlapping gate structure 82g, the gate is formed substantially similarly to the metal oxide semiconductor field effect transistor (10), and the gate is formed in a manner similar to that in the heavy gate structure 120. The structure overlaps, and the metal oxide semiconductor field effect transistor _ is formed by separately forming a convex body and a concave body to form a switching and shielding electrode _ opposite or opposite surface to complete the overlapping structure 82 〇. More specifically, the 'metal oxide semiconductor field effect transistor _ includes an overlapping gate structure 820' which is formed in the trench 824 - a switching electrode and a shielding electrode 820b 'the switching electrode 820a has an outwardly convex lower surface The masking electrode has an inwardly concave upper surface 821b' overlying a layer of dielectric layer, which causes the upper surface to have substantially the same curvature as the depressed upper surface 821b, and the switching electrode is disposed in the dielectric material 17 1301698 Above the concave layer of the mass 838, the convex lower surface of the cutting electrode (four) a has almost the same convexity as the concave upper surface, and the concave surface of the concave upper surface _ can ensure the secret electrode _ and the shielding electrode In the direction or depth of the ditch, they overlap each other. Thus, in the metal oxide semiconductor field effect transistor, an overlapping trench door structure that can reduce the Miller capacitance and increase the switching speed is formed. It must be noted that, in the embodiment of the present invention and the foregoing description, the switching electrode 82Ga has a convex lower surface 821a, and the shielding electrode has a concave upper surface.

The concaveness of the concave upper surface 821b and the convexity of the convex lower surface _ overlap such that the switching electrode 820a and the shielding electrode 8 are arranged in a trench-like direction, but it is necessary to understand the field effect of the metal oxide semiconductor. The structure of the transistor _ can also be changed, for example, the switching electrode surface has a concave lower surface 821a, the shielding electrode _ has a convex upper surface 821b, and the convex upper surface of the convex surface and the concave lower surface (4) The concavity is matched to allow the switching electrode 820a and the shielding electrode to overlap each other in a direction or depth similar to the trench to form an overlapping trench gate structure.

In the example of FIG. 2, the side 142 of the switching electrode 12A and the top cover portion 144 of the shielding electrode 1 are partially overlapped in the direction of the trench 124 or in the depth direction to form an overlapping gate Hf. The pole structure, however, the idle structure of the metal oxide semiconductor field effect transistor can also be changed, for example, having the switching electrode have a top cover or projection site and having the shadow electrode have an alcove to provide a similar overlap Gate, pole structure, this is basically a 疋 metal oxide swivel field effect transistor (10) (four) n 12 () ± lower fine version. Although the present invention has a preference for reading, the present invention can still be modified in the spirit of the present disclosure. Therefore, the patent application rate of the present invention attempts to cover any basic use disclosed herein. The original ride is a modification, use, or use of the present invention. In addition, the present patent application is intended to be encompassed by the present invention. ^专利范_ Known or become a customary 10 metal oxide semiconductor field effect transistor 12 N~~ Well electrode 14 well area _ 16 body area 18 N+ source 20 gate electrode 24 trench 26 N+ type substrate 26a substrate upper layer 28 Electrical material 3 〇 conductive material 32 channel region φ 34 inner dielectric layer 36 source metal layer 100 metal oxide semiconductor field effect transistor 112 N-汲 pole 114 well region 116 body region 118 N+ source 120 gate electrode 120a gate electrode First (top) electrode 19 1301698 120b gate electrode, second (bottom) electrode 124 trench 126 N+ type substrate 126a substrate upper layer 128 dielectric layer 132 channel region 134 inner dielectric layer 138 dielectric material / dielectric layer 140 concave room

142 side 144 top cover part 146 ledge 300 process flow 302 times ditch 304 placement of first dielectric layer 306 placement of shielding electrode 308 etching shielding electrode 310 gate dielectric layer etching 312 additional money engraved

314 is disposed in the second dielectric layer 316 to place the switching electrode 318. The remaining step 400 metal oxide semiconductor field effect transistor 412 N-drain 414 well region 416 body region 418 N+ source 420 gate structure 420a switching electrode 20 1301698 420b shielding electrode 426 N+ type substrate 426a substrate upper layer 428 dielectric layer 434 dielectric layer 438 dielectric layer 500 metal oxide semiconductor field effect transistor 512 N-drain 514 well region 516 body region 518 N+ source electrode 520 gate structure 520a switching electrode 520b Masking electrode 526 N+ type substrate 528 dielectric layer 534 dielectric layer 538 dielectric layer 600 metal oxide semiconductor field effect transistor 612 N-汲 pole φ 614 well region 616 body region 618 N+ source 620 gate structure 620a switching electrode 620b Masking electrode 628 first dielectric layer 634 dielectric layer 638 second dielectric layer 21 1301698 700 metal oxide semiconductor field effect transistor 712 N-drain 714 well region 716 body region 718 N+ source 720 gate structure 720a switching electrode 720b shielding electrode 800 metal oxide semiconductor field effect transistor 812 N-nopole

814 well area 816 body area 818 N+ source 820 gate structure 824 trench 820a switching electrode 820b shielding electrode 828 dielectric layer 834 dielectric layer 838 dielectric layer

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing invention, as well as other features and advantages of the invention, and aspects thereof, may be 1 is a schematic cross-sectional view of a prior art trench metal oxide gate structure technique. 2 is a schematic cross-sectional view of a metal oxide semiconductor gate structure of the present invention. 3 is a waveform diagram of a prior art metal oxide semiconductor gate structure and a metal oxide semiconductor 22 1301698 gate structure of FIG. Doping analysis curve FIG. 4 is a schematic diagram of a typical surface of a gold-Wide-transformed surface of FIG. 2, which is a schematic diagram of a metal oxide semiconductor field effect electro-optic suspension of the present invention. ——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————— A schematic cross-sectional view of the oxide semiconductor idle structure is a specific flow chart for manufacturing the apparatus of "2. Corresponding reference element symbols are set forth in the various figures to illustrate the specific ways in which the invention may be applied. Where the corresponding parts are indicated, the scope presented here, but this example should not be interpreted as a

twenty three

Claims (1)

'Scope of application: 1. - Improved metal oxide semiconductor _ to reduce _ capacitance and switch damage dry, is a gate structure for semiconductor devices, the semiconductor device is decorated with poles, wells and sources, the gate The structure comprises: - a shielding electrode, each part of the ship electrode is disposed in the shared plane of the secret, and a first dielectric layer is disposed in the shielding electrode and the drain and the well interval; The young families are placed in the common plane of the simplification and the second dielectric layer is disposed between the switching electrode and the well region and the source; and a third layer interposed between the shielding electrode and the switching electrode The electrical layer; wherein the shielding electrode overlaps at least a portion of the switching electrode. 2. The apparatus of claim 2, wherein the second and third dielectric layers are the same dielectric material layer. 3. The apparatus of claim 1, wherein the first and second dielectric layers are the same dielectric material layer. 4. The device of claim 1, wherein the switching electrode and a portion of the shielding electrode are disposed in a common plane. 5. The apparatus of claim 1, wherein a portion of the switching electrode, a portion of the shielding electrode, and a portion of the well region are disposed in a common plane. 6. If you apply for the device described in the fifth section of the patent shop, the plane of the center is usually flat. 7. If Shen Qing 5 is general, Che (4) 砰 (10) is often hang 24 straight. 8. The skirting electrode and the shielding electrode of the device are composed of conductive material layers as described in the scope of the patent application. 9. If you apply for a patent scope! The device of the item, wherein the first, second and third dielectric layers of the device consist of an oxide. 1〇·If you apply for the special machine, the I set in item 1, the device is composed of the towns: a well area, covered with the first conductivity type on the substrate; the source is defined in the well area, The source uses a second conductivity pattern; a drain electrode extends in the well region, the drain electrode uses the second conductivity pattern; and the gate structure includes a shielding electrode and a switching electrode, and the shielding electrode is associated with the portion The pole is shared with the well area, and the relevant portion of the switching electrode disposed on the ship electrode and the ship and the well region shares a plane with the well region and the source, and the second dielectric layer is placed in the switch Between the electrode and the source, a third dielectric layer is disposed between the shielding electrode and the switching electrode; wherein the shielding electrode overlaps at least a portion of the switching electrode. U. The device described in claim 1Q, wherein the device is designed as a vertical metal oxide semiconductor field effect transistor and includes a portion of a trench defined by the well region. And the door structure is partially disposed in the ditch. The device of claim 1, wherein the shielding electrode and the switching electrode partially overlap each other along the depth of the trench. 13: The device of claim 12, wherein the shielding electrode has a top 25 cover portion, the switching electrode having a side edge, an alcove defined by the side boundary, the top cover portion to the 乂There is a portion located in the recess such that the side portion partially overlaps the top cover along the trench depth quadrant. 14. The n-set as described in item 13 of the application of the reticle is overlapped with the top cover and the side edges within a predetermined depth range of the slat, the predetermined depth range corresponding to and adjacent to the well area. [15] The apparatus of claim 12, wherein the shielding electrode has a convex upper surface, and the __ pole has a lower surface, and the concave lower surface substantially cooperates with the convex upper surface, so that The switching electrode and the shielding electrode partially overlap each other along the depth of the trench. 16. The skirt of claim 15, wherein the switching electrode and the shielding electrode overlap within a predetermined depth range of the trench, the predetermined depth range corresponding to and adjacent to the well region . R is the device according to the item -12, the shielding electrode in the device has a concave upper surface, and the surface of the lower surface of the device is larger than the upper surface of the concave surface, so that the surface of the electromechanical field is covered. The electrodes partially overlap each other along the quadrant of the groove. The X is in the well region and is contiguous thereto. 18. The device of claim 15, wherein the switching electrode and the shielding electrode overlap with a predetermined depth in the trench, the predetermined depth range The corresponding tantalum device is designed as a vertical metal. 19. The splitting device according to the first aspect of the patent application, 26 oxide semiconductor % effect transistor, the switching electrode is disposed with a portion located above the source and the well region. This is the place to be placed - some of which are located above the light and the poleless. 20. The shield electrode in the device of the device (4) according to claim 19, and the switching electrode overlap each other above the well region. [4] The apparatus of claim 10, wherein the device is designed as a side metal oxide semiconductor field effect transistor, and the switching electrode is partially disposed above the source and the well region, and the shielding electrode is disposed. Some parts are located in the well area and above the pole. 22. The device of claim 21, wherein the shielding electrode of the center and the switching electrode overlap each other above the well region. 23. A method for improving metal oxide semiconductor closed-gate to reduce Miller capacitance and switching loss, and is a program for manufacturing a semiconductor device, the program comprising: at the semiconductor, the surface of the (four) body; The layer is used as the wall of the trench and the bottom of the trench; the first conductive material layer is placed; the first conductive material is engraved to form a shielding electrode to etch the first dielectric layer; and the first layer is placed above the shielding electrode and above the wall surface of the trench A switching electrode is disposed above the second dielectric layer of the trench (10). s,, pick up, pattern: 27 1301698 \2Η ί; 1 one by one ' , :;i >< ι ” 10 100 Figure 2 (designated representative map) -1.0 0.0 1.0 2.0 3.0 Qgate (10^15 C/1〇-*6m) 4.0 5.0 x10·15 Figure 3 Net doping Figure Well area Bole side μ I μ 1111111111111 in 111111 In 11111111 i\/i 1 ill 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Depth below source (MICRONS) Net doping analysis 400 600 712 - 〆 800 Figure 9 300 〆 Figure 10