TW201232782A - Semiconductor device formed on semiconductor substrate having substrate top surface and preparation method thereof - Google Patents

Abstract

The present invention discloses a semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.

Description

201232782 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a semiconductor element formed on a semiconductor substrate having a top surface of a substrate and a method of fabricating the same. [Prior Art] [0002] Many of today's electronic circuit designs have stringent requirements for component performance parameters such as switching performance and on-state resistance. Power MOS components are commonly used in such circuits. The mask gate trench metal oxide semiconductor field effect transistor (MOSFET) is a power MOS device with good high frequency switching performance and very low on-state resistance. Mask Gates MOSFET's existing fabrication techniques are complex and expensive, requiring six or more masks to be used during processing. Existing technologies also have high defect rates. The fabricated components typically have high contact resistance and transient characteristics are extremely unstable. SUMMARY OF THE INVENTION [0003] This application is a continuation-in-part application of U.S. Patent Application Serial No. 12/583, filed on Jan. The corresponding case of the case is hereby incorporated by reference. The present invention provides a mask gate trench metal-oxide-semiconductor field effect transistor with an enhanced source-metal joint suitable for larger source-metal contact regions and lower contact resistance. More reliable and more stable transient response. [0005] In order to achieve the above object, the present invention provides a semiconductor device formed on a semiconductor substrate having a top surface of a substrate, comprising: 10110271^WA〇101 4th page/total 43 page 1012004880-0 201232782 [0006] a gate trench extending from a top surface of the substrate to the semiconductor substrate; [0007] a gate electrode in the gate trench; [0008] a gate top dielectric material deposited over the gate electrode; [0009] a body region adjacent the trench of the gate; [0010] a source region embedded in the body region, at least a portion of the source region extending over the top dielectric material of the gate; [0011] a source region and Contact trenches in contact between the body regions; and f) 1 [0012] a metal layer deposited over at least a portion of the gate trench openings, at least a portion of the source regions, and at least a portion of the contact trenches. Preferably, the metal layer covers the gate top dielectric material 'over the gate electrode and contacts the sidewall of the source region opposite the gate dielectric material. [0014] Preferably, the semiconductor device of the present invention further comprises a mask electrode formed in the gate trench, the gate electrode and the mask electrode being separated by an inter-electrode dielectric material. Preferably, the source region has a substantially vertical surface with at least a portion of the substantially vertical surface in direct contact with the metal layer. [0016] Preferably, the gate trench has an at least partially curved trench sidewall. [0017] Preferably, at least a portion of the surface of the source region conforms to a curved portion of the sidewall of the trench. [0018] Preferably, the metal layer is in contact with the source region on a plurality of edges. 10110271#^ A〇101 Page 5 of 431012004880-0 201232782 [0019] Preferably, on one edge of the source region opposite the contact trench, and the source region opposite the gate top dielectric material On one edge, the metal layer is in contact with the source region. [0020] Preferably, the top surface of the gate top dielectric material is recessed below the top of the source region. [0021] Preferably, the contact trench is filled with at least a portion of a conductive plug. [0022] According to the purpose of the present invention, a method for fabricating a semiconductor device is further provided, the method comprising: [0023] preparing a gate trench; [0024] preparing a gate electrode in the gate trench; Preparing a gate top dielectric material over the top of the gate electrode; [0026] preparing a body region and a source region; [0027] preparing a contact trench; [0028] etching the gate top dielectric material to At least a portion of the source region extends over the gate top dielectric material; [0029] depositing a metal layer over at least a portion of the gate trench opening, at least a portion of the source region, and at least a portion of the contact trench. Preferably, the method further comprises the step of preparing a mask electrode in the gate trench before preparing the gate electrode. Preferably, the method further comprises the step of preparing an interelectrode dielectric between the mask electrode and the gate electrode. 10110271#单编号A〇101 Page 6 of 431012004880-0 201232782 [0032] Preferably, the gate top dielectric material is etched back and a metal layer is deposited such that the metal layer covers the top of the gate above the gate electrode a dielectric material and contacting a sidewall of the source region opposite the gate top dielectric material. [0033] Preferably, the top surface of the gate top dielectric material is recessed below the top of the source region. Preferably, the source region has a substantially vertical surface with at least a portion of the substantially vertical surface in direct contact with the metal layer. [0035] Preferably, the gate trench has an at least partially curved trench sidewall.

D

[0036] Preferably, at least a portion of the surface of the source region conforms to a curved portion of the sidewall of the trench. [0037] Preferably, the metal layer is in contact with the source region on a plurality of edges. Preferably, the metal layer is in contact with the source region on one edge of the source region opposite the contact trench and on one edge of the source region opposite the gate dielectric material. q [〇〇39] Preferably, the method further comprises the step of depositing at least a portion of a conductive plug within the contact trench. Preferably, the metal layer forms a conductive plug at least partially within the contact trench. [〇〇41] The present invention has an advantage that the masked gate trench metal-oxide-semiconductor field effect transistor with the enhanced source-metal joint is superior to the prior art in that the present invention is applicable to a larger source - The metal contact area and low contact resistance are more reliable and have a more stable transient response. [Embodiment] 1012004880-0 1 () 11 () 271f single number A0101 page 7 / total 43 pages 201232782 [0043] [0044]

The invention can be implemented in a variety of different ways, including a process system: material composition. In some embodiments, the present invention can be controlled by a computer program worn on a readable storage medium and/or processing H, such as configuration processing 11 'storing stored and/or remaining on the processor. Command in the body. In the nuclear towel, these H can be used in any other form, which is called technology. In general, the order of the process steps may vary within the scope of the invention. Unless otherwise specified, the above-mentioned components such as the processor or the memory used to perform the task may be temporarily configured as a component, or as a special component for performing tasks. preparation. The term "processor" as used herein refers to a component, circuit, and/or processing core for processing data, such as computer program instructions. The present invention is shown by the following figures, and the invention described in detail above or in detail of the invention is related to these embodiments, but the invention is not limited to the embodiments. The scope of the present invention is only the claims of the present invention, and the present invention contains various changes, equivalents, and equivalents. The specific details mentioned in the following description are for the purpose of understanding the invention. These details are only used to exemplify the specific details of some or all of the invention, and may be based on the claims. For the sake of clarity, the technical field of the prior art is not described in detail in order to avoid unnecessary misunderstanding. The present invention proposes a material gate FET component and a fabrication technique (4) embodiment. Preparation Techniques Nitride spacers use a self-aligned contact system. The resulting mask gate MGSFET device has a recessed gate dielectric suitable for larger source-to-metal contact regions and lower contact resistance. This is the eighth page of the total number of pages (8), the number of the production order number _ 1012004880-0 201232782 [0045] [0047] [0047] The component is more · 5τ soil crime has a more stable transient response. "Flowchart not shown" represents an embodiment of a mask gate MOSFET fabrication technique. Step Μ η 、 , , one or more gate contact openings are formed at least partially on the semiconductor 4 c u earth plate. In step 104, a nitride spacer is formed inside the gate trench opening. . The gate trench can be left to self-align to the nitride pad. During subsequent processing, the die prevents the substrate from becoming singular and forms an aligned contact trench. In step 106, the mask electrode and the gate electrode are formed in the trench pattern 3 . The dielectric material fills at least a portion of the trench and separates the mask Φ 4^ ^ from the gate electrode. The mask electrode protects the gate electrode from the south voltage*彡鄕. Know the sound. In step 108, dopants for preparing the body and the source are implanted in the substrate. Step 丨, the contact trenches are formed in a self-aligned manner without any additional mask. In step 112, a conductive plug is deposited in the contact trench. Step 114, etching back the dielectric material in the gate trench such that at least a portion of the source region extends over the dielectric material. Step 116, depositing a metal layer over at least a portion of the gate trench opening, at least a portion of the source region, and at least a portion of the contact trench. The metal layer forms a pattern in the source and gate metal. In some embodiments, the source metal can include a top metal layer and one or more contact trench plugs that contact the source regions on multiple edges to reduce contact resistance and make the components more reliable. The technical diagrams shown in Figs. 2 to 26 show an embodiment of the component preparation technique. In the following discussion, an N-type component is illustrated by way of example. P-type components can also be fabricated using similar techniques. Figures 2 through 5 show the initial steps in preparing the gate trenches. 10110271#单编号 A0101 Page 9 of 43 1012004880-0 201232782 [0048] In FIG. 2, an N-type substrate 602 is used as the drain of the element. In this example, the N-type substrate is an N + day wafer, and the N- epitaxial layer is grown on the surface of the wafer. In some embodiments, the doping concentration of the epitaxial layer is about 3E16 -1E17 dopant / cm3, the thickness is 2-4 um, and the substrate resistivity is 0. 5 - 3 mohm * cm ° [0049] Deposition or thermal oxidation is formed on the substrate. A nitride layer 606 is deposited over the tantalum oxide layer. In some embodiments, the tantalum oxide layer has a thickness of about 500 to 1500 Å and the nitride layer has a thickness of about 1500 Å. [0050] A photoresist (PR) layer is then applied over the nitride layer and patterned using a first mask (also referred to as a trench mask). In the following discussion, for the sake of explanation, it is assumed that a positive PR is used, thereby leaving the unexposed area and removing the bare area. You can also use a negative PR, just modify the mask accordingly. The mask defines an active gate trench. The mask can also define other trenches, such as source polysilicon attracting trenches and gate/cutoff trenches, which are not shown in this figure. 6 um。 In some embodiments, the width of the active trench is about 0. 6 um. Components can be prepared using a low profile mask with a critical dimension of 0.35 um to reduce the cost of the mask required. [0051] In FIG. 3, the residual PR layer 701 defines an active gate trench opening 702. In some embodiments, additional trenches such as source polysilicon attracting trenches and gate runners/cutoff trenches may be prepared, but germanium is not shown in this figure [0052] and then etched using a hard mask (HM) The exposed portions of the nitride layer and the tantalum oxide layer are etched away. The etching terminates on the surface of the crucible. Then remove the remaining 10110271# early number A0101 page 10 / total 43 pages 1012004880-0 201232782 [0054] [0055]

[0056] PR. In Fig. 4, a trench opening is formed in the exposed region while a hard mask is formed through the remaining nitride-oxide portion. A trench etch is then performed to etch into the semiconductor material 602 in the trench opening. Depending on the etching method, the trench sidewalls may be substantially straight (as shown in Figure 5A) or curved (as shown in Figure 5B). In some embodiments, the target depth of the trench is about 0.3 um to 0.5 um. In the trench opening, a very thin oxide layer is deposited or thermally grown to fill the trench bottom and trench sidewalls. In some embodiments, the oxide layer has a thickness of about 200 Å. Once the oxide layer is formed, an additional nitride layer 900 can be deposited. Only a very thin oxide layer is required under the nitride and is therefore not shown separately in the figure. In some embodiments, the additional nitride layer has a thickness of between about 1500 A and 2200 A. In some embodiments, the nitride layer has a thickness of about 1500 Å. As shown in Fig. 6, the nitride layer 900 is filled with trenches and covers the remaining bare regions. As shown in Fig. 7, after the full anisotropic etchback, the nitride spacer 100 and the like are formed along the sidewall of the trench. The initial nitride layer 606 portion is also retained. Then, the exposed liner oxide layer in the bottom of the trench opening is removed, and the trench between the nitride spacers in Fig. 8 is further deepened by a full-surface germanium etching technique. According to the _ of the component, the groove depth is about 1.5 ura~2. 5 um, and the inclination angle of the sidewall of the groove is about 87° to 88°. Nitride spacers allow the self-aligned etch technique to eliminate the need for an additional alignment step such as an alignment mask, thereby enabling oblique etch of the trench. The depth of the trench ranges from a few hundred angstroms to a few microns. Use 250 A~500 A round hole 10110271#单号崖01 Page 11/43 page 1012004880-0 201232782 (R/Η) Surname engraved to make the corner of the groove more rounded to avoid the south electric field caused by the acute angle . [0057] In FIG. 9, one or more oxide layers are deposited or thermally grown. In some embodiments, a sacrificial oxide layer of about 5 Å A can be grown and removed to improve the ruthenium surface. As an example, an oxide layer of about 250 A can be grown in the trench and then a high temperature oxide (?0) of about 900 A can be deposited. [0058] As shown in FIG. 1, polycrystalline germanium is deposited. In some embodiments, the polysilicon has a thickness of about 1 2000 A, which is greater than half the width of the widest trench in the component (not showing the widest trench). Therefore, the polycrystalline germanium layers on the sidewalls are bonded together to completely fill the trenches. This layer of polycrystalline germanium is sometimes referred to as source polycrystalline litter, masked polycrystalline litura or polycrystalline lit. [0059] Then, as shown in FIG. 11, the source polysilicon is etched back by dry etching. In this example, the remaining polycrystalline shreds are approximately 6000 A in the active thumb-channel. C〇〇6〇] Then, a high density plasma (HDP) oxide 1 506 is deposited and densified. In some embodiments, the densification is continued for about 30 seconds at a temperature of about 115 {rc. As shown in FIG. 12, the thickness of the oxide 15〇6 is greater than half the width of the active trench (in some embodiments, the thickness of the oxide layer is about 2000 A to 4000 A), thereby completely filling the active trench. . [0061] Oxidation chemical mechanical polishing (CMP) is performed. As shown in Fig. 13, the oxide is polished by the CMP technique until the top surface of the oxide is level with the nitride surface, thereby serving as the end point of the remainder. [0062] Figure 14 shows the addition of another oxide layer. In some embodiments, the oxidation is 10110271 #军号 A01〇l Page 12 of 43 1012004880-0 201232782 The thickness of the layer is about 100 〇 A-2000 A. The thickness of the oxide layer controls the angle of the wet etched undercut of the second mask. The oxide film also protects the nitride in all of the non-active regions of the element. The protected nitride can be subsequently subjected to a maskless full-scale engraving of Si. [0063] In some embodiments, a photo-resistance agent is spin-coated on the surface of the structure and a PR pattern is formed using a second mask (also known as a polysilicon overlay mask). The area covered by the PR (e.g., the cut-off trench, not shown in the figure) is not affected by the wet residual of the oxide. In the illustrated embodiment, active trench regions that are not covered by PR are susceptible to wet etching of the oxide. [Delete] Then, wet etching is performed. The results of the wet etching are shown in Fig. 15. The oxide in the area not covered by the PR is removed, leaving the remaining oxide at the desired height. The oxide layer above the polycrystalline stone, such as the oxide layer 1908, is referred to as a polycrystalline interstellar dielectric (ipd), which may range from a few hundred angstroms to several thousand angstroms. [0065] In some embodiments, 'asymmetric oxide cut-off/gate chute trenches' are formed. For these embodiments, the steps shown in Figures 13 through 15 are optional. Alternatively, the oxide 1506 in Fig. 12 can be directly etched back to form an IPD (Oxide Layer) 1908 as shown in Fig. 13. [0066] If PR is used, it is then removed and a layer of gate vapor is deposited or thermally grown. In some embodiments, the additional oxide layer has a thickness of about 450 Å. Therefore, in Fig. 16, the gate oxide is filled with active trench sidewalls 2004 and 2006 and the like. [0067] Another polycrystalline germanium deposition was performed and etched back. The result is shown in Figure 17. The polycrystalline germanium is deposited to fill the trench. In some embodiments, approximately 〇. 5-1 uin of 1011027# single number A_ page 3 of 43 1012004880-0 201232782 polycrystalline stone deposited in the trench. The deposited polysilicon is etched back to form gate polysilicon electrodes 2104 and 2106. The top of the gate polysilicon at least hits the bottom of the source. In some cases, it also overlaps the bottom of the source, so that a channel can be formed. In some embodiments, the polysilicon surface is about 500-5000 A below the bottom of the nitride pad. Alternatively, deposit a layer of titanium or a noble metal and anneal. A polycrystalline fragmentation layer is formed where the metal is in contact with the polysilicon. The metal titanium or the imide/polycrystalline telluride above the oxide or nitride can be removed. As shown, polycrystalline lithidies 2112 and 2114 are formed over the gate polycrystalline iridium electrodes 21〇4 and 216. [0068] In FIG. 18A, the exposed nitride pad near the active gate trench is removed, for example, by a wet etching technique, and the nitride layer 上方 [〇〇69] above the oxide hard mask is In the examples, various prior heat treatment techniques (e.g., oxide deposition, HDP oxide densification) cause ruthenium oxidation in the interface region, while nitrides in the same region are less oxidized. Due to the localized deuteration (LOCOS) of the tantalum process, the surface of the substrate of the nitride spacer is changed to become curved. This phenomenon is well known in the art as the "bird's beak effect." In addition, various prior art techniques have caused the nitride spacer to be eroded in a specific area, further exposing the nitride-ruthenium interface to ritualize it. Therefore, as shown in Fig. 18B, when the nitride crucible and other bare nitride materials are removed by the wet rice engraving technique, the remaining trench side walls may have a curvature. 〇] implant the body and source of the component. The body and source of the implanted component do not require an additional mask. Specifically, in the 19th and 11th drawings, the 10110271 production order description _1 the 14th page/the 43rd page 1012004880-0 201232782 [0071] ❹ [0072] Ο [0073] [0074] . The element is bombarded with an angled dopant ion. Nitrogen can be used to protect specific areas of the element (not shown). In the active region that is not protected by nitride, the implant forms body region 2304. In some embodiments, an N-channel component is fabricated using a shed ion having a doping level of about 1.8 el3 at 60 KeV, 180 KeV. Other types of ions can also be used. For example, a p-channel element is prepared using phosphorous ions. Source implantation is performed with a zero tilt angle in Figs. 20A and 20B. The element is again bombarded with dopant ions. In some embodiments, at 4 〇j (eV~80KeV, an arsenic ion having a doping level of 4e 丨 5 is used. A source region 2402 is formed in the body region 2304. In the second 〇B diagram, the source The surface of the polar region conforms to the curved shape of the sidewall of the trench. In FIGS. 21A and 21B, a dielectric layer (eg, an oxide layer) is deposited, filling the trench opening, and separating the source and gate polysilicon regions. In embodiments, the thickness of the oxide layer ranges from 5 〇〇〇A to 8 Å () A. In some embodiments, low temperature oxidation of about 5000 A is deposited using chemical vapor deposition (CVD) techniques. (LTO) and neodymium glass (BPSG) containing boric acid. In layers 22A and 22B, the oxide is etched back by dry etching. In this example, the oxide is etched down to top the oxide. It is lower than 500 A ~ 1〇〇〇a of the top surface of the substrate. The oxide hard mask formed in Figures 2 to 4 can also be removed by this technique. It can also be selected (for example, by chemical mechanical polishing (cMp) technology Flattening the oxide so that the top surface of the oxide is level with the top surface of the substrate. Figure 22C shows This is an alternative. 1Q11Q2^Material No. 1 Page 15 of 43 1012004880-0 201232782 [0075] In FIGS. 23A and 23B, the substrate is etched to form a contact trench 2702. According to the use of the component The etch depth is between 0.6 um and 0.9 um. The exposed substrate area is etched, and the area not protected by the oxide is not etched. Since the etching technique does not require an additional mask, it is also referred to as a self-aligned contact technique. In this case, the contact trench is self-aligned to the remaining portion of the oxide 2704. As shown in Fig. 23B, after etching the contact trench, a bottom (at the implant) can be selected (e.g., implanted) at the bottom of the contact trench. Heavyly doped P + body contact region. [0076] In FIGS. 24A and 24B, it is possible to selectively deposit barrier metals such as Ti and TiN (not specifically shown), and then form Ti near the contact region by RTP. Telluride. In some embodiments, the Ti and TiN used have thicknesses of 300 A and 1000 A, respectively. Then, a conductive plug material such as tungsten (W) is deposited. In some embodiments, 4000 A to 6000 A is deposited. W. Back to the deposited W, up to the base The surface of the board is formed to form a separate conductive (W) plug 3002. [0077] In the 25A and 25B, oxide etching is performed. The oxide layer is etched back. The etching technique removes the source and active gate trenches. An oxide layer above the opening, and a portion of the oxide layer in the gate trench, causes the remaining oxide layer in the gate trench to be recessed toward the top surface of the source. In other words, the top surface of the formed oxide layer is lower than the source The top surface. In some embodiments, the top surface of the oxide layer is approximately 500-1000 A lower than the top surface of the source region. As will be discussed below, for source-to-metal contact, the etch technique exposes more source regions. [0078] Alternatively, after contact trenches 2702 in FIGS. 23A and 23B, and to prepare conductive Prior to the plug 3 0 0 2, this oxide etchback technique was performed 1011027#^ A〇101 page 16 of 43 pages 1012004880-0 201232782. In an optional implementation, the 24C and 24] diagrams show the oxide etchback techniques of Figures 25A and 25B, but before the fabrication of the conductive plug 3002. In this alternative embodiment, after the structures shown in Figs. 24c and 24D are prepared, a conductive plug is deposited to form the structures shown in Figs. 25A and 25B. In the examples of FIGS. 26A and 26B, a metal layer is deposited by using AlCu to form a layer of about 3 um. In some implementations um thick metal layer Ο. The metal is then annealed at 45 (TC for about 3 minutes. In some embodiments, a pattern of metal is formed, the source and gate metal are prepared, and connected to the source through additional trenches (not shown) And the gate region. The top of the final element is formed. Although not shown, a metal layer can be formed at the bottom of the substrate, usually after the back grinding technique.

In the fabricated device, each active gate trench contains a top polysilicon electrode (eg, polysilicon 3312), which is also referred to as a tree polymorph or a thumb electrode because it acts as a gate, or It is formed in the second polycrystalline germanium deposition technique during preparation, and is therefore also referred to as polycrystalline germanium. Each top poly germanium electrode also includes a polycrystalline germanide layer 3340' deposited on the top surface of the gate electrode to improve conductivity along the gate. Each trench also includes a bottom polysilicon electrode (eg, polysilicon 332 〇), which is also referred to as a source polysilicon or source electrode due to its connection to the source, or because it is formed in the first polysilicon during fabrication. The deposition technique 'is therefore also referred to as polysilicon 1 or because it masks the gate polysilicon from high voltages' is therefore also referred to as a mask polysilicon or a mask electrode. A polycrystalline inter-turn dielectric region made of an oxide separates the source polysilicon from the gate polysilicon. In the active gate trench shown in this example, it is surrounded by 10110271^^ A〇101, page 17/43, 1012004880-0 201232782, and the oxidation of the top sidewall of the trench. The layer (e.g., emulsion layer 3324) is thinner than the oxide layer (e.g., oxide layer 3326) that surrounds the source/mask polysilicon and is lined with the sidewalls of the bottom of the trench. In the active region, the source metal 3334 is insulated from the gate electrode such as 3312 by a dielectric layer such as a germanide 33〇9. The source metal layer 3334 is electrically connected to the source region 3332 and the body region 3348 through a conductive plug 3330' such as a tungsten plug, and the conductive plug 3330 fills the source body contact opening and extends from the source metal into the body region. The body contact implant region 3346 enhances the ohmic contact between the body region and the conductive plug 3330. [0081] The above process produces a MOSFET component with an enhanced source-metal contact region. Specifically, since the source region extends over the top surface of the gate oxide, a single source region has a plurality of surfaces in contact with the top metal (e.g., source metal layer 3334 and conductive plug 3330). For example, the top metal is connected to the source region, on the source region surface 3302 opposite the contact trench, on the source region surface 3306 opposite the recessed oxide 33〇9, and on the source region surface 3304. An oxide 330 9 recessed over the gate region connects the metal to the source sidewall 3306 opposite the recessed oxide. The enhanced source-metal contact area reduces contact resistance and makes the transient response more stable. Moreover, the enhancement zone means that there is very little chance of contact with defects, so the components are more reliable and the yield is higher. In some embodiments, the conductive plug 3330 is made of the same material as the source metal layer 3334, as shown in Figure 26C. In this case, the conductive plug 333A can be prepared/filled simultaneously with the remaining source metal layer 3334. [〇〇82] Most of the above examples are described using N-channel components. As long as the polarity of various dopants is changed, the above process can be applied to p_channel 1 (3110271#single number A0101 page 18/total 43 page 1012004880-0 201232782 components. [0083] Although for ease of understanding, The specific details of the above embodiments are not limited to the details. The present invention has many alternative implementation methods. The embodiments are for explanation and are not intended to be limited. [Simplified illustration] 0084] The flowchart shown in FIG. 1 shows an embodiment of the mask fabrication technique of the mask gate MOSFET. The schematic diagrams shown in FIGS. 2 to 26C show an embodiment of the component fabrication technique. 〇 [Main component symbol description] [0085] ~116: Step 602: N-type substrate 604: germanium oxide layer 606, 900: nitride layer

701 : PM 702 : trench opening 1 000 : nitride spacer ❹ 1 506, 2704, 3309 : oxide 1908, 3324 ' 3326 : oxide layer 2004, 2006 : active trench sidewall 21 0 4, 210 6 : gate Very polycrystalline germanium electrodes 2112, 2114: polycrystalline lithiate 2304, 3348: body region 2402, 3332: source region 2702: contact trenches 3002, 3330, 3330': conductive plug 10110271, single number deletion 1 page 19 / total 43 f 1012004880-0 201232782 3302, 3304, 3306: source region surface 3312: gate electrode 3 3 2 0 : polysilicon 3334: source metal layer 3340: polycrystalline germanide layer 3346: implant region 10110271^·single number A〇 101 1012004880-0 Page 20 of 43

Claims (1)

201232782 VII. Patent application scope: 1. A semiconductor device formed on a semiconductor substrate having a top surface of a substrate, comprising: a gate trench extending from a top surface of the substrate into the semiconductor substrate; a gate electrode in the trench; a gate top dielectric material deposited over the gate electrode; a body region adjacent the stem trench, a source region embedded in the body region, at least a portion The source region extends above the gate top dielectric material; a contact trench that contacts the source region and the body region; and a portion of the gate trench opening that is deposited in at least a portion of the gate trench opening a source region and at least a portion of the metal layer over the contact trench. 2. The semiconductor device of claim 1, wherein the metal layer covers the gate top dielectric material over the gate electrode and contacts a sidewall of the source region opposite the gate top dielectric material . 3. The semiconductor device of claim 1, further comprising a mask electrode in the gate trench, wherein the gate electrode and the mask electrode are separated by an inter-electrode dielectric material separate. 4. The semiconductor component of claim 1, wherein the source region has a substantially vertical surface, at least a portion of the substantially vertical surface being in direct contact with the metal layer. 5. The semiconductor component of claim 1, wherein the gate trench has an at least partially curved trench sidewall. 6. The semiconductor device of claim 5, wherein at least a portion of the surface of the source region conforms to a curved portion of the sidewall of the trench. The semiconductor element of claim 1, wherein the metal layer is in contact with the source region on a plurality of edges. The semiconductor device of claim 1 is as claimed in claim 1 . 8. The semiconductor device of claim 1, wherein an edge of the source region opposite the contact trench and an edge of the source region opposite the gate top dielectric material The metal layer is in contact with the source region. The semiconductor component of claim 1, wherein the top surface of the dielectric material is recessed below the top of the source region. The semiconductor device of claim 1, wherein the contact trench is at least partially filled with a conductive plug. 11. A method for fabricating a semiconductor device, the method comprising: preparing a gate trench; preparing a gate electrode in the gate trench; and injecting a gate top dielectric material over the top of the 4 gate electrode ▲ a body region and a source region; preparing a contact trench; etching the gate top dielectric material such that at least a portion of the source region extends above the gate top dielectric material; and at least a portion A source layer is deposited on at least a portion of the source region of the gate trench opening and at least a portion of the contact trench. 12. The method of claim 5, further comprising the steps of: preparing the gate electrode in the gate trench before preparing the gate electrode - such as a patent range of 1 million ' 'luxury' Further, the following steps are included. Between the opaque electrode and the gate electrode, an interelectrode dielectric splicer is prepared. The method described in the patent scope _ _ 10110271#单号Α_第22页/ 43 桎 丨 1012004880-0 201232782 dielectric material, and (4) gold, such that the metal layer covers the gate top dielectric material above the electrode and contacts the source opposite the gate dielectric material The method of claim n, wherein the top surface of the thumb top dielectric material is recessed below the top of the source region. 16 . The method wherein the source region has a substantially vertical surface and at least a portion of the substantially vertical surface is in direct contact with the metal layer. The method of claim n, wherein the thumb-pole groove has an at least partially curved trench sidewall. The method of claim 17, wherein at least a portion of the surface of the source region conforms to a curved portion of the sidewall of the trench. 19. The method of claim 3, wherein the aged layer is in contact with the source region on a plurality of edges. 20 22 If applying for the method described in item 11 of the full-time, in which the source is pure on the opposite side of the contact groove, and on the edge of the __ «media material ^ (4) - the gold The method of claim 2, wherein the method of claim U further comprises the following steps: "product-at least one portion of the conductive plug is in the contact trench. For example, if I apply for the full-scale 11th item, the towel should be at least partially in the groove.曰 Page 23 of 43 1〇Π0271^Α〇101 1012004880-0