TW449837B - Method for manufacturing metal gate transistor - Google Patents

Abstract

There is provided a method for manufacturing metal gate transistor, which includes the following steps: sequentially forming a virtual layer and a mask layer on a semiconductor substrate, and defining the virtual layer and the mask layer to form a virtual gate structure; performing an ion implantation on the semiconductor substrate by lightly doping, and then forming a spacer on the sidewall of the virtual gate structure; next, performing a heavily doping ion implantation on the semiconductor substrate to form a source/drain region; then, forming an insulation layer on the semiconductor substrate and exposing the virtual gate structure; sequentially removing the mask layer and the virtual layer in the virtual gate structure for forming an opening; and sequentially forming a gate oxide layer and a metal conductive layer filled in the opening on the bottom of the virtual gate structure, thereby forming a metal gate transistor.

Description

4 4983? 5. Description of the invention (l) The present invention relates to a method for manufacturing a metal gate transistor (Metal Gate Transistor), and particularly to a method of forming a dummy dummy structure first and then removing the virtual gate. Electrode structure and a method of depositing a metal conductive layer to form a metal gate transistor. Metal-Oxide-Semiconductor Transistor (MOS) is a very important basic electronic component in VLSI technology. It is composed of three basic materials, namely a metal conductor layer, an oxide layer and a semiconductor layer. Gate transistor on a semiconductor substrate. In addition, it also includes two semiconductor regions located on both sides of the gate transistor and electrically opposite to the semiconductor substrate, which are called source and drain. At present, when a gate transistor is made, a metal conductive layer is mostly composed of doped polycrystalline silicon (PolysU icon) and metal. This structure is also called a polycrystalline silicon silicide (Po 1 yc i de). Please refer to FIG. 1 to FIG. 1D, which are cross-sectional views showing a conventional process for manufacturing an n-type polycrystalline spar gate transistor (NM0S). As shown in FIG. 1a, a P-type semiconductor substrate 100 ′ is provided, and then a Shallow Trench Isolation (STI) 104 is formed in the semiconductor substrate 100, and is isolated by the shallow groove isolation 104. Active area i〇2. If an n-type semiconductor substrate is used, 'After completing the above steps, p-type ions, such as boron ions, are implanted in the active region 102 of the semiconductor substrate 100 by ion implantation' to actively A ρ well region is formed locally in the region 102. Then, a gate oxide layer is formed on the semiconductor substrate 100 by thermal oxidation method 106 °, and then a polycrystalline silicon is formed on the gate oxide layer 106 by chemical vapor deposition (CVD) technology.

—------- 5. Description of the invention The ⑵r layer 108 ′ is doped into the polycrystalline silicon layer with a high concentration of phosphorus or arsenic to reduce the resistance of the polycrystalline silicon layer 108. The conductor layer 110 with better capability is formed on the polycrystalline silicon layer 008 by chemical vapor deposition technology, and the conductor layer is mostly made of tungsten silicide (WSix) with better conductivity. Please continue to refer to FIG. Lb, and form a photoresist layer (not shown in the figure) on the conductor layer 11 'to define the gate photoresist pattern through the lithography process, and form the gate 11 by anisotropic dry etching 2 and the polycrystalline silicon conductor 11 3, and then the photoresist pattern is removed. Next, lightly doped ion implantation was performed using gate 112 as a mask and phosphorus as an ion source to form a lightly doped source / drain region (LDDM14) to prevent short channel effects (Short Channel Effect). Then, as shown in FIG. 1c, a dielectric layer is formed on the semiconductor substrate loo by chemical vapor deposition, and the material of the dielectric layer is, for example, SiO 2 or Si 2 Silicon oxynitride (S i ON), and then use the lithography and anisotropic dry etching steps to form a spacer (Spacer) 116 on the side wall of the gate electrode 11 2 and the polycrystalline silicon conductor 1 1 3. Subsequently, the gate electrode 112 is used. The spacer 116 is used as a mask. Phosphorus or a higher solid solubility of silicon (Sol id Solubility) is used as an ion source to 'high-concentrate and deeper ion implantation of the semiconductor substrate 100', that is, doping intensively. (Heavy Doping) is used as the source / drain 114a. Therefore, an n-type complex crystalline silicon gate transistor (NM0S) is formed. Next, please refer to Figure Id to selectively perform the internal metal The connection process is performed by chemical vapor deposition on the semiconductor substrate 100, the gate 112, and the polycrystalline silicon conductor 113. Was deposited interlayer dielectric layer (Inter-Layer Dielectric Layer, ILD) 118. Then, the polycrystalline silicon conductor 113

4 ^ 983γ V. Description of the invention (3) 'a A contact opening 120 is formed by a lithographic etching process. A DC conductor method is used to deposit a metal conductor layer on the interlayer dielectric layer 118 and fill the contact opening 120, and then define a first metal interconnect 122 through a lithography etching process. Although complex-crystal silicon gate transistors have been widely used, with the increase of the semiconductor technology's requirements for accumulation, in the following processes, complex-crystal gate transistors will have a very serious emptying effect (Deplet Ion Effect), leading to a significant decline in the execution performance of the component up to 15%, greatly reducing the yield of the component ', resulting in an increase in production costs. — Furthermore, according to the conventional manufacturing method of complex-crystal silicon gate transistor, an ion implantation step is usually required to adjust the threshold voltage value (Vt) of the channel, or turn it into an anti-ion breakdown region (anti- punchthrough area). In addition, 'the gate oxide layer thickness has been further required to be thinner when manufacturing the gate transistor', which makes the device perform better. However, when using a polycrystalline silicon gate transistor, 'the conductor layer is polycrystalline silicon. Layer, if the gate oxide layer is too thin, when a positive gate voltage (+ Vg) is applied to the gate, the electrons in the source / drain will pass through the gate oxide layer and stay in the polycrystalite layer. Causes source / drain leakage. Therefore, an object of the present invention is to provide a metal layer instead of a polycrystalline silicon layer as a gate conductor 'to form a metal gate transistor. To achieve the above object, the present invention provides a method for manufacturing a metal gate transistor, which includes the following steps: sequentially forming a dummy layer and a mask layer on a semiconductor substrate, and defining the dummy layer and the mask layer to form a virtual gate structure. . Next ’, a lightly doped process is performed on the semiconductor substrate.

Page 6 V. Description of the invention (4) A spacer is formed on the sidewall of the ^ electrode structure and a virtual gate junction is used as a mask. The semiconductor substrate is heavily doped with ion implantation, with the shape of the spacer and the pole region. Then, an insulating layer is formed on the semiconductor substrate and a gate structure is selected. Then, the dummy * and the dummy layer in the virtual gate structure are sequentially removed to form an opening. Subsequently, a dummy oxide layer is formed on the virtual screen by a thermal oxidation method, and then, the dummy layer is formed on the dummy screen; == a gold conductive layer is formed and the opening is filled; Mechanical grinding removes the metal gate transistor formed on the insulation layer. It belongs to a conductor layer, and makes the above and other objects, features, and advantages of the present invention clearer. A preferred embodiment is given below and described in detail with the accompanying drawings as follows: Brief description of the drawings: ^ Figures 18 to W are cross-sectional views showing a process for manufacturing a 1! Type complex thyristor according to the conventional art; Figures 2a to 2f show the proposed method according to the method of the present invention A cross-sectional view of the process of a preferred embodiment; and FIGS. 3a to 3e are cross-sectional views of a process of the first preferred embodiment according to the method of the present invention. 1 Symbol description: 200 '300 202' 302 204 > 304 222 '322 100 102 104 106 semiconductor substrate; active area; shallow groove spacer; gate oxide layer;

4 4983γ _ Five 'description of the invention (5) 1 0 8 and 3 0 8: polycrystalline silicon layer; I 1 0: conductor layer; 112, 212a, 326: gate; II 3: polycrystalline silicon conductor: I 1 4 , 21 4, 31 4: lightly doped source / drain region; 114a, 2 14a, 314a: heavily doped source / drain region; II 6, 21 6, 3 1 2: spacer; 1 18, 21 9, 3 1 8: interlayer dielectric layer; 120, 228: contact opening; 122, 23 0: first metal interconnect; 20 6, 30 6: virtual layer; 20 8, 20 8a: mask layer; 2 1 2, 3 0: virtual gate structure; 2 1 3: metal conductor structure; 2 1 8: first insulating layer; 21 8a: second insulating layer; 2 2 0, 3 2 0: opening; 224, 323 : Barrier layer; and 22 6: metal conductor layer. Example: Example 1 Please refer to FIG. 2a to FIG. 2f, which shows the first preferred embodiment of the method for manufacturing a metal gate transistor according to the present invention. The manufactured gate transistor is of η type An example is a metal gate transistor.

/ 1 ^ 9 83 7 V. Description of the invention (6) ~ First, in Figure 2a, the semiconductor substrate 2000 is a -p-type semiconductor material. Then, a shallow groove spacer 204 is formed in the semiconductor substrate 200, and the active region 202 is isolated by the shallow groove spacer 204. If an n-type semiconductor substrate is used, after the above steps are completed, p-type ions, such as boron ions, are implanted into the active region 202 in the semiconductor substrate 200 by ion implantation to form the active region 2 in the semiconductor substrate 200. The p-well area is locally formed in 〇2. Then, a dummy layer 206 is formed on the semiconductor substrate 200. For example, oxygen is reacted with silicon in the semiconductor substrate 2000 by a thermal oxidation method to form silicon dioxide. Next, a mask layer 208 is formed on the dummy layer 206. The material of the mask layer 208 is, for example, silicon nitride, and the method of forming the mask layer 208 is, for example, chemical vapor deposition. Then through the lithography process, the gate pattern is defined, and the mask layer 208 and the dummy layer 206 are etched to form a dummy gate structure 212 on the active area 202 and a shallow groove spacer 2. A cover layer structure 20 8a is formed on 4. Next, the dummy gate structure 212 is used as a mask, and phosphorus is used as the ion source to perform lightly doped ion implantation to form a lightly doped source / drain region 2 1 4 ′ for preventing short channel effects. For details, please refer to FIG. 2b. Spacers 216 are formed on the side walls of the dummy gate structure 212 and the mask layer structure 208a. Dry dielectric etching is used to etch this dielectric layer to form spacers 2 1 6 on the side walls of the dummy gate structure 2 丨 2 and the cover layer structure 2 0 8 a. The material of the spacers 2 1 6 is, for example, silicon dioxide. Or silicon oxynitride, which functions as an isolation virtual gate structure 2 丨 2 from other gates. Subsequently, using the spacer 216 and the virtual gate structure 212 as a cover and a curtain, and using phosphorus or arsenic as an ion source, the semiconductor substrate is subjected to high concentration and depth.

Page 9. _____ V. Description of the invention (7) Deeper ion implantation, that is, doping heavily, forming source / drain 2 1 4a. Next, a first insulating layer 2 1 8 is formed on the dummy gate structure 212 and the mask layer structure 208 a, for example, by chemical vapor deposition. The first insulating layer 2 1 8 is made of silicon dioxide. The first insulating layer 2 1 8 is planarized to expose the surface of the dummy gate structure 21 2. Continuing to refer to FIG. 2c, the mask layer 208 and the dummy layer 206 located in the virtual gate structure 2 丨 2 and the mask layer structure 208a on the shallow groove spacer 204 are removed. Openings 2 2 0 are formed in the active region 202 and the shallow groove spacers 2 0 4. For example, an anisotropic dry etching method is used. At this time, the p-type semiconductor substrate 200 may be subjected to an ion implantation step 'through the opening 220 to adjust the threshold voltage value of the channel or form a bag-like anti-ion breakdown region. In addition, another preferred method is 'In the above dry money engraving process, it is optional to retain the dummy layer 206 first', and then perform an ion implantation step on the p-type semiconductor substrate 200 through the opening 220, and then perform the wet etching method. Remove. Continued 'Please refer to FIG. 2D, a gate emulsified layer 222 is formed at the bottom of the opening 220 in the active region 202. For example, the silicon oxide in the semiconductor substrate 200 is reacted with oxygen by a thermal oxidation method to form a thin gate oxide layer. 222. Continue, please refer to Figure 2e. In order to make the subsequent deposited metals, such as tungsten and silicon have better adhesion, or to avoid aluminum and silicon spikes (Spike) 'can be on the side wall and gate oxide layer A barrier layer 224 is formed on 222, for example, deposited by a DC sputtering method, and the material of the barrier layer 224 is, for example, a titanium nitride (Ti tani um Ni tride, T iN) or a nitride town ( Tungsten Nitride, TiW). Next, a metal conductor layer 226 is deposited on the first insulating layer 218, and the opening 22 is filled. The metal conductor 449837 V. Description of the invention (8) The material of the body layer 226 is, for example, tungsten metal. The metal conductor layer on the layer 218 is removed, so a metal gate electrode 212a is formed on the active area μ ?, and a metal conductor structure 21 3 is formed on the shallow groove spacer 204. The removal method is, for example, by returning a surname (gtch Back) or chemical mechanical polishing. Please continue to refer to Figure 2f for the metal interconnection process. A second insulating layer 2 1 8 a is deposited on the first insulating layer 2 1 8. The second insulating layer 2 1 8 a can be formed by a chemical vapor deposition method. The first insulating layer 2 1 8 and the second insulating layer 218 a Composite interlayer dielectric wide 219. Then, by the lithography process, a contact opening 228 ′ is formed in the second insulating layer 2 1 8 a with respect to the metal conductor structure 21 3 and exposed on the surface of the metal conductor layer 226 on the top of the metal conductor structure 213, and then A metal layer is deposited on the second insulating layer 218a and fills the contact opening 228 ', which is defined as the first metal interconnect 230 by lithography. Embodiment 2 Please refer to FIG. 3a to FIG. 3e, which shows a second preferred embodiment of the method for manufacturing a metal gate transistor, which is applied to the formation of a selective metal tungsten (Selective Tungsten). The gate transistor manufactured in the metal gate transistor manufacturing process is an n-type metal gate transistor as an example. First, referring to FIG. 3a, the semiconductor substrate 300 is made of a p-type semiconductor material. A shallow groove spacer 304 is then formed in the semiconductor substrate 300, and the active region 302 is isolated by the shallow groove spacer 304. If an n-type semiconductor substrate is used at the beginning, when the above steps are completed, P-type ions, such as boron ions, are implanted in the active region 302 by ion implantation to locally form a p-well region in the active region 302. Then, by thermal oxidation,

9 8 3 7,-. · _____ .- 5. Description of the invention (9) A dummy layer 306 is formed on the bulk substrate 300, and a polycrystalline silicon layer 3 is deposited on the dummy layer 3 0 6 by chemical vapor deposition method 3 0 8. Then, through a lithography process, a gate pattern is defined, and the polycrystalline silicon layer 308 and the dummy layer 306 are etched to form a dummy gate structure 3 1 0 on the active region 302. Next, using the dummy gate structure 3 10 as a mask and phosphorus as the ion source, lightly doped ion implantation of the semiconductor substrate 300 was performed to form a lightly doped source / drain 3 4 as a prevention Short channel response. Next, referring to FIG. 3b, a spacer 312 is formed on the side wall of the virtual gate structure 31. The method of forming the spacer 312 is, for example, first forming a dielectric layer on the semiconductor substrate 300 and then performing anisotropic dry etching. The dielectric layer is etched to leave a spacer 31 2 on the side wall of the dummy structure. The material of the spacer 31 2 is, for example, silicon nitride. Next, using the dummy gate 3 10 and the spacer 31 2 as a mask, a thick doping step is performed on the active region 'to form a source / drain region 3i4a. Subsequently, as shown in FIG. 3c, a metal silicide layer 316 is formed on the surface of the source / drain region 314a and the top of the virtual gate structure 310. For example, the formation of a self-aligned metal tungsten silicide layer 316 can be achieved by chemical vapor The deposition method deposits metal tungsten on the semiconductor substrate 300, and is achieved by the reaction of the metal tungsten with silicon in the semiconductor substrate 300, and the silicon in the polycrystalline silicon layer 300 on top of the virtual gate structure 3o. . Next, an interlayer dielectric layer 318 is formed on the semiconductor substrate 300, and a metal tungsten silicide layer 3 is exposed on the virtual gate structure 3 10. The material of the interlayer dielectric layer 3 ″ 8 is, for example, silicon dioxide, and the formation method thereof is, for example, chemical gas phase " u product '

Page 12 V. Description of the Invention (ίο)

The selective metal layer 3 丨 6 on the virtual gate structure 310 is used as a stop layer. Then, referring to FIG. 3D, the metal tungsten silicide layer 316 on the virtual gate structure 3 丨, the polycrystalline silicon layer 308 and the virtual layer 306 in the virtual gate structure 31 are sequentially removed to sequentially An opening 3 2 0 is formed in the spacer 3 丨 2, and the erasing method uses an anisotropic dry etching method. At this time, an ion implantation step can be performed on the pH semiconductor substrate 300 through the opening 3 2 0 to adjust the threshold voltage value of the channel or form a pouch-like anti-ion breakdown region. Next, as shown in FIG. 3e, the semiconductor substrate 300 at the bottom of the opening 32 is oxidized to form a thin gate oxide layer 3 2 2. For example, silicon in the semiconductor substrate 3 0 is reacted with oxygen by a thermal oxidation method. A thin gate oxide layer is formed. Then, in order to make the subsequent deposited metals, such as the town and the city, have better adhesion ability, or to avoid the peak phenomenon of aluminum and stone, a good barrier is formed on the opening 3 2 0 side wall and the gate oxide layer 322. The barrier layer 323 with adhesion ability is deposited by, for example, a DC sputtering method. The material of the barrier layer 323 is, for example, titanium nitride or tungsten nitride. Next, a metal conductor layer 324 is formed on the interlayer dielectric layer 318 and fills the opening 320. Subsequently, the metal conductor layer on the interlayer dielectric layer 318 is removed, so a metal gate 326 is formed on the active region 302, for example, by etch back or chemical mechanical polishing. The metal gate transistor manufactured by the method for manufacturing the metal gate transistor provided by the present invention has the following advantages: (1). The method for manufacturing the metal gate transistor provided by the present invention will be more traditional The manufacturing process is convenient because the surface of the semiconductor substrate located at the bottom of the virtual gate structure can be directly exposed after the dummy layer is removed.

449837 V. Description of the invention (11) Use the ion implantation method to perform an ion implantation step on the semiconductor substrate through the opening to adjust the threshold voltage value of the channel or form a bag-like anti-ion breakdown area. (2). Since the present invention uses a metal conductor layer instead of the polycrystalline silicon layer, as the conductor layer of the gate transistor, so the empty effect phenomenon of the polycrystalline silicon gate transistor does not occur, so the transistor The performance is also better than that of complex crystal idler transistor. (3). Since the present invention uses a metal conductor layer instead of the polycrystalline silicon layer, the gate oxide layer formed is also thinner than the gate oxide layer used for the polycrystalline silicon gate transistor. When the conductor is used as the conductor layer, the gate oxide layer becomes heavier. When a voltage is applied to the gate electrode, the gate oxide layer can penetrate through the gate oxide layer more easily, so that the transistor can perform better. To the metal conductor layer, the electrons will not stay in the metal conductor layer, and there is a problem of leakage current β (4). In the metal gate transistor made by the present invention, when the metal conductor layer is made of crane 'Has a fairly low resistivity (~ 1 ohm / sq)' so it can be used as a good metal interconnect conductor. (5) Using the metal gate transistor manufactured by the present invention can greatly reduce the area of word lines / bit lines over a long distance in a memory circuit. (6). In the process of preparing the metal gate transistor of the present invention, the thermal process used does not have a large amount of thermal budget, even when using Rapid Thermal Annealing (RTA). m 〇 In summary, the metal gate transistor proposed by the present invention has a comparative

Page 14-4,4 9-8-3 ^ ~ __ V. Description of the invention (12) '' Known that the multi-crystal silicon gate transistor made has more good performance and advantages, which can effectively improve the performance of the transistor With yield. The material materials used in the present invention are not limited to those cited in the examples, and can be replaced by various materials and forming methods having appropriate characteristics. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

Page 15

Claims (1)

449837 6. Application Patent Scope 1. A method for manufacturing a metal gate transistor, which is suitable for manufacturing a metal gate transistor on a semiconductor substrate. The method for manufacturing the metal gate transistor includes the following steps: forming a virtual gate on the semiconductor substrate Electrode to define the metal gate range of the transistor; forming a source / drain region in the semiconductor substrate on both sides of the virtual gate; forming an insulating layer on the semiconductor substrate and exposing the virtual gate; removing The dummy gate to form an opening; and the metal gate of the metal gate transistor to be formed in the opening. 2. The manufacturing method described in item 1 of the scope of patent application, wherein the material of the insulating layer is silicon dioxide. 3. The manufacturing method as described in item 1 of the scope of patent application, wherein the material of the closed metal is crane. 4. The manufacturing method according to item 1 of the scope of patent application, wherein the step of removing the virtual gate includes removing the mask layer and the virtual layer in the virtual gate. 5. The manufacturing method according to item 3 of the scope of patent application, wherein removing the mask layer and the dummy layer is performed by a wet etching method. 6. The manufacturing method according to item 1 of the scope of patent application, wherein after removing the virtual gate, it further includes ion implantation in the semiconductor substrate at the bottom of the opening. The manufacturing method described above, wherein the ion implantation method implants ions having the same electrical properties as the semiconductor substrate. 8. The manufacturing method described in item 1 of the scope of patent application, wherein Page 16 4983 * 7 6. The scope of patent application The virtual gate further includes the following steps: = forming a virtual layer and a mask layer in sequence on the semiconductor substrate; defining the mask layer and the virtual layer in order to A dummy gate is formed on the semiconductor substrate; and a spacer is formed around the dummy gate. The manufacturing method described in item 8 of the scope of patent application, wherein the virtual material is silicon dioxide. 10. The manufacturing method as described in item 8 of the scope of patent application, wherein the material of the curtain layer is one of silicon nitride and polycrystalline silicon. Separator 1 丄: ”Please” The manufacturing method described in item 8 of the scope, wherein the material of the space is one of oxidized monoxide and oxynitride. 12. As described in item 丨 of the patent application park In the manufacturing method, the semiconductor substrate around the virtual gate electrode forms a source / drain region step 'DX step' and further includes the following steps: before the spacer is formed, the virtual gate electrode is used to cover the conductor, The substrate is lightly doped; and after the spacer is formed, the semiconductor substrate is heavily doped with the dummy gate and the spacer curtain. 13. As described in item 2 of the scope of the patent application The manufacturing method, wherein the lightly doped and strongly doped processes implant the ions with the same electrical properties and are opposite to the electrical properties of the semi-substrate. Conductor 14. The manufacturing method described in item 1 of the declared patent scope, wherein After forming a source / drain region in the semiconductor substrate around the virtual gate, the & step is selectively formed on the source / drain region and the virtual gate structure. Page 丨 7 6. Scope of Patent Application " Selective metal layer. 15. The manufacturing method according to item 14 of the scope of patent application, wherein the material of the metal layer is a metal crane. 16. The manufacturing method according to item 14 of the application, wherein the selective metal layer is formed by selective chemical vapor deposition. 1 7. The manufacturing method according to item 1 of the scope of patent application, wherein the step of forming the metal gate of the metal gate transistor in the opening further includes the following steps: forming a gate oxide layer at the bottom of the opening; Forming a metal layer on the insulating layer and filling the opening; and removing the metal layer on the insulating layer to form the metal gate. 18. The manufacturing method according to item 17 of the scope of patent application, further comprising forming a barrier layer in the opening before forming the metal layer. 19. The manufacturing method according to item 17 of the scope of the patent application, wherein the material of the barrier layer is one of titanium nitride and tungsten nitride. 20. —A method for manufacturing a metal gate transistor, which is applied to a semiconductor substrate for manufacturing a metal gate transistor. The method for manufacturing the metal gate transistor includes the following steps: A shallow groove isolation region and an active region are defined in the semiconductor substrate. Area; sequentially forming a dummy layer and a mask layer on the semiconductor substrate; defining the dummy layer and the mask layer to form a virtual gate structure; performing ion implantation on the semiconductor substrate by a light doping process; A spacer is formed on the side wall of the gate structure; the virtual gate structure and the spacer are used as a screen to enter the active area; Page 18, 449837_ VI. Patent application: Doped ion implantation is performed to form a source / drain region in the semiconductor substrate around the virtual gate junction trench; an insulating layer is formed to cover the surface of the semiconductor substrate, and Exposing the virtual gate structure; sequentially removing the mask layer and the virtual layer located in the virtual gate structure to form an opening in the virtual interpolar structure; forming a gate oxide at the bottom of the virtual gate structure Layer, and subsequently forming a metal conductive layer in the virtual gate structure and filling the opening; and performing chemical mechanical polishing on the metal conductive layer to remove the metal conductive layer located on the insulating layer to form a metal gate Transistor. 21. The manufacturing method according to item 20 of the scope of patent application, wherein the electrical properties of the lightly-doped and heavily-doped implants are the same, but opposite to the electrical properties of the semiconductor substrate. 22. The manufacturing method as described in item 20 of the scope of the patent application, wherein the material of the cover layer is nitride stone. 23. The manufacturing method as described in item 20 of the scope of patent application, wherein the material of the spacer is one of silicon dioxide and silicon oxynitride. 24. The manufacturing method as described in item 20 of the scope of patent application, wherein the material of the insulating layer is silicon dioxide. 25. The manufacturing method as described in claim 20, wherein the mask layer and the dummy layer are removed by wet etching. 26. The manufacturing method as described in item 20 of the scope of patent application, wherein the material of the metal conductive layer is tungsten. 27. The manufacturing method described in item 20 of the scope of patent application, wherein Page 19 449837 ----- __ VI. Scope of patent application After removing the mask layer and the dummy layer, it further includes ion implantation into the semiconductor substrate at the bottom of the opening. 28. The manufacturing method as described in item 27 of the scope of application for a patent, wherein the electrical properties implanted by the ion implantation method are the same as the electrical properties of the semiconductor substrate. 2 9. The manufacturing method as described in item 20 of the patent application scope, wherein before depositing the metal conductive layer, it further comprises selectively depositing a barrier layer. 30. The manufacturing method as described in item 29 of the scope of patent application, wherein the material of the barrier layer is one of titanium nitride and tungsten nitride. 31. A method for manufacturing a metal gate transistor, which is suitable for manufacturing a metal gate transistor on a semiconductor substrate. The method for manufacturing a metal gate transistor includes the following steps: defining a shallow groove isolation region and an active region in the semiconductor substrate; Region; = a dummy layer and a polycrystalline silicon layer are sequentially formed on the semiconductor substrate; meaning the dummy layer and the polycrystalline silicon layer to form a virtual gate structure; lightly doped ion implantation on the semiconductor substrate; Spacers are formed on the side wall of the virtual gate structure; ~ The active gate area is implanted with heavily doped ions by using the virtual gate structure and the spacer as a mask, so as to surround the virtual gate structure. Forming a source / drain region in a semiconductor substrate; aligning a metal silicide layer on the source / drain region and the virtual gate structure; forming an insulating gate structure; covering the surface of the semiconductor substrate and exposing The virtual sequential removal of the selective metal layer in the virtual gate structure Page 20 ^ 9837 6. Application scope The compound crystal layer and the dummy layer form an opening; a gate oxide layer is formed at the bottom of the dummy gate structure, and two metal layers are formed in the dummy gate structure, and Fill the opening; perform chemical mechanical polishing on the second metal layer to remove the metal conductive layer on the bit layer to form a metal gate transistor. 32. The manufacturing method described in item 31 of the scope of patent application The electrical properties of the lightly doped and heavily doped implants are the same, but the electrical properties are opposite to those of the base. 33. The manufacturing method described in item 31 of the scope of patent application The material of the self-aligned metal silicide layer is tungsten silicide. 34. The manufacturing method described in item 31 of the scope of patent application, the selective metal layer is formed by selective chemical vapor deposition 35. The manufacturing method described in item 31 of the scope of patent application, the material of the spacer is two Either silicon oxide or silicon oxynitride 36. The manufacturing method described in item 31 of the scope of patent application, the material of the insulating layer is silicon dioxide. 37. The manufacturing method described in item 31 of the patent application park. The material of the second metal layer is either tungsten or aluminum. 38. The manufacturing method as described in item 31 of the scope of patent application. The material with wide barriers is one of titanium nitride and tungsten nitride. 39. The manufacturing method described in item 31 of the scope of patent application. After removing the military curtain layer and the dummy layer, it further includes implanting the semiconductor substrate at the bottom with ions. 40 · The manufacturing method described in item 38 of the scope of application for a patent shall be formed after page 21 and in the insulation 'where the semiconductor base is in which the shape is performed β where the * 〇 where the one in which the one is in the opening 〇 'Which the ι9837 Page 22