CN115662952B - Groove type super junction field effect transistor and preparation method thereof - Google Patents
Groove type super junction field effect transistor and preparation method thereof Download PDFInfo
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Abstract
The invention provides a trench type super junction field effect transistor and a preparation method thereof. The preparation process comprises the following steps: providing a substrate of a first conductive type, and forming a first groove; adopting doping gas and etching gas to deposit the epitaxial part of the first stage in the first groove, then carrying out epitaxial process under the condition of stopping supplying the doping gas and the etching gas, utilizing the high-temperature environment of the epitaxial process to make impurities in the epitaxial part deposited at the first stage diffuse to the upper part of the first groove to form the epitaxial part of the second stage with gradually changed concentration, and sealing the top of the first groove, thereby completing the filling of the first groove and forming a second conductive type column; forming a well region, a trench gate and an active region of a second conductivity type; forming an interlayer dielectric layer covering the second conductive type column, the trench gate and the active region; and electrically leading out the second conductive type column, the groove gate and the active region. The invention is helpful to reduce the process time, reduce the production cost and improve the device performance.
Description
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a trench type super junction field effect transistor and a preparation method thereof.
Background
As an advanced power MOSFET device technology, a Trench type Super Junction field effect transistor (Super Junction MOSFET) is used, a space charge region is formed by introducing a vertical P column (P Pillar) and N type epitaxy depletion, and the N type epitaxy and the P column charge balance enable the depletion region to be expanded when a reverse voltage is applied, so that the effect of improving the breakdown voltage is achieved, and therefore the on-resistance during the period can be reduced and the use efficiency of a system can be improved by adjusting the concentration of the N type epitaxy under the condition of ensuring the breakdown voltage.
The P column of the existing trench type super junction field effect transistor is formed by refilling P type epitaxy after etching N type epitaxy by a deep trench. Because the deep trench can reach 40-60um, the width of the trench is only a few microns, and the common epitaxial filling cannot meet the aspect ratio, the whole process of the conventional deep trench epitaxial filling adopts a mode of etching while filling, so that the epitaxy grows upwards from the bottom of the trench. Although the mode has a good filling effect, the single chip processing time is as long as 30-60 minutes, and a cavity is easily generated at the top sealing of the deep trench by epitaxy, so that the electrical performance of the device is reduced.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a trench type super junction field effect transistor and a method for manufacturing the same, which are used to solve the problems that in the prior art, the entire process of epitaxial filling of a deep trench is performed by performing edge etching and edge filling, so that the epitaxy grows upwards from the bottom of the trench, the process time is long, and a cavity is easily generated in the epitaxy at the top seal of the deep trench, which leads to performance degradation of a device.
In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing a trench type super junction field effect transistor, comprising the steps of:
providing a substrate of a first conductive type, and forming a first groove in the substrate;
depositing the epitaxial part of the first stage in the first groove by using doping gas and etching gas, then performing an epitaxial process under the condition of stopping supplying the doping gas and the etching gas, diffusing impurities in the epitaxial part deposited at the first stage to the upper part of the first groove by using a high-temperature environment of the epitaxial process to form the epitaxial part of the second stage with gradually changed concentration, and sealing the top of the first groove, thereby completing the filling of the first groove to form a second conductive type column, wherein the first conductive type is N-type and the second conductive type is P-type, or the first conductive type is P-type and the second conductive type is N-type;
forming a well region of the second conductive type, a trench gate penetrating through the well region and extending downwards into the substrate and an active region of the first conductive type adjacent to the well region in the substrate at the periphery of the first trench;
forming an interlayer dielectric layer covering the second conductive type column, the trench gate and the active region;
and electrically leading out the second conductive type column, the groove gate and the active region.
Optionally, the step of forming the first trench in the substrate includes:
forming a first hard mask layer of an ONO structure on a substrate;
defining a first groove area by using the first hard mask layer, and forming a first groove by etching;
and removing the residual first hard mask layer.
Optionally, the step of forming the trench gate includes:
forming a second hard mask layer covering the well region and the second conductive type column;
defining a second groove area by using the second hard mask layer, and forming a second groove by etching;
forming a gate oxide layer on the inner surface of the second trench;
filling a polycrystalline silicon layer on the inner side of the gate oxide layer, wherein the gate oxide layer and the polycrystalline silicon layer form a trench gate;
and carrying out surface planarization treatment to expose the upper surface of the trench gate.
Optionally, the interlayer dielectric layer includes a silicon dioxide layer and a borophosphosilicate glass layer, and the thickness of the silicon dioxide layer is 2000-2500 angstroms.
Optionally, the borophosphosilicate glass layer has a thickness of 8000-9000 angstroms.
Optionally, electrically leading out the second conductive type pillar, the trench gate, and the active region includes:
forming a plurality of contact holes in the interlayer dielectric layer, wherein the contact holes expose the trench gate and the second conductive type column;
forming an adhesion layer and an interconnection metal layer on the surface of the contact hole exposing the trench gate in sequence;
forming a front metal layer covering the second conductive type column and the contact hole;
and forming a passivation layer on the front metal layer and forming a pad window penetrating through the passivation layer.
Optionally, the adhesion layer comprises a titanium layer and/or a titanium nitride layer, and the interconnect metal layer comprises a tungsten layer or a copper layer; the passivation layer includes a silicon nitride layer and the front side metal layer includes an aluminum copper alloy layer.
Optionally, the preparation method further includes the step of sequentially performing thinning and gold-back processes on the surface of the substrate away from the second conductive type column.
Optionally, the thickness of the epitaxial portion formed in the first stage is 25% -40% of the depth of the first trench.
Optionally, the flow rate of the doping gas introduced in the first stage is 700-1000sccm, the flow rate of the etching gas is 1200-1400sccm, and the deposition time is 1 μm/deposition rate.
Optionally, the trench type super junction field effect transistor is prepared by the preparation method of any of the above schemes.
As described above, the trench type super junction field effect transistor and the manufacturing method thereof of the present invention have the following beneficial effects: the method combines the characteristics of the groove epitaxial growth and the super junction device, the epitaxial growth is divided into two sections, the charge balance of the epitaxial part formed in the first stage and the second conductive type column is realized, and the sealing is completed by the intrinsic epitaxy in the second stage. Therefore, by adopting the preparation method provided by the application, the process time of epitaxial filling can be greatly reduced, the production cost is reduced, the defect of a cavity at the top of the epitaxial layer can be avoided, the conductive type column with better appearance and quality can be formed, and the performance of the device can be improved.
Drawings
Fig. 1 shows a flowchart of a method for manufacturing a trench-type super junction field effect transistor provided by the invention.
Fig. 2 illustrates an exemplary structure for forming a first hard mask layer on a substrate.
Fig. 3 is a schematic diagram illustrating an exemplary structure of forming a first trench.
Fig. 4 is a schematic diagram illustrating an exemplary structure for forming second conductive type pillars.
Fig. 5 shows an exemplary structure for forming a well region.
Fig. 6 is a schematic diagram illustrating an exemplary structure for forming a second hard mask layer.
Fig. 7 is a schematic diagram illustrating an exemplary structure of forming the second trench.
Fig. 8 is a schematic diagram of an exemplary structure for forming an active region.
Fig. 9 is a schematic diagram of an exemplary structure for forming an interlayer dielectric layer.
Fig. 10 is a schematic diagram of an exemplary structure for forming a contact hole.
FIG. 11 is a schematic diagram illustrating the formation of an interconnect metal layer in a contact hole.
Fig. 12 is a schematic diagram of an exemplary structure for forming a front metal layer.
Fig. 13 is a schematic diagram of an exemplary structure after etching the front metal layer.
Fig. 14 is a schematic diagram of an exemplary structure for forming a passivation layer and a pad window.
Fig. 15 is a schematic diagram of an exemplary structure after backside thinning of a substrate.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.
In the prior art, the whole process of filling the P column of the trench-type super junction field effect transistor is in a side etching and side filling mode, so that epitaxy grows upwards from the bottom of the trench to complete filling. When the method is used for filling a trench with a high aspect ratio, the single chip processing time is as long as 30-60 minutes, and a cavity is easily generated at the top sealing of the deep trench by epitaxy, so that the performance of a device is reduced. In view of the above, the inventors of the present application have made a long-term study and have proposed an improvement.
Specifically, as shown in fig. 1, the present invention provides a method for manufacturing a trench type super junction field effect transistor, and the process thereof will be described in detail with reference to fig. 2 to 15.
First, step S1 is performed to provide a substrate 11 of a first conductivity type, and a first trench 12 is formed in the substrate 11.
The substrate 11 may be a full-epitaxial material, or as shown in this embodiment, includes a substrate 111 made of a semiconductor material such as silicon, silicon germanium, and the like, and an epitaxial layer 112 of the first conductivity type located on the surface of the substrate 111, and a buffer layer (not shown) may be further formed between the substrate 111 and the epitaxial layer 112, where the buffer layer has the same doping type as the epitaxial layer 112, but the doping concentration is less than that of the epitaxial layer 112. The buffer layer may prevent impurities in the epitaxial layer 112 from diffusing into the substrate 111 in a high temperature process. Before the subsequent processes are performed, the substrate 11 may be cleaned, for example, by sequentially cleaning the substrate with an organic solvent such as acetone and deionized water to remove contaminants on the surface of the substrate 11, and then drying the substrate, or by first removing a natural oxide layer on the surface of the substrate 11 with a diluted acid solution, then cleaning the substrate with deionized water, and finally drying the substrate, or by performing multiple cleaning with the foregoing cleaning methods.
In a preferred example, the step of forming the first trench 12 in the substrate 11 includes:
a mask layer is formed on the substrate 11 and the resulting structure is shown in fig. 2. The mask layer is preferably a hard mask to help improve the etching accuracy, and in the present embodiment, a hard mask layer of an ONO structure is preferably used, which is defined herein as the first hard mask layer 18, i.e., the mask layer includes, from bottom to top, a silicon dioxide layer 181, a silicon nitride layer 182 and a silicon dioxide layer 181, and the thickness of the silicon dioxide layer 183 on the top layer is generally greater than that of the silicon dioxide layer on the bottom layer. The hard mask layer may be formed sequentially by a chemical vapor deposition process, or may be formed by a thermal oxidation process to form the bottom silicon dioxide layer 181, and the silicon nitride layer 182 and the top silicon dioxide layer 183 are formed by a chemical vapor deposition process. With the mask layer of this structure, the silicon dioxide layer 181 at the bottom serves as a buffer layer to buffer the stress between the silicon nitride layer 182 and the substrate 11, and the silicon nitride layer 182 serves as an etching stop layer for the upper silicon dioxide layer 183, and after the trenches are defined in the mask layer, the upper silicon dioxide layer 183 will be consumed as a hard mask when the trenches in the substrate 11 are etched. Therefore, the hard mask layer with the ONO structure is beneficial to improving the etching precision and protecting the substrate 11.
After forming the hard mask layer, a first trench 12 region is defined by using the first hard mask layer 18, the first trench 12 is formed by etching, and the resulting structure is as shown in fig. 3, and then the remaining first hard mask layer 18 is removed by using an etching process including but not limited to etching. The depth of the first trench 12 is typically less than the thickness of the epitaxial layer 112, so that the subsequently formed second conductivity type pillar 13 has a bottom spaced from the substrate 111.
Next, step S2 is performed, a first-stage epitaxial portion is deposited in the first trench 12 by using a dopant gas and an etching gas, then an epitaxial process is performed under the condition that the supply of the dopant gas and the etching gas is stopped, impurities in the first-stage deposited epitaxial portion are diffused toward the upper portion of the first trench 12 by using a high-temperature environment of the epitaxial process to form a second-stage epitaxial portion with a gradually changing concentration, and the top of the first trench 12 is sealed, thereby completing the filling of the first trench 12 to form the second conductive type column 13, where the first conductive type is N-type and the second conductive type is P-type, or the first conductive type is P-type and the second conductive type is N-type, for example, the epitaxial layer 112 is an N-type layer, so that a P-type column is formed. And the P-type columns are typically multiple and spaced apart in epitaxial layer 112, thereby forming a super junction structure. That is, in this step, the conventional epitaxy method is firstly used to fill an epitaxy portion with a certain thickness in the first trench 12 to cover the bottom and the sidewalls of the first trench 12, that is, the epitaxy portion deposited in the first stage does not completely fill the first trench 12, and in the second stage, no dopant gas and etching gas is introduced but only an epitaxy reaction gas is introduced and the high temperature condition of the epitaxy process is maintained (the difference between the second stage and the first stage is that the first stage, in addition to the epitaxy reaction gas, also introduces an etching gas and a dopant gas, while the second stage introduces an epitaxy reaction gas but not introduces an etching gas and a dopant gas, and the other process conditions of the two stages, such as the flow rate, the temperature, and the degree of vacuum, are the same), the high temperature environment of the epitaxy process, such as 800 ℃ to 1200 ℃, specifically such as 800, 900, 1000, 1100, 1200, or any value in this interval, allows the impurities in the epitaxy portion formed in the first stage to diffuse into the epitaxy portion grown in the second stage according with the fick law, and the intrinsic epitaxy growth speed is naturally formed due to the partial epitaxy growth speed at the top opening angle of the trench, thereby forming the graded epitaxial portion with the concentration of the second stage, and the epitaxy portion formed in the second stage. In this step, the thickness control in the first stage is very critical, and if the thickness is too small, it may cause difficulty in the second stage to realize top sealing, and if the thickness is too large, not only the trench filling time is too long, but also it is difficult to form a graded concentration. The inventors have found through extensive experiments that the thickness of the epitaxial portion formed in the first stage is preferably 25% -40% of the depth of the first trench 12. Taking the depth of the first trench 12 as 4 μm as an example, the thickness of the epitaxial portion formed in the first stage is preferably 1-1.6 μm. The epitaxial process of the first stage can also be controlled by controlling the supply time, or off time, of the dopant gas and the etching gas of the first stage, for example, the deposition time of the first stage is 1 μm divided by the deposition rate of the machine epitaxy. The time for the first phase is approximately 600 seconds and the time for the second phase is approximately 300 seconds, as calculated by conventional epitaxy equipment. The dopant gas flow rate for the first stage epitaxy is determined by the desired epitaxy concentration.
Preferably, in the present embodiment, the flow rate of the doping gas is 700-1000sccm, more preferably 800sccm, the flow rate of the etching gas is 1200-1400sccm, more preferably 1300sccm, and the flow rate of the doping gas in the second stage is zero. The aspect ratio of the first trench 12 is preferably greater than 5, and the larger the aspect ratio, the more time can be saved by filling with the method of the present application, so that the advantages are more prominent. The epitaxial reaction gas may be selected as desired, for example, silicon epitaxial, the epitaxial gas may be silane, germanium epitaxial, if germanium epitaxial, the doping gas may be, for example, an N-containing gas, an Al-containing gas, or a B-containing gas when depositing an N-type epitaxial layer, and the etching gas may be, for example, hydrogen chloride gas. In addition, in the conventional epitaxial growth, in order to fill up the whole trench, the flow of the etching gas is increased at the second stage, for example, to 1800sccm, which results in that the overall epitaxial growth rate is reduced very low, the sidewall hardly grows, the epitaxy only grows from the bottom upwards, and the trench filling needs more than 30 minutes, so that the conventional epitaxial growth technology is generally used for planar epitaxial growth and directly and rapidly seals the trench, the upper and lower widths of the formed conductive type column are different, and the super junction device characteristics cannot be realized due to the fact that the upper and lower widths of the formed conductive type column are different from those of the N-type epitaxial layer 112.
In contrast, the present application combines the characteristics of trench epitaxial growth and super junction device characteristics, and divides the epitaxial growth into two stages, the epitaxial portion (for example, about 1 μm thick) formed in the first stage and the second conductive type column 13 achieve charge balance, and the intrinsic epitaxy in the second stage completes the sealing. Therefore, by adopting the preparation method provided by the application, the process time of epitaxial filling can be greatly reduced, the production cost is reduced, the defect of a cavity at the top of the epitaxial layer can be avoided, the conductive type column with better appearance and quality can be formed, and the performance of the device can be improved.
After the filling of the first trench 12 is completed, surface planarization, including but not limited to chemical mechanical polishing, may be performed to remove an epitaxial portion of the surface of the substrate 11 at the periphery of the first trench 12 to expose the substrate 11, so that the upper surface of the second conductive type pillar 13 is flush with the surrounding upper surface of the substrate 11, and the resulting structure is shown in fig. 4. An ion implantation process may then be performed and high temperature drive-in may be performed to form a well region 14 of the second conductivity type in the substrate 11 at the periphery of the first trench 12, and the resulting structure is shown in fig. 5.
Step S3 is next performed to form trench gates 15 extending through the well region 14 and down into the substrate 11 and active regions 16 of the first conductivity type adjacent to the well region 14.
In one example, the step of forming the trench gate 15 includes:
forming a mask layer covering the well region 14 and the second conductive type pillars 13, and in this example preferably a hard mask layer, here defined as a second hard mask layer 19, the second hard mask layer 19 preferably having an ONO structure identical to the first hard mask layer 18, and including, from bottom to top, a silicon dioxide layer 191, a silicon nitride layer 192, and a silicon dioxide layer 193, the resulting structure being as shown in fig. 6;
defining a second trench 20 region by using the second hard mask layer 19, and forming a second trench 20 in the substrate 11 at the periphery of the first trench 12 by etching, wherein the positions of the first trench 12 and the second trench 20 are staggered from each other in the longitudinal direction, and the depth of the second trench 20 is generally smaller than that of the first trench 12, and the obtained structure is as shown in fig. 7;
forming a gate oxide layer 151 on the inner surface of the second trench 20, i.e. on the sidewall of the trench, by using a thermal oxidation process, including but not limited to, the thickness of the gate oxide layer 151 is, for example, 200 a to 500 a;
then, a gate conductive layer, such as a polysilicon layer 152, is filled inside the gate oxide layer 151 by a chemical vapor deposition process, polysilicon fills the remaining space of the second trench 20, the gate oxide layer 151 and the polysilicon layer 152 in the second trench 20 form a trench gate 15, and then a chemical mechanical polishing process may be performed to remove the excess polysilicon and the polysilicon layer, thereby exposing the upper surface of the trench gate 15.
After forming the trench gate 15, an ion implantation process and a high temperature anneal are performed to form a first conductivity type active region 16 adjacent to the well region 14, for example, above the well region 14, and the resulting structure is shown in fig. 8.
Step S4 is performed next, and an interlayer dielectric layer 17 covering the second conductive type pillars 13, the trench gates 15 and the active regions 16 is formed, and the resulting structure is as shown in fig. 9.
The interlayer dielectric layer 17 may be a single structural layer, or may be a composite structural layer including a silicon dioxide layer 171 and a borophosphosilicate glass layer 172 as shown in this embodiment. The silicon dioxide layer 171 helps to improve the interlayer stress and preferably has a thickness of 2000-2500 angstroms, and the borophosphosilicate glass layer 172 preferably has a thickness of 8000-9000 angstroms.
Then, step S5 is performed to electrically extract the second conductive type pillars 13, the trench gates 15, and the active regions 16. An exemplary process of this step includes:
forming a plurality of contact holes 21 in the interlayer dielectric layer 17 by using an etching process including but not limited to, exposing the trench gate 15 and the second conductive type column 13 through the contact holes 21, and obtaining a structure as shown in fig. 10;
forming an adhesion layer and an interconnection metal layer in sequence on the surface of the contact hole 21 exposing the trench gate 15 by using a physical vapor deposition process, wherein the obtained structure is shown in fig. 11; the adhesion layer can adopt a titanium and/or titanium nitride layer, the interconnection metal layer can adopt a copper layer and/or a copper alloy layer, or the adhesion layer can adopt a tantalum and/or tantalum nitride layer, and the interconnection metal layer can adopt a tungsten layer;
a front metal layer 22 is formed overlying the second conductivity type pillars 13 and the contact holes 21 using a process including, but not limited to, physical vapor deposition, and the resulting structure is shown in fig. 12. The front-side metal layer 22 may be a copper layer and/or an aluminum-copper alloy layer, for example.
In order to realize electrical lead-out, the front metal layer 22 needs to be etched to form an opening penetrating through the front metal layer 22, and the obtained structure is shown in fig. 13;
a passivation layer 23 is formed on the front metal layer 22, and a pad window 24 penetrating the passivation layer 23 is formed. The passivation layer 23 may be a single-layer or multi-layer structure, and for example, may include only a silicon nitride layer, or may include a silicon nitride layer and a polymer layer on the silicon nitride layer, the silicon nitride layer may be formed by using a chemical vapor deposition process, the polymer layer may be formed by using a spin coating process, the passivation layer 23 may be formed to better protect the underlying structure, and then etching is performed to form the pad window 24, and the resulting structure is shown in fig. 14.
After that, the surface of the substrate 11 away from the second conductive type pillar 13 may be thinned in sequence, the resulting structure is shown in fig. 15, and then a back gold process is performed, i.e., a back metal layer (not shown) is formed. The backside metal layer may be, for example, several material layers such as a copper layer, a gold layer, a nickel layer, etc., and an adhesion layer, for example, a titanium layer and/or a titanium nitride layer, may also be formed between the backside metal layer and the substrate 11.
The invention also provides a trench type super junction field effect transistor which is prepared by adopting the preparation method of any scheme, so that the contents can be fully cited, and the details are not repeated for the sake of brevity. The specific structure of the super junction structure can be as shown in fig. 15, and the super junction structure includes a first conductive type substrate, and a plurality of second conductive type columns arranged at intervals in the substrate, for example, the substrate is N-type, so that a plurality of P-type columns are formed at intervals to form the super junction structure. The structure comprises a trench gate positioned in the substrate at the periphery of the second conductive type column, a source region and the like. Due to the adoption of the method for preparing the trench type super junction field effect transistor, the second conductive type column of the trench type super junction field effect transistor has gradient concentration and air gaps, and compared with similar devices prepared by the prior art, the trench type super junction field effect transistor has better appearance and quality, so that the performance of the devices can be further improved, and the production cost can be effectively reduced.
In summary, the present invention provides a trench super junction field effect transistor and a method for manufacturing the same, wherein the method comprises the following steps: providing a substrate of a first conductive type, and forming a first groove in the substrate; depositing the epitaxial part of the first stage in the first groove by using doping gas and etching gas, then performing an epitaxial process under the condition of stopping supplying the doping gas and the etching gas, diffusing impurities in the epitaxial part deposited at the first stage to the upper part of the first groove by using a high-temperature environment of the epitaxial process to form the epitaxial part of the second stage with gradually changed concentration, and sealing the top of the first groove, thereby completing the filling of the first groove to form a second conductive type column, wherein the first conductive type is N-type and the second conductive type is P-type, or the first conductive type is P-type and the second conductive type is N-type; forming a well region of the second conductive type, a trench gate penetrating through the well region and extending downwards into the substrate and an active region of the first conductive type adjacent to the well region in the substrate at the periphery of the first trench; forming an interlayer dielectric layer covering the second conductive type column, the trench gate and the active region; and electrically leading out the second conductive type column, the groove gate and the active region. The invention combines the characteristics of the groove epitaxial growth and the super junction device, divides the epitaxial growth into two sections, realizes charge balance between the epitaxial part formed in the first stage and the second conductive type column, and completes the sealing by the intrinsic epitaxy in the second stage. Therefore, by adopting the preparation method provided by the application, the process time of epitaxial filling can be greatly reduced, the production cost is reduced, the defect of a cavity at the top of the epitaxial layer can be avoided, the conductive type column with better appearance and quality can be formed, and the performance of the device can be improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for preparing a trench type super junction field effect transistor is characterized by comprising the following steps:
providing a substrate of a first conductive type, and forming a first groove in the substrate;
depositing the epitaxial part of the first stage in the first groove by using doping gas and etching gas, then performing an epitaxial process under the condition of stopping supplying the doping gas and the etching gas, diffusing impurities in the epitaxial part deposited at the first stage to the upper part of the first groove by using a high-temperature environment of the epitaxial process to form the epitaxial part of the second stage with gradually changed concentration, and sealing the top of the first groove, thereby completing the filling of the first groove to form a second conductive type column, wherein the first conductive type is N-type and the second conductive type is P-type, or the first conductive type is P-type and the second conductive type is N-type;
forming a well region of the second conductive type, a trench gate penetrating through the well region and extending downwards into the substrate and an active region of the first conductive type adjacent to the well region in the substrate at the periphery of the first trench;
forming an interlayer dielectric layer covering the second conductive type column, the trench gate and the active region;
and electrically leading out the second conductive type column, the groove gate and the active region.
2. The method of claim 1, wherein the step of forming the first trench in the substrate comprises:
forming a first hard mask layer of an ONO structure on a substrate;
defining a first groove area by using the first hard mask layer, and forming a first groove by etching;
and removing the residual first hard mask layer.
3. The method of claim 1, wherein the step of forming the trench gate comprises:
forming a second hard mask layer covering the well region and the second conductive type column;
defining a second groove area by using the second hard mask layer, and forming a second groove by etching;
forming a gate oxide layer on the inner surface of the second trench;
filling a polycrystalline silicon layer on the inner side of the gate oxide layer, wherein the gate oxide layer and the polycrystalline silicon layer form a trench gate;
and carrying out surface planarization treatment to expose the upper surface of the trench gate.
4. The method according to claim 1, wherein the interlayer dielectric layer comprises a silicon dioxide layer and a borophosphosilicate glass layer, the silicon dioxide layer has a thickness of 2000-2500 angstroms, and the borophosphosilicate glass layer has a thickness of 8000-9000 angstroms.
5. The method of claim 1, wherein electrically extracting the second conductivity type pillar, the trench gate, and the active region comprises:
forming a plurality of contact holes in the interlayer dielectric layer, wherein the contact holes expose the trench gate and the second conductive type column;
forming an adhesion layer and an interconnection metal layer on the surface of the contact hole exposing the trench gate in sequence;
forming a front metal layer covering the second conductive type pillar and the contact hole;
and forming a passivation layer on the front metal layer and forming a pad window penetrating through the passivation layer.
6. The method of claim 5, wherein the adhesion layer comprises a titanium layer and/or a titanium nitride layer, and the interconnection metal layer comprises a tungsten layer or a copper layer; the passivation layer includes a silicon nitride layer and the front side metal layer includes an aluminum copper alloy layer.
7. The method of manufacturing according to claim 1, further comprising the step of performing thinning and gold-back processes on the surface of the substrate facing away from the second conductivity type pillar in sequence.
8. The production method according to any one of claims 1 to 7, wherein the thickness of the epitaxial portion formed at the first stage is 25% to 40% of the depth of the first trench.
9. The method according to any one of claims 1 to 7, wherein the doping gas is introduced at a flow rate of 700 to 1000sccm, the etching gas is introduced at a flow rate of 1200 to 1400sccm, and the deposition time is 1 μm per deposition rate in the first stage.
10. A trench type super-junction field effect transistor is prepared by the preparation method of any one of claims 1-9.
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| CN104201099A (en) * | 2014-09-17 | 2014-12-10 | 中航（重庆）微电子有限公司 | Production process of super-junction device |
| CN105590844A (en) * | 2015-12-23 | 2016-05-18 | 西安龙腾新能源科技发展有限公司 | Super junction structure deep groove manufacturing method |
| CN111200008A (en) * | 2018-11-20 | 2020-05-26 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
| CN114068678A (en) * | 2021-11-25 | 2022-02-18 | 华虹半导体(无锡)有限公司 | Super junction trench gate MOSFET device and manufacturing method thereof |
| CN114512406A (en) * | 2022-04-19 | 2022-05-17 | 北京芯可鉴科技有限公司 | Manufacturing method of super junction device |
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| US8390058B2 (en) * | 2009-06-12 | 2013-03-05 | Aplha and Omega Semiconductor Incorporated | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201099A (en) * | 2014-09-17 | 2014-12-10 | 中航（重庆）微电子有限公司 | Production process of super-junction device |
| CN105590844A (en) * | 2015-12-23 | 2016-05-18 | 西安龙腾新能源科技发展有限公司 | Super junction structure deep groove manufacturing method |
| CN111200008A (en) * | 2018-11-20 | 2020-05-26 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
| CN114068678A (en) * | 2021-11-25 | 2022-02-18 | 华虹半导体(无锡)有限公司 | Super junction trench gate MOSFET device and manufacturing method thereof |
| CN114512406A (en) * | 2022-04-19 | 2022-05-17 | 北京芯可鉴科技有限公司 | Manufacturing method of super junction device |
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