JP4528997B2 - Silicon wafer manufacturing method and silicon wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon wafer having a columnar cross-sectional conductivity type region used for a power MOS and the like, and a method for manufacturing the silicon wafer.
[0002]
[Prior art]
Conventionally, as shown in FIG. 5, columnar n-type regions 20a and columnar p-type regions 20b are alternately arranged as a vertical MOSFET capable of increasing current capacity by reducing on-resistance while having a high breakdown voltage. A power MOSFET 100 having the above structure in the drift region 20 has been developed.
The power MOSFET 100 includes a gate G, a columnar n-type region 20a formed below the gate G, a source S, and a columnar p formed below the source S and between the n-type region 20a. A mold region 20b and a drain region 20c formed at a position spaced from the gate G and the source S and connected to the drift region 20 made of the columnar region group.
[0003]
When the power MOSFET 100 having the above configuration is in the ON state, a drift current flows to the drain region 20c through the n-type columnar regions 20a arranged in parallel. Further, when the power MOSFET 100 is in the OFF state, a high breakdown voltage can be realized by spreading a depletion layer from each pn junction of the p-type columnar region 20b and the n-type columnar region 20a.
[0004]
A silicon wafer 101 for manufacturing such a power MOSFET 100 needs to have a columnar conductivity type region having a desired width and height formed therein. Therefore, the conventional silicon wafer 101 is manufactured as shown in FIG. 5B by silicon epitaxial layers 22, 23 in which p-type and n-type impurity diffusion regions are formed on the main surface of the silicon single crystal substrate 21. , 24 and 25 are laminated.
That is, a silicon epitaxial layer (hereinafter simply referred to as an epitaxial layer) 22 is formed on the main surface of the silicon single crystal substrate 21, and desired impurities are diffused to a desired position of the epitaxial layer by photolithography and ion implantation. Thereafter, columnar p-type and n-type regions are formed by repeating the same process for the epitaxial layers 23, 24, and 25.
[0005]
[Problems to be solved by the invention]
However, as described above, the method of repeating the steps such as epitaxial growth, photolithography, and ion implantation many times costs a lot of manufacturing. In particular, in the case of a high breakdown voltage power MOS substrate, it is necessary to make the p-type and n-type columnar regions higher, so that the number of manufacturing steps further increases and the cost further increases. In addition, the yield may decrease due to many processes during manufacturing.
[0006]
The subject of this invention is providing the manufacturing method of a silicon wafer which can manufacture the board | substrate for power MOSs by a fewer process, and a silicon wafer.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the inventors have formed a trench (groove) in the thickness direction from the main surface of a silicon single crystal wafer, and then formed a silicon epitaxial layer inside the trench. Attempted to manufacture silicon wafers. However, if epitaxial growth is performed to fill the inside of the trench with an epitaxial layer, the growth rate of the epitaxial layer at the opening may be higher than the inside of the trench, such as faceting at the opening of the trench. As a result, the upper part of the trench is blocked without completely forming the epitaxial layer inside the trench, and a slit-like or bubble-like cavity may be formed inside the trench. Thus, if a cavity is formed in the columnar conductivity type region, it is not preferable because it may affect the pressure resistance characteristics or may cause the substrate to crack due to the cavity.
On the other hand, in order to fill the inside of the trench without a cavity, an attempt has been made to form an epitaxial layer inside the trench while removing the epitaxial layer at the opening of the trench by etching or the like. However, in this case as well, it is necessary to perform formation of an epitaxial layer, etching, and the like, which is troublesome. As a result of further studies, the present invention has been achieved.
[0008]
That is, the first means according to the present invention includes a step of forming a trench in the thickness direction from the main surface of the second conductivity type silicon single crystal wafer to form a columnar second conductivity type region, and the silicon single crystal wafer. Trench Side and bottom of the A silicon epitaxial layer of the first conductivity type is formed on the trench, and the trench in which the silicon epitaxial layer is formed is filled with polysilicon doped with an impurity of the first conductivity type, and a columnar shape comprising the silicon epitaxial layer and the polysilicon is formed. Forming a first conductivity type region, wherein the impurity amounts of the columnar first conductivity type region and the second conductivity type region are formed to be equal to each other. .
The silicon wafer manufacturing method of the first means includes a step of polishing the main surface of the silicon single crystal wafer after the formation of the polysilicon, a source and a source on the main surface of the polished silicon single crystal wafer. And a step of bonding a silicon single crystal thin plate for forming a gate or the like.
[0009]
Here, the silicon single crystal wafer may be a mirror wafer formed by slicing from a silicon single crystal ingot, or may be an epitaxial layer formed on the main surface thereof.
Forming a trench in a silicon single crystal wafer means that, for example, when manufacturing a silicon wafer having a columnar n-type region and a columnar p-type region on the main surface, such as for power MOS, A trench for forming a columnar p-type region is formed on the surface. Therefore, in this case, the trench is formed with the desired width and depth of the p-type region.
The same applies when an n-type columnar region is formed in a p-type epitaxial layer formed on the main surface of a silicon single crystal wafer, and the trench is formed to have a desired width and depth of the n-type region. Is done.
In addition, the formation of a silicon epitaxial layer on the inner peripheral surface of the trench means that the side surface and the bottom inside the trench. surface That is, an epitaxial layer is formed on the part. Further, the polysilicon is formed so as to fill the inside of the trench in which the silicon epitaxial layer is formed.
[0010]
According to the first means, a trench is formed in the second conductivity type silicon single crystal wafer to form a columnar second conductivity type region, and the trench Side and bottom of the After the first conductivity type epitaxial layer is formed, the trench is filled with polysilicon doped with the first conductivity type impurity, thereby forming an epitaxial layer along the inner periphery of the trench. A columnar first conductivity type region completely filled with polysilicon, that is, a columnar first conductivity type region composed of the silicon epitaxial layer and the polysilicon can be formed.
For example, when the region around the trench is an n-type epitaxial layer, if the epitaxial layer formed on the inner periphery of the trench is p-type, a depletion layer can be formed in the boundary region between the periphery of the trench and the inner periphery of the trench. it can. If a plurality of such columnar conductive regions are formed in a silicon single crystal wafer, a silicon wafer that can be used for a power MOS can be manufactured.
Therefore, a columnar conductive type region without a cavity can be formed with fewer steps compared to the conventional method, so that labor and cost can be reduced compared to the conventional method, and the yield of the product is reduced. Can be suppressed.
[0011]
In the silicon wafer manufacturing method of the first means, after forming an epitaxial layer on the inner peripheral surface of the trench, an oxide film is formed on the inner surface of the region where the silicon epitaxial layer is formed. The inside of the formed region is made of polysilicon Polish the main surface of the silicon single crystal wafer after filling and forming the polysilicon, and bond the silicon single crystal substrate to the main surface of the polished silicon single crystal wafer May be. In the silicon wafer manufactured in this way, an oxide film is interposed between the silicon epitaxial layer and the polysilicon. Accordingly, it is possible to manufacture a silicon wafer having good insulation between the source and drain when used as a power MOS substrate.
[0012]
According to a second means of the present invention, in a silicon wafer in which columnar first conductivity type regions and second conductivity type regions are alternately formed, one of the first conductivity type region and the second conductivity type region is provided. Is From the main surface of the silicon single crystal wafer to the thickness direction A columnar region left by forming a trench, and the other is the trench Side and bottom of the And the polysilicon portion formed so as to fill the region surrounded by the silicon epitaxial layer, and the impurity amounts of the first conductivity type region and the second conductivity type region are equal. This is a silicon wafer.
[0013]
In the silicon wafer of the second means, polysilicon is formed so as to fill the region surrounded by the silicon epitaxial layer, and the inside of the columnar conductivity type region does not have a cavity, so it is used for a power MOS. This is suitable because the withstand pressure characteristics are good and the occurrence of cracks in the silicon wafer can be suppressed.
[0014]
In the silicon wafer of the second means, the polysilicon portion may be doped with the same type of impurity as either the n-type or p-type impurity doped in the silicon epitaxial layer. In the silicon wafer configured as described above, the charge balance can be controlled by the amount of impurities doped in the polysilicon portion. Therefore, since the amount of impurities can be controlled more easily, manufacturing costs can be reduced and productivity can be improved.
[0015]
In the silicon wafer of the second means, one of the first conductivity type region or the second conductivity type region is From the main surface of the silicon single crystal wafer to the thickness direction Consists of the columnar region left by forming the trench, the other is the trench Side and bottom of the And a polysilicon portion formed so as to fill a region surrounded by the silicon epitaxial layer, and the polysilicon portion in the region surrounded by the oxide film It may be composed of undoped polysilicon. Since the silicon wafer thus configured has an oxide film interposed between the silicon epitaxial layer and the polysilicon portion, the insulation between the source and the drain when used as a substrate for a power MOS is improved.
Furthermore, in the silicon wafer of the second means, the polysilicon portion in the region surrounded by the silicon epitaxial layer may be made of polysilicon not doped with impurities.
As described above, if the polysilicon portion is made of polysilicon that is not doped with impurities, it is preferable that a leakage current is prevented from being generated by applying a voltage when the silicon wafer is used as a power MOSFET. .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[First reference Form)
Hereinafter, referring to FIG. reference As an example, the first reference A form is demonstrated. First reference The silicon wafer manufactured in the form is used for a power MOS, for example.
Book reference In the embodiment, a method for forming a p-type columnar conductivity type region in an n-type epitaxial layer of a silicon epitaxial wafer will be described.
[0017]
Book First reference form In this silicon wafer manufacturing method, an n-type silicon single crystal wafer (hereinafter referred to as wafer 1), which is obtained by slicing a silicon single crystal ingot and performing mirror finishing, is used. The wafer 1 is formed with a drain when used as a power MOS.
[0018]
An n-type silicon epitaxial layer 2 having a desired thickness is formed on the main surface of the wafer 1 by vapor phase growth. The thickness of the n-type epitaxial layer 2 is the height of the desired columnar p-type region.
[0019]
Next, a trench T having a desired shape such as a width is formed in a thickness direction from a desired position (position where a columnar p-type region is formed) on the main surface of the n-type epitaxial layer 2 formed on the main surface of the wafer 1. Let The depth of the trench is equal to the thickness of the epitaxial layer 2 and the bottom of the trench. surface The part is formed so as to reach the main surface of the wafer 1. The trench T is formed by, for example, photolithography and etching.
The planar shape of the trench T (the shape when the wafer 1 is viewed from above) and the number of trenches are arbitrary, and are set as appropriate according to the desired power MOS structure. FIG. 1A shows a cross-sectional shape of the wafer 1 when the trenches T are formed at three locations. When a plurality of trenches T are formed as described above, the interval between the trenches T is appropriately set according to a desired power MOS structure.
[0020]
Silicon epitaxial growth is performed on the wafer 1 on which the trench T is formed, and a p-type epitaxial layer 3 is formed on the side surface and the bottom surface of the trench T.
The p-type epitaxial layer 3 is formed by, for example, a single-wafer type vapor phase growth apparatus. The wafer 1 is placed in a reaction chamber in the apparatus and heated, and on the main surface of the wafer 1, monosilane, dichlorosilane, Alternatively, a silicon source gas such as trichlorosilane and a dopant gas are circulated together with the carrier gas. The dopant gas may be an impurity for forming a p-type semiconductor. For example, diborane (B ₂ H ₆ ) Etc.
[0021]
Here, if the p-type epitaxial layer 3 is formed thick, facets may be formed on the upper portion of the trench T, and the upper portion may be blocked in a state where a cavity is formed inside the trench T. Therefore, in order to form the epitaxial layer 3 without blocking the upper portion of the trench T, the heating temperature of the wafer 1 during the epitaxial growth is lower than the normal epitaxial growth temperature (about 1000 ° C. to 1200 ° C.) (about 700 ° C. to 1000 ° C.). And grow under reduced pressure. Then, since the speed of epitaxial growth becomes slow and the thin epitaxial layer 3 can be formed in the side surface part and bottom face part of the trench T, without blocking the upper part of the trench T, it is preferable.
[0022]
In the wafer 1 (FIG. 1B) in which the epitaxial layer 3 is formed on the side surface and the bottom surface of the trench T (FIG. 1B), no impurity is doped so as to fill the inside of the trench T (hereinafter also referred to as non-doped). ) Polysilicon is formed (FIG. 1C). The polysilicon is formed in the vapor phase growth apparatus by heating the wafer 1 to about 600 ° C. and circulating the silicon source gas. Polysilicon grows amorphous so that the trench can be filled without gaps.
Polysilicon formed inside the trench T surrounded by the epitaxial layer 3 is referred to as a polysilicon portion 4.
[0023]
After the polysilicon portion 4 is formed inside the trench T, the main surface of the n-type epitaxial layer 2 is polished. After the formation of the p-type epitaxial layer 3 and the polysilicon portion 4, the p-type epitaxial layer and polysilicon are deposited not only inside the trench T but also on the main surface of the n-type epitaxial layer 2. Therefore, polishing removes excess p-type epitaxial layer and polysilicon on the main surface of n-type epitaxial layer 2 and flattens the main surface of n-type epitaxial layer 2.
Polishing is performed, for example, by a CMP (Chemical Mechanical Polishing) method.
[0024]
The n-type epitaxial layer 2, the p-type epitaxial layer 3, and the polysilicon portion 4 are formed and the polished wafer is defined as a silicon wafer 10 (FIG. 1 (d)). The region of the trench T manufactured in this way is the side and bottom of the trench T. surface The p-type epitaxial layer 3 is formed in the portion, and the inside is completely filled with the polysilicon portion 4 to become a p-type region 6 (first conductivity type region) having a columnar cross section. As shown in FIG. 1, when a plurality (three in the figure) of columnar p-type regions 6 are formed by the trench T, the upper main surface of the silicon wafer 10 is connected to the columnar p-type region 6 formed in the trench T. The columnar n-type regions 7 (second conductivity type regions) between the trenches T are alternately arranged.
[0025]
Further, a silicon single crystal thin plate 5 is bonded onto the main surface of the silicon wafer 10.
In the bonding method, the thin plate 5 and the main surface of the silicon wafer 10 are brought into close contact with each other without any foreign matter, and then bonded by heat treatment at a temperature of about 1000 to 1200 ° C. The main surface of the bonded thin plate 5 may be polished as necessary to have a desired thickness.
[0026]
The thin plate 5 may be bonded by a hydrogen ion implantation separation method (also called a smart cut method). In this method, after an oxide film is formed on the surface of a silicon single crystal substrate to be bonded, hydrogen ions are implanted into the main surface side to a predetermined depth. Then, after removing the oxide film of the silicon single crystal substrate, the back side is brought into close contact with the main surface of the silicon wafer 10 to perform heat treatment. By this heat treatment, the region where the hydrogen ions are implanted on the main surface side of the silicon single crystal substrate is peeled off, and the thin plate 5 having a predetermined thickness is obtained.
[0027]
A silicon wafer 10 bonded to the thin plate 5 is provided with a source S and a gate G by appropriately forming a p-type region, an n-type region, an oxide film, or the like according to a desired power MOS structure on the thin plate 5. It is used by providing a drain D on the back side of the wafer 10.
In the silicon wafer 10 thus manufactured, a depletion layer can be formed in the boundary region between the columnar p-type region 6 formed in the trench T and the columnar n-type region 7 between the trenches T. A power MOS structure can be formed.
[0028]
According to the method for manufacturing the silicon wafer 10 described above, after forming the n-type epitaxial layer 2 on the main surface of the wafer 1, the step of forming the trench T, and the epitaxial layer 3 on the inner peripheral surface of the trench T are formed. The silicon wafer 10 in which the columnar p-type region 6 and the columnar n-type region 7 are arranged can be manufactured by the step of forming and the step of filling the trench T in which the epitaxial layer 3 is formed with the polysilicon portion 4. . Then, the thin plate 5 can be bonded to the silicon wafer 10 whose surface has been polished after the polysilicon portion 4 is formed, thereby forming a power MOS structure.
Therefore, since the silicon wafer 10 can be manufactured with fewer steps compared to the conventional method by epitaxial layer formation and repetition of photolithography and ion implantation, the cost can be reduced and the decrease in yield can be suppressed. Furthermore, since a columnar conductive type region without a cavity can be formed inside the trench, the manufactured silicon wafer 10 has favorable pressure resistance characteristics and is preferable because the occurrence of cracks due to the cavity is reduced.
[0029]
Book The first reference form is the above description It is not limited to.
For example, by forming a p-type epitaxial layer on a wafer, forming a trench in the p-type layer, and then forming an n-type epitaxial layer inside the trench, a columnar p-type between the columnar n-type region and the trench is formed. An area may be formed.
[0030]
[No. 1 Embodiment of
Hereinafter, the first in the present invention. 1 Embodiments will be described. The manufacturing method of the silicon wafer in the present embodiment, First reference above Since the manufacturing method of the silicon wafer described in the embodiment is the same up to the step of forming the epitaxial layer 3 inside the trench T, the description thereof is omitted.
[0031]
First 1 In this embodiment, when forming the polysilicon portion 4 ′ inside the trench T of the silicon wafer 10 on which the epitaxial layer 3 is formed, a dopant gas is circulated together with the silicon source gas, and impurities are introduced into the polysilicon portion 4 ′. Dope. The impurity is the same type as the epitaxial layer 3 of p-type or n-type. First reference above Since the epitaxial layer 3 is p-type in form, a polysilicon portion 4 ′ doped with p-type impurities is formed.
[0032]
Further, as the amount of impurities doped into the polysilicon portion 4 ′, the sum of the acceptor amounts of the p-type epitaxial layer 3 and the p-type polysilicon portion 4 ′ is made equal to the donor amount of the n-type epitaxial layer 2. . When the silicon wafer thus formed is used as a power MOS, when the MOSFET is in an off state, the depletion layer extends to the inside of the polysilicon portion 4 ′.
In this way, after forming the p-type polysilicon portion 4 ′, First reference above Similar to the embodiment, the main surface of the n-type epitaxial layer 2 is polished to form a silicon wafer 11 (shown in a sectional view in FIG. 2). A silicon single crystal thin film 5 is bonded to the main surface of the silicon wafer 11 and used as a power MOS substrate.
[0033]
In the silicon wafer 11 thus formed, First reference above Like the silicon wafer 10 in the embodiment, the power MOS substrate can be manufactured with fewer steps, and the charge balance can be controlled by the amount of impurities doped in the polysilicon portion 4 ′. Therefore, it is possible to reduce the yield reduction due to the charge balance failure, so that the manufacturing cost can be reduced and the productivity can be improved, which is preferable.
[0034]
[No. Reference of 2 Form)
First Reference of 2 In form, First reference above Since the manufacturing method of the silicon wafer described in the embodiment is the same up to the step of forming the epitaxial layer 3 inside the trench T, the description thereof is omitted.
First Reference of 2 In the embodiment, after the epitaxial layer 3 is formed inside the trench T, the oxide film 41 is formed on the inner surface of the epitaxial layer 3. As a method for forming the oxide film 41, a method using thermal oxidation, a CVD method, or the like can be used. The oxide film 41 is formed without doping impurities.
[0035]
After the formation of the oxide film 41, the polysilicon portion 4 is formed without doping impurities so as to fill the inside of the region surrounded by the oxide film 41. Then the first reference Similar to the embodiment, the main surface of the n-type epitaxial layer 2 is polished to form a silicon wafer 12 (shown in cross-sectional view in FIG. 3). A silicon single crystal thin film 5 is bonded to the main surface of the silicon wafer 12 and used as a power MOS substrate.
[0036]
Polysilicon has a large interface state, and an electron-hole pair is easily generated when an electric field is applied. Therefore, the inside of the epitaxial layer 3 formed inside the trench T is filled with a non-doped polysilicon portion 4 (FIG. 4), or the polysilicon portion 4 ′ is doped with impurities as shown in FIG. When used as a power MOSFET, it is also conceivable that hole electron pairs 40 are generated by application of voltage, resulting in leakage current.
This first Reference of 2 In the silicon wafer 12 manufactured in the form, an oxide film 41 is interposed between the epitaxial layer 3 and the non-doped polysilicon portion 4 and functions as an insulating film. Therefore, between the source and drain when used for a power MOS. Good insulation.
Therefore, the second Reference of 2 According to the embodiment, the power MOS substrate can be manufactured with fewer steps than before, and the silicon wafer 12 with good insulation can be manufactured, which is preferable.
[0037]
Reference form above In this silicon wafer manufacturing method, depending on the desired characteristics of the power MOS substrate, whether or not polysilicon is doped with impurities, and an oxide film is formed between the epitaxial layer in the trench T and the polysilicon portion. A silicon wafer according to the purpose may be manufactured by appropriately selecting whether or not to provide the substrate.
[0038]
【The invention's effect】
According to the first means of the present invention, a trench is formed in the thickness direction from the main surface of the silicon single crystal wafer, and the trench Side and bottom of the After the epitaxial layer is formed on the polysilicon, polysilicon is formed so as to fill the inside of the trench, whereby a columnar conductive type region can be formed inside the silicon single crystal wafer.
Therefore, compared to the conventional method of epitaxial layer formation, photolithography, and ion implantation, the columnar conductive type region can be formed with fewer steps, so the cost can be reduced in the production of power MOS silicon wafers. In addition, a decrease in yield can be suppressed. Furthermore, by filling the inside of the trench with polysilicon, a columnar conductivity type region without a cavity can be formed.
[0039]
According to the second means, one of the first conductivity type region and the second conductivity type region formed in the silicon wafer has its side surface portion and bottom surface. surface A silicon epitaxial layer is formed on the part.
Since the polysilicon is formed so as to fill the region surrounded by the silicon epitaxial layer, the columnar conductivity type region does not have a cavity inside, so that the withstand voltage characteristic is good and the occurrence of cracks in the substrate is suppressed. Is preferable.
[Brief description of the drawings]
FIGS. 1A and 1B show a manufacturing process of a power MOS silicon wafer according to a first embodiment, wherein FIG. 1A shows a trench formed in an n-type epitaxial layer, and FIG. 1B shows a trench in FIG. Side and bottom parts (C) is a state in which the inside of the trench in (b) is filled with polysilicon, (d) is a state in which the main surface of the silicon wafer in (c) is polished, (e) is a state in which the p-type epitaxial layer is formed in FIG. It is sectional drawing which shows a mode that the silicon single crystal thin plate was bonded together to the silicon wafer main surface of (d).
FIG. 2 is a cross-sectional view showing a silicon wafer manufactured according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a silicon wafer manufactured in a second reference embodiment.
FIG. 4 is a cross-sectional view showing how hole electron pairs are generated in the silicon wafer manufactured in the first embodiment.
5A is a cross-sectional view showing an example of a power MOS structure, and FIG. 5B is a cross-sectional view of a power MOS silicon wafer manufactured by a conventional method.
[Explanation of symbols]
1 Wafer (Silicon single crystal wafer)
2 n-type epitaxial layer
3 p-type epitaxial layer (silicon epitaxial layer)
4 Polysilicon part
41 Oxide film
5 Thin plate (silicon single crystal thin plate)
6 Columnar p-type region (first conductivity type region)
7 Columnar n-type region (second conductivity type region)
10, 11, 12 Silicon wafer
T trench

Claims (3)

Forming a columnar second conductivity type region by forming a trench in the thickness direction from the main surface of the second conductivity type silicon single crystal wafer;
Polysilicon in which a first conductivity type silicon epitaxial layer is formed on the side and bottom portions of the trench of the silicon single crystal wafer, and the first conductivity type impurity is doped inside the trench in which the silicon epitaxial layer is formed. Forming a columnar first conductivity type region comprising the silicon epitaxial layer and the polysilicon,
And the columnar first conductivity type region and the second conductivity type region are formed to have the same amount of impurities. Polishing the main surface of the silicon single crystal wafer after the formation of the polysilicon;
Bonding the silicon single crystal thin plate to the main surface of the polished silicon single crystal wafer;
The method for producing a silicon wafer according to claim 1, further comprising: In a silicon wafer in which columnar first conductivity type regions and second conductivity type regions are alternately formed inside,
One of the first conductivity type region or the second conductivity type region is a columnar region left by forming a trench in the thickness direction from the main surface of the silicon single crystal wafer ,
The other consists of a silicon epitaxial layer formed on the side surface and bottom surface of the trench, and a polysilicon portion formed so as to fill a region surrounded by the silicon epitaxial layer,
A silicon wafer, wherein the first conductivity type region and the second conductivity type region have the same amount of impurities.

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