CN107275216A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN107275216A CN107275216A CN201610217390.7A CN201610217390A CN107275216A CN 107275216 A CN107275216 A CN 107275216A CN 201610217390 A CN201610217390 A CN 201610217390A CN 107275216 A CN107275216 A CN 107275216A
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- effect transistor
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- 230000005669 field effect Effects 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000000926 separation method Methods 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 39
- 239000013589 supplement Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 17
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 91
- 238000002347 injection Methods 0.000 description 15
- 239000007924 injection Substances 0.000 description 15
- 230000007423 decrease Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000001502 supplementing effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Abstract
A kind of forming method of fin formula field effect transistor, including：Semiconductor substrate is provided, the semiconductor substrate surface is formed with the discrete and arranged in parallel fin of two or more；In semiconductor substrate surface formation separation layer, the insulation surface is less than the top surface of fin and the partial sidewall of covering fin；The pseudo- grid structure of one or more fins, dummy gate structure covering fin side wall and top are developed across in the insulation surface；Pocket ion implanting, length direction of the pocket ion implanting direction perpendicular to fin are carried out to the fin；In pseudo- grid structure side wall formation side wall, then the fin of pseudo- grid structure and side wall both sides is carried out that ion implanting is lightly doped.Methods described can improve the shadow effect in pocket ion implantation process.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of formation side of fin formula field effect transistor
Method.
Background technology
With continuing to develop for semiconductor process technique, process node is gradually reduced, rear grid (gate-last)
Technique is widely applied, and to obtain preferable threshold voltage, improves device performance.But work as device
Characteristic size when further declining, even if using rear grid technique, the structure of conventional metal-oxide-semiconductor field effect transistor
Also the demand to device performance can not be met, multi-gate device has been obtained extensively as the replacement of conventional device
General concern.
Fin formula field effect transistor is a kind of common multi-gate device, as shown in figure 1, being existing fin
The structural representation of effect transistor.The fin formula field effect transistor includes Semiconductor substrate 10；It is located at
Some fins 20 on substrate 10；Separation layer 30 positioned at the surface of Semiconductor substrate 10, the separation layer 30
Surface be less than the top surface of fin 20, and cover the partial sidewall of fin 20；Positioned at separation layer 30
Surface and across the grid structure of the fin 20, the grid structure includes gate dielectric layer 41 and positioned at institute
State the grid 42 on the surface of gate dielectric layer 41.Be also formed with the fin 20 of the grid structure both sides source electrode and
Drain electrode.In order to improve the channel region area of fin formula field effect transistor, the fin formula field effect transistor
Grid structure is generally across multiple fins 20.
Prior art during the fin formula field effect transistor is formed, it is elongated can be under grid structure
Pocket ion implanting, the pocket ion implanting are carried out between the channel region of side and source electrode, drain region
Doped ions type and fin formula field effect transistor to be formed type on the contrary, formation can be improved
Punch through voltage between the source electrode of fin formula field effect transistor and drain electrode, so as to suppress fin field effect crystal
The Punchthrough effect of pipe, improves the performance of fin formula field effect transistor.
But, in the prior art, to fin formula field effect transistor carry out pocket ion implanting effect compared with
Difference, the Doped ions of pocket injection are hardly entered in source region, drain region close to channel region
Part so that limited to the performance improvement of fin formula field effect transistor, it is necessary to further improve the mouth
The technique of bag ion implanting, further to improve the performance of fin formula field effect transistor.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of fin formula field effect transistor, improves and is formed
Fin formula field effect transistor performance.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
Semiconductor substrate is provided, the semiconductor substrate surface is formed with the discrete and arranged in parallel fin of two or more
Portion；In semiconductor substrate surface formation separation layer, the insulation surface is less than the top table of fin
Face and the partial sidewall for covering fin；The puppet of one or more fins is developed across in the insulation surface
Grid structure, dummy gate structure covering fin side wall and top；Pocket ion is carried out to the fin
Injection, length direction of the pocket ion implanting direction perpendicular to fin；Formed in pseudo- grid structure side wall
Side wall, then to the fin of pseudo- grid structure and side wall both sides carries out that ion implanting is lightly doped.
Optionally, the angle between the pocket ion implanting direction and the normal of Semiconductor substrate is 0 °
~20 °.
Optionally, the pocket ion implanting is divided into twice, and the both sides of fin are carried out respectively.
Optionally, the ionic type of the pocket ion implanting and fin formula field effect transistor to be formed
Type is opposite.
Optionally, the pocket ion implanting forms pocket doped region, the pocket doped region in fin
Positioned at the centre position in the width direction of fin.
Optionally, in addition to：After side wall is formed, supplement pocket ion implanting is carried out to fin.
Optionally, the supplement pocket ion implanting is carried out before ion implanting is lightly doped.
Optionally, the supplement pocket ion implanting is carried out after ion implanting is lightly doped.
Optionally, the direction of the supplement pocket ion implanting is in the projection of substrate surface and the length of fin
Angle between direction is less than 90 °.
Optionally, there is hard mask layer at the top of dummy gate structure.
Optionally, the forming method of the side wall includes：Form covering separation layer, fin, hard mask layer
Spacer material layer.
Optionally, in addition to：The spacer material layer is etched, is formed and is located at pseudo- grid structure side wall surface
Side wall.
Optionally, the material of the side wall is silica or silicon nitride.
Optionally, in addition to：The fin of the pseudo- grid structure both sides of etching, forms groove, in the groove
Stressor layers are epitaxially formed, source electrode and drain electrode is used as.
Optionally, the material of the stressor layers is SiGe, SiC or SiP.
Optionally, using doping process in situ, during stressor layers are epitaxially formed, to the stress
Layer carries out N-type or p-type ion doping.
Optionally, the ion energy of the pocket ion implanting is 0KeV~60KeV, and dosage is 1E13
atom/cm2~1E14atom/cm2。
Optionally, in addition to remove dummy gate structure, be developed across the grid structure of fin.
Compared with prior art, technical scheme has advantages below：
Technical scheme, after the pseudo- grid structure of fin is developed across, carries out pocket ion note
Enter, then re-form side wall.The direction of the pocket ion implanting of the pocket ion implanting and pseudo- grid
Parallelism structural, vertically and fin, so as to avoid making the stop of injecting ion on fin length direction
With the shadow effect of improvement ion implanting.It is additionally, since pseudo- grid structure side wall and does not form sidewall structure,
Carry out pocket ion implanting parallel to pseudo- grid structure, can make the pocket doped region to be formed and pseudo- grid structure it
Between apart from very little, by diffusion can so that pseudo- grid structure below there is pocket doped region, it is and existing
Technology is compared, and can reduce the dosage of the pocket ion implanting, so as to reduce the fin field effect of formation
The resistance of transistor.
Further, it is possible to the ion energy by adjusting the pocket ion implanting, control injection ion
Depth, so that pocket doped region is located at the centre position in the width direction of fin, so as to play
Optimal anti-punch through effect.
Further, after side wall is formed, it can also carry out supplementing pocket ion implanting.Due to described light
The ionic type of Doped ions injection is with the Doped ions type in pocket doped region on the contrary, in diffusion
Under, the charged ion concentration in pocket doped region can be caused to decline, so as to carry out supplementing pocket ion implanting
The decline of charged ion concentration can be made up, strengthens the anti-Punchthrough effect of the pocket doped region.
Brief description of the drawings
Fig. 1 is the structural representation of the fin formula field effect transistor of prior art of the present invention；
Fig. 2 to Fig. 6 is that the structure of the forming process of the fin formula field effect transistor of embodiments of the invention is shown
It is intended to.
Embodiment
As described in the background art, it is existing that the pocket ion implanting that fin formula field effect transistor is carried out is entered
The ion dose entered in source region, drain region close to channel region is smaller, and the break-through to source-drain electrode shows
It is limited as improving.
Research is found, because prior art would generally form some adjacent fins on a semiconductor substrate,
Also, the grid structure of fin formula field effect transistor generally also can be simultaneously across multiple fins, to improve fin
The channel region area of formula field-effect transistor.Because the integrated level of existing semiconductor chip is all higher, so,
Spacing between adjacent fin is also smaller.In order to improve short-channel effect, it will usually in gate structure sidewall
Formed after side wall, then carry out pocket ion implanting.The pocket ion implanting needs to note Doped ions
Enter in the fin between channel region and source drain region, so, the injection side of the pocket ion implanting
, will to that would generally have certain angle between the short transverse of fin and the length direction of fin
Doped ions inject fin at the position of grid structure.
Due to the fin for raised stereochemical structure, it is necessary to the both sides of source electrode and drain electrode are carried out respectively from
Son injection, it is existing during ion implanting is carried out, in ion implanting direction and the short transverse of fin
In the case that the angle of support is certain, typically cause the projection of ion implanting direction on a semiconductor substrate with
Angle between fin length direction is 45 ° or 90 °, in order to be carried out to source electrode and drain electrode diverse location
During ion implanting, the angle of convenient adjustment injection.
When the angle is 45 °, because the distance between adjacent fin is smaller, pocket ion is being carried out
During injection, adjacent fin can have certain effect of blocking to the ion beam of injection, thus to from
Son injection produces shadow effect, causes the quantity that above-mentioned pocket ion implanting is reached near channel region to reduce,
Punchthrough problem can not be effectively improved；And when the angle is 90 °, due to the stop of side wall, again
It is difficult to which the injection ion made enters in channel region, it is impossible to be effectively improved Punchthrough effect.
Embodiments herein, after the pseudo- grid structure of fin is developed across, carries out pocket ion implanting,
The pocket ion implanting direction can improve shadow effect perpendicular to the length direction of fin.
In the present embodiment, between the direction of the pocket ion implanting and the normal of the Semiconductor substrate
Angle is 0 °~20 °, in other embodiments of the invention, can also according to the height of the fin and
Spacing between adjacent fin, adjusts the angle between the pocket ion implanting and Semiconductor substrate normal.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 2 be refer to there is provided Semiconductor substrate 100, the surface of Semiconductor substrate 100 is formed with two
The discrete and arranged in parallel fin 101 of the above；Separation layer 200 is formed on the surface of Semiconductor substrate 100,
The surface of separation layer 200 is less than the top surface of fin 101 and the partial sidewall of covering fin 101；
The pseudo- grid structure 300 of one or more fins 101, the puppet are developed across on the surface of separation layer 200
Grid structure 300 covers the side wall of fin 101 and top.
The material of the Semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs,
The Semiconductor substrate 100 can be that body material can also be composite construction such as silicon-on-insulator.This area
Technical staff according to the semiconductor devices that is formed in Semiconductor substrate 100 semiconductor can be selected to serve as a contrast
The type at bottom 100, therefore the type of the Semiconductor substrate 100 should not limit the scope of the invention.
In the present embodiment, the material of the Semiconductor substrate 100 is monocrystalline silicon wafer crystal.
By being performed etching to Semiconductor substrate 100 fin can be formed in the Semiconductor substrate 100
101, it can also be formed in the Semiconductor substrate 100 after epitaxial layer, etch the epitaxial layer and formed
The fin 101.
In the present embodiment, to form five fins 101 on a semiconductor substrate 100 as an example, at this
In the other embodiment of invention, it can also be formed with the Semiconductor substrate 100 multiple discrete and parallel
The fin 101 of arrangement.
The material of the separation layer 200 can be the dielectric material such as silica, silicon nitride, silicon oxide carbide
Material, the separation layer 200 is used as the isolation structure between adjacent fin 101, and the grid being subsequently formed
Isolation structure between pole structure and Semiconductor substrate 100.
The forming method of the separation layer 200 includes：The deposition isolation material in the Semiconductor substrate 100
Material, the isolated material covers fin 101, and fills the groove between the adjacent fin 101 of full phase；
Using the top of fin 101 as polish stop layer, using chemical mechanical milling tech to the isolation material
Material carries out planarization process, forms the spacer material layer flushed with the top surface of fin 101；Then, it is right
The spacer material layer is etched back, and declines the apparent height of the spacer material layer, forms surface
Less than the separation layer 200 of the top surface of fin 101.
Formed after the fin 101, ion doping can be carried out to the fin 101, such as trap is mixed
It is miscellaneous, adjusting thresholds doping etc..
Dummy gate structure 300 includes：Pseudo- gate dielectric layer (not shown) and it is situated between positioned at the pseudo- grid
The dummy grid of matter layer surface.The material of the pseudo- gate dielectric layer is silica, and the material of the dummy grid is
Polysilicon, subsequently using rear grid technique, forms metal gate structure to replace dummy gate structure 300.
Dummy gate structure also has hard mask layer, including silicon nitride layer 401 and positioned at silicon nitride layer 401
The silicon oxide layer 402 on surface.Before dummy gate structure 300 is formed, oxygen can be carried out to fin portion surface
Change is handled, and is formed oxide layer, is used as pseudo- gate dielectric layer.
The forming method of dummy gate structure 300 includes：Pseudo- grid are formed on the surface of separation layer 200 to be situated between
The material bed of material, the pseudo- gate dielectric material layer covering separation layer 200 and fin 101, in the pseudo- grid
Dielectric material layer surface formation dummy grid material layer, then forms in the dummy grid material surface and covers firmly
Film layer, using the hard mask layer as mask, is carried out to the dummy grid material layer and pseudo- gate dielectric material layer
Graphically, it is developed across the pseudo- grid structure 300 of fin 101.
Fig. 3 is refer to, pocket ion implanting, the pocket ion implanting direction are carried out to the fin 101
Perpendicular to the length direction of fin 101, and angle between the normal of the Semiconductor substrate 100 is
0 °~20 °.
The fin 101 of the side of dummy gate structure 300 is source electrode or drain region, the pocket ion note
Entering needs to form pocket doped region between the channel region of transistor and source electrode or drain region, and described
The type of the Doped ions type of pocket ion implanting and fin formula field effect transistor to be formed on the contrary, with
Improve the source-drain electrode punch through voltage of transistor.
The direction of the pocket ion implanting is parallel with pseudo- grid structure 300, vertically with fin 101, so as to
To avoid on the length direction of fin 101 to the barrier effect for injecting ion, pseudo- grid structure 300 is additionally, since
Side wall does not form sidewall structure, carries out pocket ion implanting parallel to pseudo- grid structure 300, can make shape
Into the distance between pocket doped region and pseudo- grid structure 300 very little, by diffusion can so that pseudo- grid
There is pocket doped region below structure, compared with prior art, the pocket ion implanting can be reduced
Dosage, so as to reduce the resistance of the fin formula field effect transistor of formation.
The ion energy of the pocket ion implanting is 0KeV~60KeV, and dosage is 1E13
atom/cm2~1E14atom/cm2。
In the present embodiment, the pocket ion implanting is divided into be carried out twice, respectively to the both sides of fin 101
Injected, can so reduce the ion dose of bolus injection, so as to reduce the one side to fin 101
The implant damage that surface is subject to.
In other embodiments of the invention, only can also be carried out in the side of fin 101 above-mentioned pocket from
Son injection.
Fig. 4 is refer to, to be formed after pocket doped region 102, the section along the vertical direction of fin 101 shows
It is intended to.
In the present embodiment, by adjusting the ion energy of the pocket ion implanting, control injection ion
Depth, so that pocket doped region 102 is located at the centre position in the width direction of fin 101, from
And optimal anti-punch through effect can be played.
In other embodiments of the invention, the pocket doped region 102 can also be in other positions.
Fig. 5 is refer to, the wall formation side wall 500 in dummy gate structure 300 (refer to Fig. 4) side, so
Afterwards the fin 101 of pseudo- grid structure and the both sides of side wall 200 is carried out that ion implanting is lightly doped.
In the present embodiment, the forming method of the side wall 500 includes：Form covering separation layer 200, fin
101st, the spacer material layer of hard mask 401,402.Positioned at the part side of the pseudo- sidewall surfaces of grid structure 300
The walling bed of material is as side wall 500, in the present embodiment, remains the spacer material layer of other positions.
In other embodiments of the invention, spacer material layer can also be performed etching, only retained
Spacer material layer on the pseudo- side wall of grid structure 300, is used as side wall 500.
The material of the side wall 500 can be silica or silicon nitride, in the present embodiment, the side wall 500
Material be silicon nitride.The spacer material layer can be formed using chemical vapor deposition method.
Formed after the side wall 500, to 500 liang of side wall in dummy gate structure 500 and its side wall
The fin of side be lightly doped ion implanting, the ionic type that ion implanting is lightly doped with it is to be formed
The type of fin formula field effect transistor is consistent, the short-channel effect for improving transistor.
By adjusting the thickness of the side wall 500, can limit formation is lightly doped injection region and pseudo- grid knot
The distance between channel region of the lower section of structure 500.
Refer to Fig. 6 for carry out it is described be lightly doped after ion implanting, formation lightly doped district 103 along fin
The diagrammatic cross-section of portion's length direction.
The pocket doped region 101 is located at can prevent source and drain from wearing between lightly doped district 103 and channel region
Correspond topic.
In other embodiments of the invention, can also be according to reality after the side wall 500 is formed
Situation, supplement pocket ion implanting is carried out to fin 101.The supplement pocket ion implanting is being lightly doped
Carry out, can also be carried out after ion implanting is lightly doped before ion implanting.
The ionic type of ion implanting and the Doped ions class in pocket doped region 102 is lightly doped due to described
Type on the contrary, under diffusion, the charged ion concentration in pocket doped region 102 can be caused to decline, from
And the decline of charged ion concentration can be made up by carrying out supplement pocket ion implanting, strengthen the pocket doping
The anti-Punchthrough effect in area.
The direction of the supplement pocket ion implanting is between the projection of substrate surface and the length direction of fin
Angle be less than 90 °, with ensure it is described supplement pocket ion implanting ion can enter lightly doped district 103
Between the channel region of the pseudo- lower section of grid structure 300.
In the present embodiment, the forming method of the fin formula field effect transistor also includes：The pseudo- grid structure of etching
The fin 101 of 300 both sides, forms groove, is epitaxially formed stressor layers in the groove 101, is used as source
Pole and drain electrode.
The material of the stressor layers can be SiGe, SiC or SiP etc., if the fin to be formed effect
It is p type field effect transistor to answer transistor, then the material of the stressor layers can be SiGe, if described treat
The fin formula field effect transistor of formation is N-type fin formula field effect transistor, then the material of the stressor layers is
SiP。
During stressor layers are epitaxially formed, the stressor layers can be entered using doping process in situ
Shape N-type or p-type ion doping, or Doped ions in the stressor layers progress of formation are injected, make described answer
Power layer is that N-type or p-type are adulterated.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (18)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
Semiconductor substrate is provided, it is discrete and arranged in parallel that the semiconductor substrate surface is formed with two or more
Fin；
In semiconductor substrate surface formation separation layer, the insulation surface is less than the top table of fin
Face and the partial sidewall for covering fin；
The pseudo- grid structure of one or more fins, dummy gate structure are developed across in the insulation surface
Cover fin side wall and top；
Pocket ion implanting, length of the pocket ion implanting direction perpendicular to fin are carried out to the fin
Spend direction；
In pseudo- grid structure side wall formation side wall, then the fin of pseudo- grid structure and side wall both sides is gently mixed
Heteroion injects.
2. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
Angle between the normal of pocket ion implanting direction and the Semiconductor substrate is 0 °~20 °.
3. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
Pocket ion implanting is divided into twice, and the both sides of fin are carried out respectively.
4. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
The ionic type of pocket ion implanting is opposite with the type of fin formula field effect transistor to be formed.
5. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
Pocket ion implanting forms pocket doped region in fin, the pocket doped region be located at fin along width
Spend the centre position in direction.
6. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap
Include：After side wall is formed, supplement pocket ion implanting is carried out to fin.
7. the forming method of fin formula field effect transistor according to claim 6, it is characterised in that described
Supplement pocket ion implanting is carried out before ion implanting is lightly doped.
8. the forming method of fin formula field effect transistor according to claim 6, it is characterised in that described
Supplement pocket ion implanting is carried out after ion implanting is lightly doped.
9. the forming method of the fin formula field effect transistor according to claim 7 or 8, it is characterised in that
The direction of the supplement pocket ion implanting is between the projection of substrate surface and the length direction of fin
Angle is less than 90 °.
10. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
Pseudo- grid structural top has hard mask layer.
11. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
The forming method of side wall includes：Form the spacer material layer of covering separation layer, fin, hard mask layer.
12. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that also wrap
Include：The spacer material layer is etched, the side wall for being located at pseudo- grid structure side wall surface is formed.
13. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that described
The material of side wall is silica or silicon nitride.
14. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap
Include：The fin of the pseudo- grid structure both sides of etching, forms groove, stressor layers is epitaxially formed in the groove,
It is used as source electrode and drain electrode.
15. the forming method of fin formula field effect transistor according to claim 14, it is characterised in that described
The material of stressor layers is SiGe, SiC or SiP.
16. the forming method of fin formula field effect transistor according to claim 14, it is characterised in that use
The stressor layers during stressor layers are epitaxially formed, are carried out N-type or P by doping process in situ
Type ion doping.
17. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
The ion energy of pocket ion implanting is 0KeV~60KeV, and dosage is 1E13atom/cm2~1E14
atom/cm2。
18. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap
Removal dummy gate structure is included, the grid structure of fin is developed across.
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