CN107492496B - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
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- CN107492496B CN107492496B CN201610407517.1A CN201610407517A CN107492496B CN 107492496 B CN107492496 B CN 107492496B CN 201610407517 A CN201610407517 A CN 201610407517A CN 107492496 B CN107492496 B CN 107492496B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 150000002500 ions Chemical class 0.000 claims abstract description 294
- 238000000034 method Methods 0.000 claims abstract description 134
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 238000002955 isolation Methods 0.000 claims abstract description 49
- 230000008569 process Effects 0.000 claims abstract description 46
- 238000000137 annealing Methods 0.000 claims abstract description 41
- 238000002347 injection Methods 0.000 claims description 32
- 239000007924 injection Substances 0.000 claims description 32
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- -1 boron ion Chemical class 0.000 claims description 5
- 238000002156 mixing Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 241000208340 Araliaceae Species 0.000 claims 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 2
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 2
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- 230000000694 effects Effects 0.000 abstract description 25
- 239000010410 layer Substances 0.000 description 73
- 239000000463 material Substances 0.000 description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 238000010849 ion bombardment Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000008439 repair process Effects 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
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- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 5
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- 230000002829 reductive effect Effects 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
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- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
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- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and its manufacturing method, which comprises provide substrate, substrate has fin；Isolation structure is formed on substrate between fin, protrudes from the fin of isolation structure as fin first area；It is developed across fin and covers the gate structure on institute's fin first area atop part surface and sidewall surfaces；Using gate structure as exposure mask, the first lightly doped technique is carried out to the side of fin first area, Doped ions are the first ion；Using gate structure as exposure mask, the second lightly doped technique is carried out to the other side of fin first area, Doped ions are the second ion, and the second ionic type is identical as the first ionic type, and the atomic mass of the second ion is less than the atomic mass of the first ion；After first lightly doped technique and the second lightly doped technique, annealing process is carried out to substrate.By the combination of the first ion and the second ion, the quality of fin had not only been improved, but also has improved the short-channel effect of device, and then has optimized the electric property of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor field more particularly to a kind of semiconductor structure and its manufacturing methods.
Background technique
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature size persistently subtracts
It is small.For the reduction of meeting market's demand size, the channel length of MOSFET field-effect tube is also corresponding constantly to be shortened.However, with device
The shortening of part channel length, device source electrode between drain electrode at a distance from also shorten therewith, therefore grid to the control ability of channel with
Variation, the difficulty of grid voltage pinch off (pinch off) channel is also increasing, so that sub-threshold leakage
(subthreshold leakage) phenomenon, i.e., so-called short-channel effect (SCE:short-channel effects) are more held
Easily occur.
Therefore, for the reduction of better meeting market's demand size, semiconductor technology gradually starts from planar MOSFET crystal
Pipe to more high effect three-dimensional transistor transient, such as fin field effect pipe (FinFET).In FinFET, grid are extremely
Ultra-thin body (fin) can be controlled from two sides less, there is control of the grid more much better than than planar MOSFET devices to channel
Ability can be good at inhibiting short-channel effect；And FinFET has better existing integrated circuit relative to other devices
The compatibility of manufacturing technology.
But the electric property of the semiconductor devices of prior art formation is still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and its manufacturing method, optimizes the electricity of semiconductor devices
Performance.
To solve the above problems, the present invention provides a kind of manufacturing method of semiconductor structure, comprising: substrate is provided, it is described
Substrate has fin；Isolation structure is formed on substrate between the fin, wherein protruding from the fin of the isolation structure
As fin first area；It is developed across the gate structure of the fin, the gate structure covers the fin first area
Atop part surface and sidewall surfaces；Using the gate structure as exposure mask, the is carried out to the side of the fin first area
One lightly doped technique forms first and ion area is lightly doped, and the Doped ions of first lightly doped technique are the first ion；With institute
Stating gate structure is exposure mask, carries out the second lightly doped technique to the other side of the fin first area, forms second and be lightly doped
Ion area, the Doped ions of second lightly doped technique are the second ion, wherein second ionic type and described first
Ionic type is identical, and the atomic mass of second ion is less than the atomic mass of first ion；First is lightly doped work
After skill and the second lightly doped technique, annealing process is carried out to the substrate.
Optionally, the substrate is used to form N-type device, and first ion and the second ion are N-type ion.
Optionally, first ion is As ion, and second ion is P ion.
Optionally, it is 1Kev to 8Kev that the parameter of first lightly doped technique, which includes: the ion energy of injection, injection
Ion dose is 1E14 to 8E14 atom per square centimeter, and implant angle is 7 degree to 20 degree.
Optionally, it is 1Kev to 6Kev that the parameter of second lightly doped technique, which includes: the ion energy of injection, injection
Ion dose is 1E14 to 5E14 atom per square centimeter, and implant angle is 7 degree to 20 degree.
Optionally, the annealing process is laser annealing, spike annealing or rapid thermal anneal process.
Optionally, the annealing process is spike annealing process；The technological parameter of the annealing process includes: annealing temperature
It is 900 degrees Celsius to 1050 degrees Celsius, pressure is a standard atmospheric pressure, and reaction gas is nitrogen, and the gas flow of nitrogen is 5
Standard per minute rises to 40 standard liters per minute.
Optionally, after carrying out annealing process to the substrate, the manufacturing method further include: in the gate structure two sides
Fin in formed source and drain doping area.
Optionally, the substrate includes first area and second area, and the first area substrate is used to form N-type device
Part, the second area substrate are used to form P-type device；Fin on the first area substrate is the first fin, position
In the fin on the second area substrate be the second fin；The first fin for protruding from the first area isolation structure is the
One fin first area, the second fin for protruding from the second area isolation structure is the second fin first area；To described
The side of fin first area carried out in the step of the first lightly doped technique, carried out to the side of first fin first area
First lightly doped technique；In the step of carrying out the second lightly doped technique to the other side of the fin first area, to described the
The other side of one fin first area carries out the second lightly doped technique；Before carrying out annealing process to the substrate, the manufacture
Method further include: third lightly doped technique is carried out to second fin first area, third is formed and ion area is lightly doped.
Optionally, it is 2Kev to 8Kev that the parameter of the third lightly doped technique, which includes: the ion energy of injection, injection
Ion dose is 8E13 to 5E14 atom per square centimeter, and implant angle is 7 degree to 20 degree.
Optionally, the step of carrying out annealing process to the substrate includes: while ion area, the is lightly doped to described first
The second light industry bureau Doped ions area and third are lightly doped ion area and carry out annealing process, with active ions.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate have fin；Isolation junction
Structure, on the substrate between the fin, wherein protruding from the fin of the isolation structure as fin first area；Grid
Structure, atop part surface and sidewall surfaces across the fin and the covering fin first area；First be lightly doped from
Sub-district, the side in the fin first area, the described first Doped ions that ion area is lightly doped are the first ion；The
The second light industry bureau Doped ions area, the other side in the fin first area, described second is lightly doped the Doped ions in ion area
For the second ion, wherein second ionic type is identical as first ionic type, the atomic mass of second ion
Less than the atomic mass of first ion.
Optionally, the semiconductor structure is N-type device, and first ion and the second ion are N-type ion.
Optionally, first ion is As ion, and second ion is P ion.
Optionally, the described first ion concentration that ion area is lightly doped is that 1E19 atoms per cubic centimeter is every to 5E20 atom
Cubic centimetre.
Optionally, the described second ion concentration that ion area is lightly doped is that 1E19 atoms per cubic centimeter is every to 5E20 atom
Cubic centimetre.
Optionally, the semiconductor structure further include: source and drain doping area, in the fin of the gate structure two sides.
Optionally, the substrate includes first area and second area, and the semiconductor structure of the first area is N-type device
Part, the semiconductor structure of the second area are P-type device；Fin on the first area substrate is the first fin,
Fin on the second area substrate is the second fin；The first fin for protruding from the first area isolation structure is
First fin first area, the second fin for protruding from the second area isolation structure is the second fin first area；It is described
First is lightly doped the side that ion area is located in first fin first area；Described second is lightly doped ion area positioned at described
The other side in first fin first area；The semiconductor structure further include: in second fin first area
Ion area is lightly doped in third.
Optionally, it includes boron ion that the Doped ions in ion area, which are lightly doped, in the third, and ion area is lightly doped in the third
Ion concentration be 8E13 atoms per cubic centimeter to 5E14 atoms per cubic centimeter.
Compared with prior art, technical solution of the present invention has the advantage that
The present invention carries out the first lightly doped technique to the side of the fin first area, first lightly doped technique
Doped ions are the first ion, carry out the second lightly doped technique to the other side of the fin first area, second is lightly doped work
The Doped ions of skill be the second ion, wherein second ionic type is identical as first ionic type, described second from
The atomic mass of son is less than the atomic mass of first ion.On the one hand by only mixing the side of the fin first area
The heavier ion of impurity level avoids the fin of the fin first area other side from converting due to the doping heavier ion of quality
At amorphous state, to make not mentioned by the part fin first area of first ion bombardment during subsequent annealing process
For more monocrystal materials, avoid the problem that the fin first area is difficult to repair into monocrystalline state because lacking monocrystal material,
And then improve the quality of the fin；On the other hand lighter weight is adulterated by the other side only to the fin first area
Ion, avoid the ion horizontal proliferation of excessive lighter weight into channel region, imitated so as to improve the short channel of device.Therefore, lead to
The combination of the first ion and the second ion is crossed, the quality of fin has not only been improved, but also improves the short-channel effect of device, Jin Eryou
The electric property of semiconductor devices is changed.
In semiconductor structure provided by the invention, described first, which is lightly doped ion area, is located in the fin first area
Side, the described first Doped ions that ion is lightly doped are the first ion；Described second, which is lightly doped ion area, is located at the fin
The other side in first area, the described second Doped ions that ion is lightly doped are the second ion；Wherein, second ionic species
Type is identical as first ionic type, and the atomic mass of second ion is less than the atomic mass of first ion.One
Aspect avoids the fin first area other side from being lightly doped in the forming process in ion area first, because by heavier mass
First ion bombardment and amorphous state is converted to by monocrystalline state, to make not the firstth area of part fin by first ion bombardment
Domain provides more single phase materials in fin repair process, amorphous material is converted to single phase material again, in turn
Improve the quality of the fin；On the other hand, can to avoid excessive lighter weight ion horizontal proliferation to device channel region, from
And the short-channel effect of device can be improved.Therefore, by the combination of the first ion and the second ion, the fin had both been improved
Quality, and the short-channel effect of device is improved, so that the electric property of semiconductor devices be made to be optimized.
Detailed description of the invention
Fig. 1 and Fig. 2 is each step counter structure schematic diagram in a kind of manufacturing method of semiconductor structure；
Fig. 3 is a kind of Electronic Speculum schematic diagram of semiconductor structure；
Fig. 4 to Figure 13 is each step counter structure schematic diagram in one embodiment of manufacturing method of semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that the electric property for the FinFET that the prior art is formed is still to be improved.
Its reason is analyzed in conjunction with a kind of forming method of semiconductor structure.In conjunction with reference Fig. 1 and Fig. 2, a kind of half is shown
Each step counter structure schematic diagram in the manufacturing method of conductor structure.
With reference to Fig. 1, substrate 100 is provided, there is fin 110 on the substrate 100；Substrate between the fin 110
Isolation structure 101 is formed on 100, wherein the fin 110 for being exposed to the isolation structure is used as fin first area (not indicating)；
It is developed across the gate structure 102 of the fin 110, the gate structure 102 covers the part top of the fin first area
Portion surface and sidewall surfaces；It is exposure mask with the gate structure 102, lightly doped technique 120 is carried out to the fin first area,
Ion area (not shown) is lightly doped in formation.
In the above method, the substrate 100 is used to form N-type device；The Doped ions of the lightly doped technique 120 are N
Type ion.Specifically, the N-type ion includes As ion or P ion.
But when the Doped ions of the lightly doped technique 120 are P ion, since the atomic mass of P ion is lighter,
When carrying out the lightly doped technique 120, horizontal proliferation is easy to device channel region, to be easy the short-channel effect to device
(SCE:short-channel effects) generates adverse effect, and then causes bad shadow to the electric property of semiconductor devices
It rings.
When the Doped ions of the lightly doped technique 120 are As ion, in conjunction with referring to figs. 2 and 3, Fig. 2 is the edge Fig. 1
The schematic diagram of the section structure in the direction AA1, Fig. 3 are the electron microscope of region B in Fig. 2.It is described since the atomic mass of As ion is heavier
After fin first area is by As ion bombardment, the material of the two sides of the fin first area is easy to be converted to by monocrystalline state non-
Crystalline state, i.e. two sides are converted to amorphous layer 111 (as shown in Figure 2)；After subsequent annealing process, the amorphous layer 110 is easy
More serious (the i.e. more fins of the phenomenon that being difficult to repair into monocrystalline state because lacking single phase material, and being converted to amorphous layer 110
The material of first area is converted to amorphous layer 110), the fin first area is just more difficult to repair, so as to cause the fin
The quality of portion first area declines, and then causes adverse effect to the electric property of semiconductor devices.
In order to solve the technical problem, the present invention provides a kind of manufacturing method of semiconductor devices, comprising: provides lining
Bottom, the substrate have fin；Isolation structure is formed on substrate between the fin, wherein protruding from the isolation structure
Fin as fin first area；It is developed across the gate structure of the fin, the gate structure covers the fin the
The atop part surface in one region and sidewall surfaces；Using the gate structure as exposure mask, to the side of the fin first area
Carry out the first lightly doped technique, form first and be lightly doped ion area, the Doped ions of first lightly doped technique be first from
Son；Using the gate structure as exposure mask, the second lightly doped technique is carried out to the other side of the fin first area, forms second
Ion area is lightly doped, the Doped ions of second lightly doped technique are the second ion, wherein second ionic type and institute
State that the first ionic type is identical, and the atomic mass of second ion is less than the atomic mass of first ion；First is light
After doping process and the second lightly doped technique, annealing process is carried out to the substrate.
The present invention carries out the first lightly doped technique to the side of the fin first area, first lightly doped technique
Doped ions are the first ion, carry out the second lightly doped technique to the other side of the fin first area, second is lightly doped work
The Doped ions of skill be the second ion, wherein second ionic type is identical as first ionic type, described second from
The atomic mass of son is less than the atomic mass of first ion.On the one hand by only mixing the side of the fin first area
The heavier ion of impurity level avoids the fin of the fin first area other side from converting due to the doping heavier ion of quality
At amorphous state, to make not mentioned by the part fin first area of first ion bombardment during subsequent annealing process
For more monocrystal materials, avoid the problem that the fin first area is difficult to repair into monocrystalline state because lacking monocrystal material,
And then improve the quality of the fin；On the other hand lighter weight is adulterated by the other side only to the fin first area
Ion, avoid the ion horizontal proliferation of excessive lighter weight into channel region, imitated so as to improve the short channel of device.Therefore, lead to
The combination of the first ion and the second ion is crossed, the quality of fin has not only been improved, but also improves the short-channel effect of device, Jin Eryou
The electric property of semiconductor devices is changed.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 13 is each step counter structure schematic diagram in one embodiment of manufacturing method of semiconductor structure of the present invention.
In conjunction with reference Fig. 4 and Fig. 5, wherein Fig. 4 is the perspective view (only illustrating two fins) of semiconductor structure, and Fig. 5 is
Fig. 4 provides substrate 200 along the schematic diagram of the section structure in the direction CC1, and the substrate 200 has fin (not indicating).
The substrate 200 provides technique platform to be subsequently formed semiconductor devices.
In the present embodiment, the substrate 200 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be on the silicon substrates or insulator on insulator
Germanium substrate.
In the present embodiment, the substrate 200 includes first area I (as shown in Figure 5) and second area II (such as Fig. 5 institute
Show).Correspondingly, the fin being located on I substrate 200 of first area is the first fin 210, it is located at the second area II and serves as a contrast
Fin on bottom 200 is the second fin 220.
The material of first fin 210 and second fin 220 is identical as the material of the substrate 200.This implementation
In example, the material of first fin 210 and the second fin 220 is silicon.In other embodiments, first fin and described
The material of two fins can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the first area I is used to form N-type device, and the second area II is used to form p-type device
Part.In another embodiment, the first area is used to form P-type device, and the second area is used to form N-type device.In
In other embodiments, the first area and second area are used to form N-type device.
Specifically, the step of providing the substrate 200 and fin includes: offer initial substrate, on the initial substrate
Form patterned hard mask layer 300；It is exposure mask with the hard mask layer 300, etches the initial substrate, is formed several discrete
Protrusion；The protrusion is fin, and for the initial substrate after etching as substrate 200, the substrate 200 includes I He of first area
Second area II, the fin positioned at the first area I are the first fin 210, and the fin positioned at the second area II is the
Two fins 220.
In the present embodiment, the material of the hard mask layer 300 is silicon nitride, subsequent when carrying out flatening process, described
300 surface of hard mask layer is used to define the stop position of flatening process, and the hard mask layer 300 can also play protection institute
State the effect at 220 top of 210 top of the first fin and the second fin.
It should be noted that after the substrate 200 and fin are provided, the manufacturing method further include: described first
Fin 210 and 220 surface of the second fin form cushion oxide layer (not shown), for repairing first fin 210 and second
Fin 220.
In oxidation processes, due to the ratio table for the faceted portions that first fin 210 and the second fin 220 protrude
Face is bigger, it is easier to it is oxidized, after the subsequent removal cushion oxide layer, and not only first fin 210 and the second fin
The defect layer on 220 surfaces is removed, and is protruded faceted portions and be also removed, and first fin 210 and the second fin 220 are made
Surface is smooth, and lattice quality is improved, and avoids 220 apex angle point discharge problem of first fin 210 and the second fin, has
Conducive to the performance for improving fin field effect pipe.
In the present embodiment, the cushion oxide layer is also located at 200 surface of substrate, and the material of the cushion oxide layer is
Silica.
Unless otherwise instructed, the structural schematic diagram provided during subsequent technique is schematic diagram on the basis of Fig. 5.
With reference to Fig. 6, isolation structure 201 is formed on the substrate 200 between the fin (not indicating), wherein protruding from institute
The fin for stating isolation structure 201 (does not indicate) as fin first area.
Isolation structure of the isolation structure 201 as semiconductor structure, for playing buffer action to adjacent devices.This
In embodiment, the material of the isolation structure 201 is silica.In other embodiments, the material of the isolation structure 201 is also
It can be silicon nitride, silicon oxynitride or carbon silicon oxynitride.
It should be noted that the isolation structure 201 is shallow groove isolation layer, but is not limited to shallow trench in the present embodiment
Separation layer.
In the present embodiment, the fin includes the first fin 210, Yi Jiwei on I substrate 200 of first area
The second fin 210 on II substrate 200 of second area.Correspondingly, protruding from I isolation structure 201 of first area
The first fin 210 be the first fin first area (not indicating)；Protrude from the second of II isolation structure 201 of second area
Fin 220 is the second fin first area (not indicating).
Specifically, the step of forming isolation structure 201 include: in the cushion oxide layer (not shown) formed every
From film, the top of the isolation film is higher than the hard mask layer 300 top (as shown in Figure 5)；Grinding removal is covered firmly higher than described
The isolation film at 300 top of film layer；The isolation film of segment thickness is removed to form isolation structure 201；Remove the hard mask layer
300。
It should be noted that also removing the liner oxygen of part fin portion surface in while removing the isolation film of segment thickness
Change layer.
With reference to Fig. 7, it is developed across the gate structure (not indicating) of the fin (not indicating), the gate structure covers institute
State atop part surface and the sidewall surfaces of fin first area (not indicating).
In the present embodiment, the gate structure includes the first grid across first fin first area (not indicating)
Structure 211, the first grid structure 211 cover atop part surface and the sidewall surfaces of first fin first area；
It further include the second grid structure 221 across second fin first area (not indicating), the second grid structure 221 is covered
Cover atop part surface and the sidewall surfaces of second fin first area.
In the present embodiment, the gate structure is pseudo- grid structure, and the gate structure is used to be subsequently formed metal gates
Structure takes up space position.
The gate structure is single layer structure or laminated construction, and the gate structure includes pseudo- grid layer or the grid
Structure includes pseudo- oxide layer and the pseudo- grid layer positioned at pseudo- oxidation layer surface.The material of the puppet oxide layer is silica, described
The material of pseudo- grid layer is polysilicon, silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous
Carbon.In the present embodiment, the material of the puppet grid layer is polysilicon.
In another embodiment, the gate structure is metal gate structure.The gate structure include gate dielectric layer with
And the gate electrode layer positioned at the gate dielectric layer surface, wherein the material of gate dielectric layer be silica or high-k gate dielectric material,
The material of the gate electrode layer be polysilicon or metal material, the metal material include Ti, Ta, TiN, TaN, TiAl,
One of TiAlN, Cu, Al, W, Ag or Au or a variety of.
It is pseudo- grid structure as example using the gate structure in the present embodiment.Form the technique step of the gate structure
It suddenly include: that pseudo- grid film is formed on the isolation structure 201, the puppet grid film covers the fin (not indicating)；To the puppet
Grid film carries out flatening process；Graph layer (not shown) is formed in the pseudo- grid film surface, the graph layer defines to be formed
Gate structure figure；Using the graph layer as exposure mask, the graphical pseudo- grid film, in the 210 surface shape of the first fin
Second grid structure 221 is formed on 220 surface of the second fin at first grid structure 211, and also.
It should be noted that being formed after the first grid structure 211 and second grid structure 221, the manufacturer
Method further include: the first side wall of first area (not shown) is formed in 211 side wall of first grid structure, in the second grid
221 side wall of structure forms the first side wall of second area (not shown).
The material of first side wall of first area and the first side wall of second area can be silica, silicon nitride, carbonization
Silicon, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides, first side wall of first area and the secondth area
The first side wall of domain can be single layer structure or laminated construction.In the present embodiment, first side wall of first area and second area
First side wall is single layer structure, and the material of first side wall of first area and the first side wall of second area is silicon nitride.
It is the structural schematic diagram based on Fig. 4 with reference to Fig. 8 and Fig. 9, Fig. 8, wherein Fig. 8 only illustrates that a fin, Fig. 9 are
Fig. 8 along the direction DD1 the schematic diagram of the section structure, with the gate structure (not indicating) be exposure mask, to the fin first area
The side of (not indicating) carries out the first lightly doped technique 231, forms first and ion area (not shown) is lightly doped, described first gently mixes
The Doped ions of general labourer's skill 231 are the first ion.
Specifically, the step of ion area is lightly doped in formation described first includes: on the substrate 200 of the second area II
The first graph layer 310 is formed, first graph layer 310 also covers the second grid structure 221；With first graph layer
310 and first area the first side wall (not shown) be exposure mask, the side of first fin first area (not indicating) is carried out
First lightly doped technique 231.
In the present embodiment, after ion area is lightly doped in formation described first, reservation first graph layer 310, described first
Mask layer of the graph layer 310 also as subsequent doping process.
In the present embodiment, I substrate 200 of first area is used to form N-type device, correspondingly, first ion is N
Type ion.
In the present embodiment, first ion is As ion.Specifically, the parameter packet of first lightly doped technique 231
Include: implant angle is 7 degree to 20 degree.
It should be noted that the ion energy of injection should not be too large, and it is also unsuitable too small, if the ion energy mistake of injection
Small, ion is difficult in the predetermined depth for being injected into first fin first area；If the ion energy of injection is excessive, it is easy
Deteriorate short-channel effect, is reduced so as to cause the electric property of device.For this purpose, in the present embodiment, first lightly doped technique
The ion energy of 231 injections is 1Kev to 8Kev.
It should be noted that the ion dose of injection should not be too large, it is also unsuitable too small.If the ion dose mistake of injection
It is small, it is easy to cause the resistance value of first fin 210 to increase；If the ion dose of injection is excessive, it is easy to deteriorate short channel effect
It answers, is reduced so as to cause the electric property of device.For this purpose, in the present embodiment, the ion of the injection of the first lightly doped technique 231
Dosage is 1E14 to 8E14 atom per square centimeter.
In conjunction with reference Fig. 8 and Figure 10, Figure 10 is the structural schematic diagram based on Fig. 9, is with the gate structure (not indicating)
Exposure mask carries out the second lightly doped technique 232 to the other side of the fin first area (not indicating), formed second be lightly doped from
Sub-district (not shown), the Doped ions of second lightly doped technique are the second ion, wherein second ionic type and institute
State that the first ionic type is identical, the atomic mass of second ion is less than the atomic mass of first ion.
Specifically, forming for second the step of ion area is lightly doped includes: with first graph layer 310 and first area the
One side wall (not shown) is exposure mask, carries out the second lightly doped technique to the other side of first fin first area (not indicating)
232；Remove first graph layer 310.
In the present embodiment, first graph layer 310 is photoresist layer.Using wet process remove photoresist or cineration technics removal described in
First graph layer 310.
In the present embodiment, I substrate 200 of first area is used to form N-type device, and first ion is N-type ion,
Correspondingly, second ion is N-type ion.
In the present embodiment, second ion is P ion.Specifically, the parameter packet of second lightly doped technique 232
Include: implant angle is 7 degree to 20 degree.
It should be noted that the ion energy of injection should not be too large, and it is also unsuitable too small, if the ion energy mistake of injection
Small, ion is difficult in the predetermined depth for being injected into first fin first area；If the ion energy of injection is excessive, it is easy
Deteriorate short-channel effect, is reduced so as to cause the electric property of device.For this purpose, in the present embodiment, second lightly doped technique
The ion energy of 232 injections is 1Kev to 6Kev.
It should also be noted that, the ion dose of injection should not be too large, it is also unsuitable too small.If the ion dose mistake of injection
It is small, it is easy to cause the resistance value of first fin 210 to increase；If the ion dose of injection is excessive, it is easy to deteriorate short channel effect
It answers, is reduced so as to cause the electric property of device.For this purpose, in the present embodiment, the ion of the injection of the second lightly doped technique 232
Dosage is 1E14 to 5E14 atom per square centimeter.
It is the partial structurtes sectional view of first area I in Fig. 8 in conjunction with reference Figure 11, Figure 11.In the present embodiment, described first
The Doped ions of lightly doped technique 231 are As ion, and the Doped ions of second lightly doped technique 232 are P ion；
It should be noted that on the one hand, since the atomic mass of As ion is heavier, first fin first area is (not
Mark) side by As ion bombardment after, material is converted to amorphous state by monocrystalline state, i.e. side is converted to amorphous layer 215
(as shown in figure 11), but the other side is since by As ion bombardment, material is not still monocrystalline state；Therefore in subsequent annealing process
In, more single phase material can not be provided by part the first fin first area of As ion bombardment, so as to described
First fin first area is repaired, and amorphous layer 215 is converted to monocrystalline state layer again, to improve first fin
210 quality；On the other hand, since the atomic mass of P ion is lighter, by only to the another of first fin first area
Side carry out P ion doping, can to avoid excessive lighter weight P ion horizontal proliferation to device channel region, so as to improve
The short-channel effect of device.
Therefore, by the combination of As ion and P ion, the quality of first fin 210 had not only been improved, but also has improved device
The short-channel effect of part, so that the electric property of semiconductor devices be made to be optimized.
It should also be noted that, first lightly doped technique 231 (as shown in Figure 9) and the second lightly doped technique 232 are (such as
Shown in Figure 10) after, the manufacturing method further include: third is carried out to second fin first area (not indicating), work is lightly doped
Skill (not shown) forms third and ion area (not shown) is lightly doped, and Doped ions are third ion.
In the present embodiment, II substrate 200 of second area is used to form P-type device, correspondingly, the third ion is
P-type ion.Specifically, it includes boron ion that the parameter of third lightly doped technique, which includes: the ion of injection, and the ion energy of injection is
2Kev to 8Kev, the ion dose of injection are 8E13 to 5E14 atom per square centimeter, and implant angle is 7 degree to 20 degree.
It should also be noted that, first carrying out the first lightly doped technique to first fin first area in the present embodiment
231 and second lightly doped technique 232, then third lightly doped technique is carried out to second fin first area；In another implementation
In example, third lightly doped technique first can also be carried out to second fin first area, then to firstth area of the first fin
Domain carries out the first lightly doped technique and the second lightly doped technique.
With reference to Figure 12, the first lightly doped technique 231 (as shown in Figure 9) and the second lightly doped technique 232 (as shown in Figure 10)
Afterwards, annealing process 400 is carried out to the substrate 200.
In the present embodiment, includes: to the step of substrate 200 progress annealing process 400 while gently mixing described first
Heteroion area (not shown), second are lightly doped ion area (not shown) and third is lightly doped ion area (not shown) and carries out lehr attendant
Skill 400, with active ions.
After carrying out the annealing process 400, first ion, the second ion and third ion are activated, and
The annealing process 400 can also repair the lattice damage in the fin first area, and by firstth area of the first fin
Amorphous material in domain is converted to single phase material, that is to say, that passes through after the annealing process 400, the amorphous state
215 (as shown in figure 11) of layer are converted to monocrystalline state layer.
In the present embodiment, the annealing process 400 is spike annealing process.It in other embodiments, can also be using sharp
Photo-annealing or rapid thermal anneal process carry out the annealing process.
It should be noted that in order to activate first ion, the second ion and third ion, and promote first fin
While amorphous material in portion first area is converted to single phase material, avoid to first ion, the second ion and
Third ion and first lightly doped technique 231 (as shown in Figure 9), the second lightly doped technique 232 (as shown in Figure 10) and
The ion distribution injected in ion doping technique before third lightly doped technique causes adverse effect, the annealing process 400
Technological parameter need to control in the reasonable scope.
Specifically, it is 750 degrees Celsius to 1000 Celsius that the technological parameter of the spike annealing process, which includes: annealing temperature,
Degree, pressure are a standard atmospheric pressure, and reaction gas is nitrogen, and the gas flow of nitrogen is that 5 standards per minute rise to 40 every point
Clock standard liter.
In conjunction with reference Figure 13, it should be noted that after carrying out annealing process 400 (as shown in figure 12) to the substrate 200,
The manufacturing method further include: source and drain doping area (not shown) is formed in the fin of the gate structure two sides.
In the present embodiment, I substrate 200 of first area is used to form N-type device, II substrate 200 of second area
It is used to form P-type device.
Correspondingly, the source and drain doping area includes: in the first fin 210 of 211 two sides of first grid structure
The first source and drain doping area (not shown)；The second source and drain in the second fin 220 of 221 two sides of second grid structure
Doped region (not shown).Wherein, the ionic type in first source and drain doping area be N-type, second source and drain doping area from
Subtype is p-type.
In another embodiment, the first area substrate is used to form P-type device, and the second area substrate is used for shape
At N-type device, correspondingly, the ionic type in first source and drain doping area is p-type, the ionic species in second source and drain doping area
Type is N-type.In another embodiment, the first area substrate and second area substrate are used to form N-type device, accordingly
, the ionic type in first source and drain doping area and the second source and drain doping area is N-type.
In the present embodiment, the step of forming the source and drain doping area includes: the of 211 two sides of first grid structure
The first stressor layers 212 are formed in one fin 210, form second in the second fin 220 of 221 two sides of second grid structure
Stressor layers 222；The first source and drain doping area is formed in first stressor layers 212；Is formed in second stressor layers 222
Two source and drain doping areas.
In the present embodiment, auto-dope processing in situ is used to be formed during forming the first stressor layers 212 described
First source and drain doping area；Described second is formed using auto-dope processing in situ during forming the second stressor layers 222
Source and drain doping area.
In other embodiments, can also after forming first stressor layers 212, to first stressor layers 212 into
Row heavy doping processing, to form first source and drain doping area；After forming second stressor layers 222, answer described second
Power layer 222 carries out heavy doping processing, to form second source and drain doping area.
It should also be noted that, forming the source after carrying out annealing process 400 (as shown in figure 12) to the substrate 200
Before leaking doped region, the manufacturing method further include: form the firstth area on first area the first side wall (not shown) surface
Domain the second side wall (not shown)；The second side wall of second area (figure is formed on second area the first side wall (not shown) surface
Do not show).
The material of second side wall of first area and the second side wall of second area can be silica, silicon nitride, carbonization
Silicon, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides, second side wall of first area and the secondth area
The second side wall of domain can be single layer structure or laminated construction.In the present embodiment, second side wall of first area and second area
Second side wall is single layer structure, and the material of second side wall of first area and the second side wall of second area is silicon nitride
The present embodiment carries out the first lightly doped technique 231 (such as to the side of first fin first area (not indicating)
Shown in Fig. 9), the Doped ions of first lightly doped technique 231 are the first ion, to the other side of the fin first area
The second lightly doped technique 232 (as shown in Figure 10) is carried out, the Doped ions of the second lightly doped technique 232 are the second ion, wherein
Second ionic type is identical as first ionic type, and the atomic mass of second ion is less than first ion
Atomic mass.Not only it had avoided first fin first area and has been difficult to the problem of repairing, but also improved the short channel effect of device
It answers, so that the electric property of semiconductor devices be made to be optimized.
3 are continued to refer to figure 1, the present invention also provides a kind of semiconductor structures, comprising:
Substrate 200, the substrate 200 have fin (not indicating)；
Isolation structure 201, on the substrate 200 between the fin, wherein protruding from the fin of the isolation structure 201
Portion (does not indicate) as fin first area；
Gate structure (does not indicate), across the atop part surface and side of the fin and the covering fin first area
Wall surface；
First is lightly doped ion area (not shown), the side in the fin first area, and described first is lightly doped
The Doped ions in ion area are the first ion；
Second is lightly doped ion area (not shown), and the other side in the fin first area, described second gently mixes
The Doped ions in heteroion area are the second ion, wherein second ionic type is identical as first ionic type, described
The atomic mass of second ion is less than the atomic mass of first ion.
In the present embodiment, the substrate 200 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be on the silicon substrates or insulator on insulator
Germanium substrate.
In the present embodiment, the substrate 200 includes first area I and second area II.Correspondingly, being located at firstth area
Fin on I substrate 200 of domain is the first fin 210, and the fin on II substrate 200 of second area is the second fin
220。
The material of first fin 210 and second fin 220 is identical as the material of the substrate 200.This implementation
In example, the material of first fin 210 and the second fin 220 is silicon.In other embodiments, first fin and described
The material of two fins can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the semiconductor structure of the first area I is N-type device, the semiconductor of the second area II
Structure is P-type device.In another embodiment, the semiconductor structure of the first area is P-type device, the second area
Semiconductor structure is N-type device.In other embodiments, the semiconductor structure of the first area and second area is N-type
Device.
Isolation structure of the isolation structure 201 as semiconductor structure, for playing buffer action to adjacent devices.This
In embodiment, the material of the isolation structure 201 is silica.In other embodiments, the material of the isolation structure 201 is also
It can be silicon nitride, silicon oxynitride or carbon silicon oxynitride.
It should be noted that the isolation structure 201 is shallow groove isolation layer, but is not limited to shallow trench in the present embodiment
Separation layer.
Correspondingly, the first fin 210 for protruding from I isolation structure 201 of first area is the first fin first area
(not indicating)；The second fin 220 for protruding from II isolation structure 201 of second area is that the second fin first area (is not marked
Show).
Correspondingly, described first is lightly doped the side that ion area is located in first fin first area；Described second
The other side that ion area is located in first fin first area is lightly doped.
In the present embodiment, the semiconductor structure of the first area I is N-type device, correspondingly, first ion and the
Two ions are N-type ion.Specifically, first ion is As ion, and second ion is P ion.
It should be noted that described first be lightly doped ion area and second ion area is lightly doped ion concentration should not mistake
Height, it is also unsuitable too low.If ion concentration is too low, the resistance value of first fin 210 is easy to cause to increase；If ion concentration
It is excessively high, it is easy to deteriorate short-channel effect, be reduced so as to cause the electric property of device.For this purpose, described first is light in the present embodiment
The ion concentration in Doped ions area is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter；Described second be lightly doped from
The ion concentration of sub-district is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.
It should be noted that the semiconductor structure further include: be located in second fin first area (not indicating)
Third be lightly doped ion area (not shown), Doped ions are third ion.
In the present embodiment, the semiconductor structure of the second area II is P-type device, correspondingly, the third ion is P
Type ion.Specifically, the third ion includes boron ion, and the ion concentration that ion area is lightly doped in the third is 8E13 atom
It is per cubic centimeter to 5E14 atoms per cubic centimeter.
In the present embodiment, the gate structure includes the first grid across first fin first area (not indicating)
Structure 211, the first grid structure 211 cover atop part surface and the sidewall surfaces of first fin first area；
It further include the second grid structure 221 across second fin first area (not indicating), the second grid structure 221 is covered
Cover atop part surface and the sidewall surfaces of second fin first area.
The gate structure is metal gate structure.The gate structure include gate dielectric layer and be located at the gate medium
The gate electrode layer of layer surface, wherein the material of gate dielectric layer is silica or high-k gate dielectric material, the material of the gate electrode layer
Material is polysilicon or metal material, and the metal material includes Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag or Au
One of or it is a variety of.In the present embodiment, the metal material is W.
It should be noted the semiconductor structure further include: the source in the fin of the gate structure two sides
Leak doped region (not shown).
Specifically, the source and drain doping area includes: in the first fin 210 of 211 two sides of first grid structure
The first source and drain doping area (not shown)；The second source and drain in the second fin 220 of 221 two sides of second grid structure
Doped region (not shown).Wherein, the ionic type in first source and drain doping area be N-type, second source and drain doping area from
Subtype is p-type.
In another embodiment, the semiconductor structure of the first area is P-type device, the semiconductor of the second area
Structure be N-type device, correspondingly, the ionic type in first source and drain doping area be p-type, second source and drain doping area from
Subtype is N-type.In another embodiment, the semiconductor structure of the first area and second area is N-type device, accordingly
, the ionic type in first source and drain doping area and the second source and drain doping area is N-type.
In the present embodiment, the semiconductor structure further include: be located at 211 first fin of two sides of first grid structure
The first stressor layers 212 in 210, the second stressor layers 222 in 221 second fin of two sides 220 of second grid structure；
Wherein, first source and drain doping area is located in first stressor layers 212, and second source and drain doping area is located at described second
In stressor layers 222.
Described first is lightly doped the side that ion area (not shown) is located in first fin first area (not indicating),
Described first Doped ions that ion is lightly doped are the first ion；Described second, which is lightly doped ion area (not shown), is located at described the
The other side in one fin first area, the described second Doped ions that ion is lightly doped are the second ion；Wherein, described second
Ionic type is identical as first ionic type, and the atomic mass of second ion is less than the atom matter of first ion
Amount.On the one hand avoid first fin first area other side from being lightly doped in the forming process in ion area first, because by
First ion bombardment of heavier mass and amorphous state is converted to by monocrystalline state, to make not by the part fin of As ion bombardment
One region provides more single phase materials in 210 repair process of the first fin, and amorphous material is converted to monocrystalline again
State material, and then improve the quality of first fin 210；It on the other hand, can be lateral to avoid the ion of excessive lighter weight
Device channel region is diffused to, so as to improve the short-channel effect of device.Therefore, pass through the knot of the first ion and the second ion
It closes, the quality of first fin 210 had not only been improved, but also improve the short-channel effect of device, to make semiconductor devices
Electric property is optimized.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of manufacturing method of semiconductor structure characterized by comprising
Substrate is provided, the substrate has fin；
Isolation structure is formed on substrate between the fin, wherein protruding from the fin of the isolation structure as fin
One region；
It is developed across the gate structure of the fin, the gate structure covers the atop part surface of the fin first area
And sidewall surfaces；
Using the gate structure as exposure mask, the first lightly doped technique is carried out to the side of the fin first area, forms first
Ion area is lightly doped, the Doped ions of first lightly doped technique are the first ion；
Using the gate structure as exposure mask, the second lightly doped technique is carried out to the other side of the fin first area, forms the
The second light industry bureau Doped ions area, the Doped ions of second lightly doped technique are the second ion, wherein second ionic type with
First ionic type is identical, and the atomic mass of second ion is less than the atomic mass of first ion；
After first lightly doped technique and the second lightly doped technique, annealing process is carried out to the substrate.
2. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the substrate is used to form N-type device
Part, first ion and the second ion are N-type ion.
3. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that first ion is As ion,
Second ion is P ion.
4. the manufacturing method of semiconductor structure as claimed in claim 3, which is characterized in that the ginseng of first lightly doped technique
Number includes: that the ion energy of injection is 1Kev to 8Kev, and the ion dose of injection is 1E14 to 8E14 atom per square centimeter, is infused
Entering angle is 7 degree to 20 degree.
5. the manufacturing method of semiconductor structure as claimed in claim 3, which is characterized in that the ginseng of second lightly doped technique
Number includes: that the ion energy of injection is 1Kev to 6Kev, and the ion dose of injection is 1E14 to 5E14 atom per square centimeter, is infused
Entering angle is 7 degree to 20 degree.
6. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the annealing process moves back for laser
Fire, spike annealing or rapid thermal anneal process.
7. the manufacturing method of semiconductor structure as claimed in claim 6, which is characterized in that the annealing process is spike annealing
Technique；
The technological parameter of the annealing process includes: that annealing temperature is 900 degrees Celsius to 1050 degrees Celsius, and pressure is a standard
Atmospheric pressure, reaction gas are nitrogen, and the gas flow of nitrogen is that 5 standards per minute rise to 40 standard liters per minute.
8. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that carry out annealing process to the substrate
Afterwards, the manufacturing method further include: source and drain doping area is formed in the fin of the gate structure two sides.
9. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the substrate include first area and
Second area, the first area substrate are used to form N-type device, and the second area substrate is used to form P-type device；
Fin on the first area substrate is the first fin, and the fin on the second area substrate is second
Fin；
The first fin for protruding from the first area isolation structure is the first fin first area, protrudes from the second area
Second fin of isolation structure is the second fin first area；
In the step of carrying out the first lightly doped technique to the side of the fin first area, to first fin first area
Side carry out the first lightly doped technique；
In the step of carrying out the second lightly doped technique to the other side of the fin first area, to firstth area of the first fin
The other side in domain carries out the second lightly doped technique；
Before carrying out annealing process to the substrate, the manufacturing method further include: second fin first area is carried out
Third lightly doped technique forms third and ion area is lightly doped.
10. the manufacturing method of semiconductor structure as claimed in claim 9, which is characterized in that the third lightly doped technique
Parameter includes: that the ion of injection includes boron ion, and the ion energy of injection is 2Kev to 8Kev, and the ion dose of injection is 8E13
To 5E14 atom per square centimeter, implant angle is 7 degree to 20 degree.
11. the manufacturing method of semiconductor structure as claimed in claim 9, which is characterized in that carry out lehr attendant to the substrate
The step of skill include: and meanwhile to described first be lightly doped ion area, second be lightly doped ion area and third be lightly doped ion area into
Row annealing process, with active ions.
12. a kind of semiconductor structure characterized by comprising
Substrate, the substrate have fin；
Isolation structure, on the substrate between the fin, wherein protruding from the fin of the isolation structure as fin
One region；
Gate structure, atop part surface and sidewall surfaces across the fin and the covering fin first area；
First is lightly doped ion area, the side in the fin first area, and described first is lightly doped the doping in ion area
Ion is the first ion；
Second is lightly doped ion area, the other side in the fin first area, and described second is lightly doped mixing for ion area
Heteroion is the second ion, wherein second ionic type is identical as first ionic type, the original of second ion
Protonatomic mass is less than the atomic mass of first ion.
13. semiconductor structure as claimed in claim 12, which is characterized in that the semiconductor structure is N-type device, described the
One ion and the second ion are N-type ion.
14. semiconductor structure as claimed in claim 12, which is characterized in that first ion be As ion, described second
Ion is P ion.
15. semiconductor structure as claimed in claim 14, which is characterized in that described first is lightly doped the ion concentration in ion area
For 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.
16. semiconductor structure as claimed in claim 14, which is characterized in that described second is lightly doped the ion concentration in ion area
For 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.
17. semiconductor structure as claimed in claim 12, which is characterized in that the semiconductor structure further include: source and drain doping
Area, in the fin of the gate structure two sides.
18. semiconductor structure as claimed in claim 12, which is characterized in that the substrate includes first area and the secondth area
Domain, the semiconductor structure of the first area are N-type device, and the semiconductor structure of the second area is P-type device；
Fin on the first area substrate is the first fin, and the fin on the second area substrate is second
Fin；
The first fin for protruding from the first area isolation structure is the first fin first area, protrudes from the second area
Second fin of isolation structure is the second fin first area；
Described first is lightly doped the side that ion area is located in first fin first area；
Described second is lightly doped the other side that ion area is located in first fin first area；
The semiconductor structure further include: ion area is lightly doped in the third in second fin first area.
19. semiconductor structure as claimed in claim 18, which is characterized in that the Doped ions in ion area are lightly doped in the third
Including boron ion, it is 8E13 atoms per cubic centimeter to every cube of 5E14 atom that the ion concentration in ion area, which is lightly doped, in the third
Centimetre.
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