CN103681507A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN103681507A
CN103681507A CN201210356107.0A CN201210356107A CN103681507A CN 103681507 A CN103681507 A CN 103681507A CN 201210356107 A CN201210356107 A CN 201210356107A CN 103681507 A CN103681507 A CN 103681507A
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fin
metal material
material layer
function metal
work function
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CN103681507B (en
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张海洋
王冬江
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate which includes at least a first fin and a second fin; depositing a high-work-function metal material layer on the substrate so as to cover the first fin and the second fin; forming a low-work-function metal material layer on the second fin and the high-work-function layer on the two sides of the second fin so as to form a work-function metal material lamination layer on the second fin; depositing a gate pattern mask layer and etching the low-work-function metal material layer and the high-work-function metal material layer so as to form gate structures on the first fin and the second fin. In the semiconductor device manufactured through the manufacturing method, a threshold voltage (Vth) is controllable and it is junction-less between the two metal gates obtained through the manufacturing method and the dual metal gates are independent dual gates FinFET so that the threshold voltage (Vth) of the semiconductor device is more stable and performance of an SRAM unit is enhanced.

Description

A kind of semiconductor device and preparation method thereof
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
To be mainly size by constantly dwindling integrated circuit (IC)-components realize with the speed that improves it in the raising of performance of integrated circuits.At present, because semi-conductor industry in pursuing high device density, high-performance and low cost has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to 22nm or when following, from manufacturing and the challenge of design aspect has caused three dimensional design as the development of FinFET (FinFET).
With respect to existing planar transistor, described FinFET device is controlled and reduced the aspects such as shallow channel effect at raceway groove has more superior performance; Planar gate is arranged at described raceway groove top, and in gate loop described in FinFET around described fin setting, therefore can control static from three faces, the performance aspect electrostatic control is also more outstanding.In FinFET, the length of grid obtains by measuring the parallel length of fin, the width of described grid is twice and the wide sum of fin of described fin height, the limitation in height of fin the electric current of device and the electric capacity of grid, the width of fin can affect the threshold voltage of device and short channel is controlled.
Threshold voltage in currently available technology (Vth) controlled, independently bigrid FinFET's is introduced in semiconductor device preparation, be used for the stability of the sram cell performance that strengthens, in order further to reduce threshold voltage (Vth), to strengthen the current driving ability when compared with low supply voltage, can select the FinFET of double-metal grid to realize described effect, Metal Phase counterdiffusion technology (Metal inter-diffusion technology) becomes the key of preparing double-metal grid FinFET.
The cylindrical transistor without node (junction-less) has been proposed at present, preparation technology has been simplified in described transistorized preparation greatly, in this process, can omit the step that the ring of light/expansion and source/leakage is injected, having avoided forming described gate stack carries out activating the step of annealing after Implantation, thereby reduce, produce heat budget, more possibility is provided simultaneously in the selection of gate metal and gate dielectric layer material.
The method of preparing at present the FinFET of double-metal grid is in Semiconductor substrate, to form fin, then deposit metallic material layer and hard mask layer on described substrate, then patterning, to form, be positioned at all around gate on described fin, two grid structures in double-metal grid interconnect, have node simultaneously, have identical threshold voltage (Vth), the stability of threshold voltage in the device that makes to prepare (Vth) is not ideal enough.
Therefore, although there is the transistor without node (junction-less) in prior art, but also do not have method preparation not contain the FinFET of the double-metal grid of node, need prior art to do further improvement simultaneously, to make the threshold voltage (Vth) of semiconductor device more stable, make two grids in described double-metal grid there is different threshold voltage (Vth) simultaneously, and mutually more independent.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The preparation method who the invention provides a kind of semiconductor device, comprising:
Semiconductor substrate is provided, on described substrate, at least comprises the first fin and the second fin;
On described substrate, deposit high work function metal material layer, to cover described the first fin and described the second fin;
On the described high work function metal material layer of described the second fin and both sides, form low work function metal material layer, to form work function metal material laminate on described the second fin;
Deposition gate pattern mask layer, low work function metal material layer and described high work function metal material layer described in etching, to form grid structure on described the first fin and described the second fin.
As preferably, form after described grid structure, carry out annealing steps, so that the low work function metal in the described low work function metal material layer on described the second fin diffuses in described high work function metal material layer.
As preferably, form after described grid structure, also comprise the step of deposition interlayer dielectric layer planarization.
As preferably, when described interlayer dielectric layer is removed in described planarization, remove remaining described high work function metal material layer and described low work function metal material layer on described fin, to form independently bigrid without junction structure.
As preferably, low work function metal material layer and described high work function metal material layer described in dry etching, to form grid structure.
As preferably, described dry etching is selected Cl 2and O 2combination, or CHF 3and O 2combination.
As preferably, described method is further comprising the steps of:
Before the high work function metal material layer of deposition, on described the first fin region and described the second fin region, carry out dissimilar doping.
As preferably, described the first fin both sides doping P type dopant, to form PMOS.
As preferably, described the second fin both sides doped N-type dopant, to form NMOS.
As preferably, described high work function metal material layer is Mo.
As preferably, described low work function metal material layer is Ta.
As preferably, on described substrate, deposit after high work function metal material layer, in described the first fin both sides, carry out same type or dissimilar Implantation, to form identical or different threshold voltages.
As preferably, on described the second fin, deposit after low work function metal material layer, in described the second fin both sides, carry out same type or dissimilar Implantation, to form identical or different threshold voltages.
The present invention also provides a kind of and has had independent double-metal grid without the semiconductor device of junction structure, and it comprises:
Semiconductor substrate;
Be positioned at the first fin and the second fin in described Semiconductor substrate;
Uniform doped with dissimilar dopant in described the first fin both sides and described the second fin both sides substrate;
Be positioned at the high work function metal material layer of described the first fin both sides, to form independently bigrid in described the first fin region without junction structure,
Be positioned at high work function metal material layer and the low work function metal material layer of described the second fin both sides, to form independently bigrid in described the second fin region without junction structure.
As preferably, described high work function metal material layer is Mo.
As preferably, described low work function metal material layer is Ta.
As preferably, the dopant of described the second fin both sides is N-type dopant, to form NMOS.
As preferably, the dopant of described the second fin both sides is P type dopant, to form PMOS.
As preferably, between the high work function metal material layer on described the first fin and the high work function metal material layer on described the second fin, mutually isolate.
(Vth) is controlled for threshold voltage in the device that the method for the invention prepares, and there is no node between the double-metal grid for preparing of described method, for bigrid FinFET independently, make the threshold voltage (Vth) of semiconductor device more stable, strengthened the performance of sram cell.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1-4 for forming the preparation flow schematic diagram of metal material layer on described fin in the present invention;
Fig. 5 is the vertical view in PMOS region in Fig. 4;
Fig. 6 is the vertical view in territory, nmos area in Fig. 4;
Fig. 7 is for containing the process chart of the semiconductor device of highly controlled fin in preparation the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that the preparation method of semiconductor device of the present invention to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Preparation method below in conjunction with Fig. 1-6 pair semiconductor device containing highly controlled fin of the present invention is described further:
As shown in Figure 1, provide Semiconductor substrate, on described substrate, at least comprise the first fin and the second fin;
Particularly, described Semiconductor substrate 101 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In Semiconductor substrate, can be defined active area.On this active area, can also include other active device, in order to simplify accompanying drawing, shown in do not indicate in figure.
Described Semiconductor substrate is divided into territory, nmos area and PMOS region in the present invention.
Then in described Semiconductor substrate, form fin, at least in described PMOS region and territory, nmos area, form respectively the first fin 20 and the second fin 10.The formation method of described the first fin and the second fin can be selected ability common method, for example in the present invention can be on described substrate epitaxial growth semiconductor material layer, then on described semiconductor material layer, form fin pattern mask layer, the photoresist mask layer that for example comprises fin CD, pattern, then take described fin pattern mask layer as semiconductor material layer described in mask etch, to described substrate, form the first fin 20 and the second fin 10, then remove described mask layer.
With reference to Fig. 2, on described substrate, deposit high work function metal material layer, to cover described the first fin and described the second fin;
Particularly, after forming described the first fin 20 and the second fin 10, on described substrate, carry out uniformly ion doping, for example on substrate, N-type doping is carried out in territory, nmos area, to form N-type transistor, carries out the doping of P type in PMOS region, to form P transistor npn npn, described N-type dopant comprises P, As, Sb, and described P type dopant comprises B and BF and In, and described doping method can be following any method:
First method is Implantation (Nitrogen implantation), and the ion energy of described injection is 1kev-10kev, and the ion dose of injection is 5 * 10 14-5 * 10 16atom/cm 2.Be preferably in the present invention below 400 ℃, and can comparatively independently control Impurity Distribution (ion energy) and impurity concentration (ion current density and injection length) by described method, the method more easily obtains the doping of high concentration, and be anisotropy doping, independently controlling depth and concentration.
The present invention also can select plasma doping (plasma doping), when adopting the method, generally selects higher temperature, generally selects in the present invention 900-1200 ℃, and described method is isotropism.
Then on described substrate, deposit high work function metal material layer, preferred Mo in the present invention, described deposition process can be selected a kind of in sputter (Sputtering), physical vapor deposition (PVD) method, and its thickness can be 40-100nm.
Then in the both sides of fin described in described PMOS region, carry out Implantation, wherein said injection ionic type can be identical or different, to form identical or different threshold voltages in described fin both sides, preferably carry out in the present invention dissimilar Implantation, form different threshold voltages, the ion of wherein said injection can select this area to commonly use kind, at this, will not enumerate.
Then on described the second fin and both sides, deposit low work function metal material layer, to cover described the second fin, and form work function metal material laminate on described the second fin;
Particularly, at the low work function metal material layer of the upper deposition of described high work function metal material layer (Mo material layer), preferred Ta in the present invention, then on described the second fin region, form mask layer, etching is removed and is positioned at the described low work function metal material layer on the first fin region, then remove mask layer, only on described the second fin region, form low work function metal material layer, in conjunction with the Mo material layer that is positioned at below, form work function metal material laminate, wherein said Ta selects physical vapor deposition (PVD) method to form, and its thickness can be 20-50nm.In this step, the high work function metal material layer on the high work function metal material layer on described the first fin region and described the second fin region is formed to isolation, to form separately independently grid structure simultaneously.
Then in the both sides of the second fin described in territory, described nmos area, carry out Implantation, wherein said injection ionic type can be identical or different, to form identical or different threshold voltages in described fin both sides, preferably carry out in the present invention dissimilar Implantation, form different threshold voltages, the ion of wherein said injection can select this area to commonly use kind, at this, will not enumerate.
With reference to Fig. 4, on described the first fin and described the second fin, form grid structure;
Particularly, can first on described metal material layer, form grid structure patterned mask layer, the described grid structure patterned mask layer of take is metal material layer described in mask etch, comprises Mo and Ta material layer, forms grid structure.
As preferably, described in etching, selecting Cl during metal material layer 2and O 2combination, or CHF 3and O 2combination, wherein gas flow is 10-400sccm, described etching pressure is 20-300mTorr, etching period is 5-120s, is preferably 5-60s, more preferably 5-30s.
After forming described grid structure, also comprise annealing steps; so that the described low work function metal material layer on described the second fin diffuses in described high work function metal material layer; wherein said annealing steps is generally that described substrate is placed under the protection of high vacuum or high-purity gas; being heated to certain temperature heat-treats; at high-purity gas of the present invention, be preferably nitrogen or inert gas; the temperature of described thermal anneal step is 900-1200 ℃, and the described thermal anneal step time is 1-200s.
As further preferred, can select rapid thermal annealing in the present invention, particularly, can select a kind of in following several mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent wideband light source (as halogen lamp, arc lamp, graphite heating) short annealing etc.Those skilled in the art can select as required, are also not limited to examples cited.
After executing annealing steps, can also further comprise the step that deposits interlayer dielectric layer, described interlayer dielectric layer can be used such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc. in an embodiment of the present invention.Or, also can use film having formed SiCN film etc. on fluorocarbon (CF).It is main component that fluorocarbon be take fluorine (F) and carbon (C).Fluorocarbon also can be used the material with noncrystal (amorphism) structure.Interlayer dielectric layer can also be used such as Porous structures such as carbon doped silicon oxide (SiOC).
Then carry out planarisation step, in this step, remove remaining described high work function metal material layer and described low work function metal material layer on described the first fin and the second fin, to form independently bigrid without junction structure (Dual gate junctionless) simultaneously.
Fig. 5 be the bigrid that forms in described PMOS without the vertical view of junction structure, in the both sides of described the first fin, formed and there is certain thickness Mo material layer.
Fig. 6 be the bigrid that forms in described NMOS without the vertical view of junction structure, in the both sides of described the first fin, formed and there is certain thickness work function metal material laminate.
The present invention also provides a kind of and has had independent double-metal grid without the semiconductor device of junction structure, and it comprises:
Semiconductor substrate;
Be positioned at the first fin and the second fin in described Semiconductor substrate;
Uniform doped with dissimilar dopant in described the first fin both sides and described the second fin both sides substrate;
Be positioned at the high work function metal material layer of described the first fin both sides, to form independently bigrid in described the first fin region without junction structure,
Be positioned at high work function metal material layer and the low work function metal material layer of described the second fin both sides, to form independently bigrid in described the second fin region without junction structure.
(Vth) is controlled for threshold voltage in the device that the method for the invention prepares, and there is no node (junction) between the double-metal grid for preparing of described method, for bigrid FinFET independently, make the threshold voltage (Vth) of semiconductor device more stable, strengthened the performance of sram cell.
Fig. 7 is the process chart that preparation the present invention prepares semiconductor device, comprises the following steps:
Step 201 provides Semiconductor substrate, at least comprises the first fin and the second fin on described substrate;
Step 202 deposits high work function metal material layer on described substrate, to cover described the first fin and described the second fin;
Step 203 forms low work function metal material layer on the described high work function metal material layer of described the second fin and both sides, to form work function metal material laminate on described the second fin;
Step 204 deposition gate pattern mask layer, low work function metal material layer and described high work function metal material layer described in etching, to form grid structure on described the first fin and described the second fin.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims (19)

1. a preparation method for semiconductor device, comprising:
Semiconductor substrate is provided, on described substrate, at least comprises the first fin and the second fin;
On described substrate, deposit high work function metal material layer, to cover described the first fin and described the second fin;
On the described high work function metal material layer of described the second fin and both sides, form low work function metal material layer, to form work function metal material laminate on described the second fin;
Deposition gate pattern mask layer, low work function metal material layer and described high work function metal material layer described in etching, to form grid structure on described the first fin and described the second fin.
2. method according to claim 1, is characterized in that, forms after described grid structure, carries out annealing steps, so that the low work function metal in the described low work function metal material layer on described the second fin diffuses in described high work function metal material layer.
3. method according to claim 1, is characterized in that, forms after described grid structure, also comprises the step of deposition interlayer dielectric layer planarization.
4. method according to claim 3, it is characterized in that, when described interlayer dielectric layer is removed in described planarization, remove remaining described high work function metal material layer and described low work function metal material layer on described fin, to form independently bigrid without junction structure.
5. method according to claim 1, is characterized in that, low work function metal material layer and described high work function metal material layer described in dry etching, to form grid structure.
6. method according to claim 5, is characterized in that, described dry etching is selected Cl 2and O 2combination, or CHF 3and O 2combination.
7. method according to claim 1, is characterized in that, described method is further comprising the steps of:
Before the high work function metal material layer of deposition, on described the first fin region and described the second fin region, carry out dissimilar doping.
8. method according to claim 7, is characterized in that, described the first fin both sides doping P type dopant, to form PMOS.
9. method according to claim 7, is characterized in that, described the second fin both sides doped N-type dopant, to form NMOS.
10. method according to claim 1, is characterized in that, described high work function metal material layer is Mo.
11. methods according to claim 1, is characterized in that, described low work function metal material layer is Ta.
12. methods according to claim 1, is characterized in that, deposit after high work function metal material layer on described substrate, carry out same type or dissimilar Implantation, to form identical or different threshold voltages in described the first fin both sides.
13. methods according to claim 1, it is characterized in that, on described the second fin, deposit after low work function metal material layer, in described the second fin both sides, carry out same type or dissimilar Implantation, to form identical or different threshold voltages.
14. 1 kinds have independent double-metal grid without the semiconductor device of junction structure, and it comprises:
Semiconductor substrate;
Be positioned at the first fin and the second fin in described Semiconductor substrate;
Uniform doped with dissimilar dopant in described the first fin both sides and described the second fin both sides substrate;
Be positioned at the high work function metal material layer of described the first fin both sides, to form independently bigrid in described the first fin region without junction structure,
Be positioned at high work function metal material layer and the low work function metal material layer of described the second fin both sides, to form independently bigrid in described the second fin region without junction structure.
15. semiconductor device according to claim 14, is characterized in that, described high work function metal material layer is Mo.
16. semiconductor device according to claim 14, is characterized in that, described low work function metal material layer is Ta.
17. semiconductor device according to claim 14, is characterized in that, the dopant of described the second fin both sides is N-type dopant, to form NMOS.
18. semiconductor device according to claim 14, is characterized in that, the dopant of described the second fin both sides is P type dopant, to form PMOS.
19. semiconductor device according to claim 14, is characterized in that, isolation mutually between the high work function metal material layer on described the first fin and the high work function metal material layer on described the second fin.
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