CN103681507B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103681507B CN103681507B CN201210356107.0A CN201210356107A CN103681507B CN 103681507 B CN103681507 B CN 103681507B CN 201210356107 A CN201210356107 A CN 201210356107A CN 103681507 B CN103681507 B CN 103681507B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000007769 metal material Substances 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 101
- 239000002019 doping agent Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 11
- 238000002360 preparation method Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 5
- 230000009977 dual effect Effects 0.000 abstract description 3
- 238000003475 lamination Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 15
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000009415 formwork Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 150000002835 noble gases Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate which includes at least a first fin and a second fin; depositing a high-work-function metal material layer on the substrate so as to cover the first fin and the second fin; forming a low-work-function metal material layer on the second fin and the high-work-function layer on the two sides of the second fin so as to form a work-function metal material lamination layer on the second fin; depositing a gate pattern mask layer and etching the low-work-function metal material layer and the high-work-function metal material layer so as to form gate structures on the first fin and the second fin. In the semiconductor device manufactured through the manufacturing method, a threshold voltage (Vth) is controllable and it is junction-less between the two metal gates obtained through the manufacturing method and the dual metal gates are independent dual gates FinFET so that the threshold voltage (Vth) of the semiconductor device is more stable and performance of an SRAM unit is enhanced.
Description
Technical field
A kind of the present invention relates to semiconductor applications, in particular it relates to semiconductor device and preparation method thereof.
Background technology
Improving of performance of integrated circuits mainly improves its speed by the size constantly reducing IC-components
Come to realize.At present, because pursuing high device density, semi-conductor industry has advanced to a nanometer skill in high-performance and low cost
Art process node, particularly when dimensions of semiconductor devices drops to 22nm or following, from manufacture and design aspect challenge
Through result in the development of three dimensional design such as FinFET (finfet).
With respect to existing planar transistor, described finfet device in raceway groove control and reduces the side such as shallow ridges channel effect
Face has more superior performance；Planar gate is arranged above described raceway groove, and grid cincture described in finfet
Described fin setting, therefore can control electrostatic from three faces, the performance in terms of Electrostatic Control is also more prominent.In finfet
The length of grid is obtained by measuring the parallel length of fin, and the width of described grid is twice and the fin of described fin height
Wide sum, the limitation in height of the fin electric capacity of the electric current of device and grid, the width of fin can affect the threshold value electricity of device
Pressure and short channel control.
In currently available technology, controlled, the independent bigrid finfet's of threshold voltage (vth) is introduced into quasiconductor
In device preparation, for the stability of enhanced sram unit performance, in order to reduce threshold voltage (vth) further, to strengthen
Current driving ability when compared with low supply voltage, can select the finfet of double-metal grid to realize described effect, metal
Mutually diffusion technique (metal inter-diffusion technology) becomes the key preparing double-metal grid finfet.
Have been proposed for the transistor of cylinder no node (junction-less) at present, preparing of described transistor is big
Simplify greatly preparation technology, the step that the ring of light/extension and source drain implant can be omitted in this process, it is to avoid formed described
Gate stack activates annealing step after carrying out ion implanting, thus reducing generation heat budget, simultaneously in gate metal and grid
More possibility are provided on the selection of pole dielectric layer material.
The method preparing the finfet of double-metal grid at present is to form fin on a semiconductor substrate, then in described lining
On bottom, deposited metal material layer and hard mask layer, then pattern, to form all around gate being located on described fin, double gold
Two grid structures belonging in grid are connected with each other, and there is node simultaneously, have identical threshold voltage (vth) so that preparing
In the device obtaining, the stability of threshold voltage (vth) is not ideal enough.
Therefore although there is the transistor of no node (junction-less) in prior art, but also there is no method system
The finfet of the standby double-metal grid without node, simultaneously need to further being improved to prior art, to make quasiconductor
The threshold voltage (vth) of device is more stable, makes in described double-metal grid two grids have different threshold value electricity simultaneously
Pressure (vth), and mutually more independent.
Content of the invention
Introduce a series of concept of reduced forms in Summary, this will specific embodiment partly in enter
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme required for protection
Key feature and essential features, more do not mean that the protection domain attempting to determine technical scheme required for protection.
The invention provides a kind of preparation method of semiconductor device, comprising:
Semiconductor substrate is provided, described substrate includes at least the first fin and the second fin；
Deposit high work function metal material layer over the substrate, to cover described first fin and described second fin；
The described high work function metal material layer of described second fin and both sides forms low work function metal material layer, with
Work function metal material laminate is formed on described second fin；
Deposition gate pattern mask layer, etches described low work function metal material layer and described high work function metal material layer, with
Grid structure is formed on described first fin and described second fin.
Preferably, after forming described grid structure, execute annealing steps, so that the described low work(on described second fin
Low work function metal in letter metal material layer diffuses in described high work function metal material layer.
Preferably, after forming described grid structure, also including interlayer dielectric layer the step planarizing.
Preferably, while described planarization removes described interlayer dielectric layer, removing remaining described on described fin
High work function metal material layer and described low work function metal material layer, to form independent bigrid no junction structure.
Preferably, low work function metal material layer described in dry etching and described high work function metal material layer, to form grid
Pole structure.
Preferably, described dry etching selects cl2And o2Combination, or chf3And o2Combination.
Preferably, methods described is further comprising the steps of:
Before deposition high work function metal material layer, described first fin regions and described second fin regions are carried out
Different types of doping.
Preferably, described first fin both sides doped p type dopant, to form pmos.
Preferably, described second fin both sides doping n-type dopant, to form nmos.
Preferably, described high work function metal material layer is mo.
Preferably, described low work function metal material layer is ta.
Preferably, after depositing high work function metal material layer over the substrate, in described first fin both sides execution phase
Same type or different types of ion implanting, to form identical or different threshold voltages.
Preferably, after depositing low work function metal material layer on described second fin, holding in described second fin both sides
Row same type or different types of ion implanting, to form identical or different threshold voltages.
Present invention also offers a kind of semiconductor device with independent double-metal grid no junction structure, comprising:
Semiconductor substrate；
The first fin in described Semiconductor substrate and the second fin；
Uniformly doped with different types of dopant in described first fin both sides and described second fin both sides substrate；
Positioned at the high work function metal material layer of described first fin both sides, independent to be formed in described first fin regions
Bigrid no junction structure,
Positioned at high work function metal material layer and the low work function metal material layer of described second fin both sides, with described second
Fin regions form independent bigrid no junction structure.
Preferably, described high work function metal material layer is mo.
Preferably, described low work function metal material layer is ta.
Preferably, the dopant of described second fin both sides is n-type dopant, to form nmos.
Preferably, the dopant of described second fin both sides is p-type dopant, to form pmos.
Preferably, the high work function metal in high work function metal material layer and described second fin on described first fin
Mutually isolated between material layer.
In the device that the method for the invention prepares, threshold voltage (vth) is controlled, and methods described is prepared into
To double-metal grid between there is no node, be independent bigrid finfet, make the threshold voltage (vth) of semiconductor device more
Plus stable, enhance the performance of sram unit.
Brief description
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of this
Bright embodiment and its description, for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1-4 is the preparation flow schematic diagram forming metal material layer in the present invention on described fin；
Fig. 5 is the top view in pmos region in Fig. 4；
Fig. 6 is the top view in nmos region in Fig. 4；
Fig. 7 is the process chart of the semiconductor device in the preparation present invention containing highly controllable fin.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can one or more of these details and be able to
Implement.In other examples, in order to avoid obscuring with the present invention, some technical characteristics well known in the art are not entered
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
The preparation method of conductor device.Obviously, what the execution of the present invention was not limited to that the technical staff of semiconductor applications is familiar with is special
Details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have it
His embodiment.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
Exemplary embodiment according to the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is intended to include plural form.Additionally, it should be understood that, when in this manual using term "comprising" and/or " inclusion "
When, it indicates there is described feature, entirety, step, operation, element and/or assembly, but does not preclude the presence or addition of one or many
Other features individual, entirety, step, operation, element, assembly and/or combinations thereof.
Now, it is more fully described the exemplary embodiment according to the present invention with reference to the accompanying drawings.However, these exemplary realities
Apply example to implement with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Be understood by, these embodiments are provided so that disclosure of the invention is thoroughly and complete, and by these exemplary enforcements
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region
Degree, and make to be presented with like reference characters identical element, thus description of them will be omitted.
With reference to Fig. 1-6, the preparation method of the semiconductor device containing highly controllable fin of the present invention is done further
Explanation:
As shown in figure 1, offer Semiconductor substrate, described substrate includes at least the first fin and the second fin；
Specifically, described Semiconductor substrate 101 can be at least one in the following material being previously mentioned: silicon, insulator
Stacking silicon (ssoi) on upper silicon (soi), insulator, stacking SiGe (s-sigeoi), germanium on insulator SiClx on insulator
And germanium on insulator (geoi) etc. (sigeoi).Active area can be defined on Semiconductor substrate.Also may be used on the active region
To include other active devices, in order to simplify accompanying drawing, do not indicate in shown figure.
Described Semiconductor substrate is divided into nmos region and pmos region in the present invention.
Then form fin on the semiconductor substrate, difference shape at least in described pmos region and nmos region
Become the first fin 20 and the second fin 10.The forming method of described first fin and the second fin can commonly use side from ability
Method, for example in the present invention can epitaxial growth of semiconductor material layer over the substrate, then in described semiconductor material layer
Upper formation fin pattern mask layer, for example, comprise the photoresist mask layer of fin cd, pattern, then with described fin pattern mask
Layer is semiconductor material layer described in mask etch, to described substrate, forms the first fin 20 and the second fin 10, then removes institute
State mask layer.
With reference to Fig. 2, deposit high work function metal material layer over the substrate, to cover described first fin and described second
Fin；
Specifically, after forming described first fin 20 and the second fin 10, uniformly carry out ion over the substrate
Doping, such as on substrate, nmos region carries out N-shaped doping, to form n-type transistor, carries out p-type doping in pmos region, with
Form p-type transistor, described n-type dopant includes p, as, sb, and described p-type dopant includes b and bf and in, described doping side
Method can be any one method following:
First method is ion implanting (nitrogen implantation), and the ion energy of described injection is 1kev-
10kev, the ion dose of injection is 5 × 1014-5×1016Atom/cm2.It is preferably less than 400 DEG C in the present invention, Er Qietong
Cross the control Impurity Distribution (ion energy) that methods described can be more independent and impurity concentration (when ion current density and injection
Between), the method is easier to obtain the doping of high concentration, and for anisotropy doping, the independent controlling depth of energy and concentration.
The present invention also can be selected for plasma doping (plasma doping), when this method is employed typically from higher
Temperature, typically selects 900-1200 DEG C in the present invention, and methods described is isotropism.
Then deposit high work function metal material layer over the substrate, in the present invention preferably mo, described deposition process can
So that from one of sputtering (sputtering), physical vapour deposition (PVD) (pvd) method, its thickness can be 40-100nm.
Then the both sides of fin described in described pmos region carry out ion implanting, and wherein said injection ionic type can
With identical or different, to form identical or different threshold voltages in described fin both sides, preferably carry out in the present invention
Dissimilar ion implanting, forms different threshold voltages, and the ion of wherein said injection can select species commonly used in the art,
Here will not enumerate.
Then low work function metal material layer is deposited on described second fin and both sides, to cover described second fin, and
Work function metal material laminate is formed on described second fin；
Specifically, in described high work function metal material layer (mo material layer) the low work function metal material layer of upper deposition, at this
Preferred ta in bright, then forms mask layer on described second fin regions, and etching removes the institute being located on the first fin regions
State low work function metal material layer, then remove mask layer, only on described second fin regions, form low work function metal material layer,
In conjunction with underlying mo material layer, form work function metal material laminate, wherein said ta selects physical vapour deposition (PVD) (pvd) method
Formed, its thickness can be 20-50nm.In this step simultaneously by the high work function metal material layer on described first fin regions
Form isolation with the high work function metal material layer on described second fin regions, to form each independent grid structure.
Then the both sides of the second fin described in described nmos region carry out ion implanting, wherein said injection ionic species
Type can be identical or different, to form identical or different threshold voltages in described fin both sides, in the present invention preferably
Carry out dissimilar ion implanting, form different threshold voltages, the ion of wherein said injection can be selected commonly used in the art
Species, here will not enumerate.
With reference to Fig. 4, grid structure is formed on described first fin and described second fin；
Specifically, grid structure patterned masking layer can be formed first on described metal material layer, with described grid knot
Structure pattern mask layer is metal material layer described in mask etch, including mo and ta material layer, forms grid structure.
Preferably, selecting cl when etching described metal material layer2And o2Combination, or chf3And o2Combination, its
Middle gas flow is 10-400sccm, and described etching pressure is 20-300mtorr, and etching period is 5-120s, preferably 5-
60s, more preferably 5-30s.
Also include annealing steps after forming described grid structure, so that the described low work content gold on described second fin
Belong to material layer and diffuse in described high work function metal material layer, wherein said annealing steps are usually that described substrate is placed in Gao Zhen
Under the protection of sky or high-purity gas, it is heated to certain temperature and carries out heat treatment, be preferably nitrogen in high-purity gas of the present invention
Gas or noble gases, the temperature of described thermal anneal step is 900-1200 DEG C, and the described thermal anneal step time is 1-200s.
As further preferred, rapid thermal annealing can be selected in the present invention, specifically, can select following several
One of mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser are fast
Fast annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc..Those skilled in the art are permissible
Selected as needed, be also not limited to examples cited.
After having executed annealing steps, the step that can also comprise interlevel dielectric deposition further, the present invention's
Interlayer dielectric layer described in embodiment can be using such as sio2, fluorocarbon (cf), carbon doped silicon oxide (sioc) or carbon nitrogen
SiClx (sicn) etc..Or, it is possible to use define film of sicn thin film etc. on fluorocarbon (cf).Fluorocarbon
With fluorine (f) and carbon (c) as main component.Fluorocarbon can also use has the material that noncrystal (amorphism) constructs.
Interlayer dielectric layer can also be using the such as Porous such as carbon doped silicon oxide (sioc) construction.
Then execute planarisation step, remove remaining on described first fin and the second fin in this step simultaneously
Described high work function metal material layer and described low work function metal material layer, to form independent bigrid no junction structure (dual
Gate junctionless).
Fig. 5 is the top view of the bigrid no junction structure being formed in described pmos, is formed in the both sides of described first fin
There is certain thickness mo material layer.
Fig. 6 is the top view of the bigrid no junction structure being formed in described nmos, is formed in the both sides of described first fin
There is certain thickness work function metal material laminate.
Present invention also offers a kind of semiconductor device with independent double-metal grid no junction structure, comprising:
Semiconductor substrate；
The first fin in described Semiconductor substrate and the second fin；
Uniformly doped with different types of dopant in described first fin both sides and described second fin both sides substrate；
Positioned at the high work function metal material layer of described first fin both sides, independent to be formed in described first fin regions
Bigrid no junction structure,
Positioned at high work function metal material layer and the low work function metal material layer of described second fin both sides, with described second
Fin regions form independent bigrid no junction structure.
In the device that the method for the invention prepares, threshold voltage (vth) is controlled, and methods described is prepared into
To double-metal grid between there is no node (junction), be independent bigrid finfet, make the threshold value of semiconductor device
Voltage (vth) is more stable, enhances the performance of sram unit.
Fig. 7 is the process chart that the preparation present invention prepares semiconductor device, comprises the following steps:
Step 201 provides Semiconductor substrate, and described substrate includes at least the first fin and the second fin；
Step 202 deposits high work function metal material layer over the substrate, to cover described first fin and described second
Fin；
Step 203 forms low work function metal material in the described high work function metal material layer of described second fin and both sides
Layer, to form work function metal material laminate on described second fin；
Step 204 deposits gate pattern mask layer, etches described low work function metal material layer and described high work function metal material
The bed of material, to form grid structure on described first fin and described second fin.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member, it is understood that the invention is not limited in above-described embodiment, can also make more kinds of according to the teachings of the present invention
Variants and modifications, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (19)
1. a kind of preparation method of semiconductor device, comprising:
Semiconductor substrate is provided, described substrate includes at least the first fin and the second fin；
Deposit high work function metal material layer over the substrate, to cover described first fin and described second fin；
The described high work function metal material layer of described second fin and both sides forms low work function metal material layer, with described
Work function metal material laminate is formed on the second fin；
Deposition gate pattern mask layer, etches described low work function metal material layer and described high work function metal material layer, with institute
State formation grid structure on the first fin and described second fin；
Remove the described high work function metal material layer on described first fin top, formed solely with the both sides in described first fin
Vertical bigrid no junction structure, removes the described high work function metal material layer on described second fin top and described low work(simultaneously
Letter metal material layer, to form independent bigrid no junction structure in described second fin both sides.
2., after method according to claim 1 is it is characterised in that form described grid structure, execute annealing steps, so that
The low work function metal in described low work function metal material layer on described second fin diffuses to described high work function metal material layer
In.
3., after method according to claim 1 is it is characterised in that form described grid structure, also include depositing interlayer Jie
Matter layer the step planarizing.
4. method according to claim 3 it is characterised in that described planarization remove described interlayer dielectric layer while,
Remove remaining described high work function metal material layer on described first fin top, remove surplus on described second fin top simultaneously
Remaining described high work function metal material layer and described low work function metal material layer, to form independent bigrid no junction structure.
5. method according to claim 1 is it is characterised in that low work function metal material layer and described height described in dry etching
Work function metal material layer, to form grid structure.
6. method according to claim 5 is it is characterised in that described dry etching selects cl2And o2Combination, or
chf3And o2Combination.
7. method according to claim 1 is it is characterised in that methods described is further comprising the steps of:
Before deposition high work function metal material layer, described first fin regions and described second fin regions carry out difference
The doping of type.
8. method according to claim 7 is it is characterised in that described first fin both sides doped p type dopant, to be formed
pmos.
9. method according to claim 7 it is characterised in that described second fin both sides doping n-type dopant, with formed
nmos.
10. method according to claim 1 is it is characterised in that described high work function metal material layer is mo.
11. methods according to claim 1 are it is characterised in that described low work function metal material layer is ta.
After 12. methods according to claim 1 are it is characterised in that deposit high work function metal material layer over the substrate,
In described first fin both sides execution same type or different types of ion implanting, to form identical or different threshold values
Voltage.
13. methods according to claim 1 are it is characterised in that deposit low work function metal material on described second fin
After layer, execute same type or different types of ion implanting in described second fin both sides, identical or different to be formed
Threshold voltage.
A kind of 14. semiconductor device with independent double-metal grid no junction structure, comprising:
Semiconductor substrate；
The first fin in described Semiconductor substrate and the second fin；
Uniformly doped with different types of dopant in described first fin both sides and described second fin both sides substrate；
Positioned at the high work function metal material layer of described first fin both sides, to form independent double grid in described first fin regions
Pole no junction structure,
Positioned at high work function metal material layer and the low work function metal material layer of described second fin both sides, with described second fin
Region forms independent bigrid no junction structure.
15. semiconductor device according to claim 14 are it is characterised in that described high work function metal material layer is mo.
16. semiconductor device according to claim 14 are it is characterised in that described low work function metal material layer is ta.
17. semiconductor device according to claim 14 are it is characterised in that the dopant of described second fin both sides is n
Type dopant, to form nmos.
18. semiconductor device according to claim 14 are it is characterised in that the dopant of described second fin both sides is p
Type dopant, to form pmos.
19. semiconductor device according to claim 14 are it is characterised in that high work function metal material on described first fin
Mutually isolated between high work function metal material layer on the bed of material and described second fin.
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| US9837416B2 (en) * | 2015-07-31 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Multi-threshold voltage field effect transistor and manufacturing method thereof |
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| CN102222693A (en) * | 2010-04-15 | 2011-10-19 | 中国科学院微电子研究所 | FinFET device and manufacturing method thereof |
| CN102237399A (en) * | 2010-04-22 | 2011-11-09 | 联华电子股份有限公司 | Semiconductor element having metal gate and manufacturing method thereof |
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| CN102222693A (en) * | 2010-04-15 | 2011-10-19 | 中国科学院微电子研究所 | FinFET device and manufacturing method thereof |
| CN102237399A (en) * | 2010-04-22 | 2011-11-09 | 联华电子股份有限公司 | Semiconductor element having metal gate and manufacturing method thereof |
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