CN113130309B - Doping defect removal method - Google Patents

Doping defect removal method Download PDF

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CN113130309B
CN113130309B CN202110396009.9A CN202110396009A CN113130309B CN 113130309 B CN113130309 B CN 113130309B CN 202110396009 A CN202110396009 A CN 202110396009A CN 113130309 B CN113130309 B CN 113130309B
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semiconductor structure
grinding
liquid
defects
doping
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CN113130309A (en
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刘金彪
罗军
李俊峰
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The application provides a doping defect removing method, which provides a semiconductor structure, wherein the semiconductor structure is subjected to ion implantation and annealing treatment, the semiconductor structure is provided with a sharp corner, defects exist at the sharp corner, then the semiconductor structure can be oxidized at a low temperature to oxidize the defects at the sharp corner, and as more dangling bonds exist at the defects, the activity is higher, the semiconductor structure is easy to oxidize, oxidized parts in the semiconductor structure can be removed, so that the defects formed during doping of the semiconductor structure can be effectively removed, and the device performance is improved.

Description

Doping defect removal method
Technical Field
The present disclosure relates to semiconductor devices and methods for fabricating the same, and more particularly, to a method for removing doping defects.
Background
In the manufacturing process of the semiconductor device, there is a process of doping the semiconductor structure by ion implantation, specifically, annealing may be performed at normal temperature or low temperature implantation to activate doped ions in the semiconductor structure, however, when the semiconductor structure has sharp corners, twin defects (twin defects) are formed at the sharp corners after annealing, referring to fig. 1, which is a schematic diagram of a current twin defect, in which a semiconductor structure 200 is formed on a substrate 100, and twin defects 210 are formed at the sharp corners of the semiconductor structure 200, and such defects affect electrical performance of the semiconductor structure.
Heat implantation is often used to eliminate this defect, but the heat implantation has adverse effects on the control and activation of the impurity profile. How to remove such defects without affecting the doping effect is an important issue for improving the performance of semiconductor devices.
Disclosure of Invention
In view of the above, an object of the present application is to provide a method for removing doping defects, which effectively removes defects formed during doping of a semiconductor structure, and improves device performance.
An embodiment of the present application provides a method for removing a doping defect, including:
providing a semiconductor structure; the semiconductor structure is subjected to ion implantation and annealing treatment, the semiconductor structure is provided with a sharp corner, and a defect exists at the sharp corner;
performing low-temperature oxidation on the semiconductor structure to oxidize defects at the sharp corners;
and removing the oxidized part of the semiconductor structure.
Optionally, the removing the oxidized portion of the semiconductor structure includes:
placing the semiconductor structure in a polishing apparatus; the grinding device comprises a grinding cavity; a grinding machine is arranged in the grinding cavity and is used for placing the semiconductor structure; the side wall of the grinding cavity is provided with a liquid inlet and a liquid outlet; the liquid inlet is used for introducing grinding liquid into the grinding cavity, and the liquid outlet is used for flowing out the grinding liquid in the grinding cavity;
introducing grinding liquid into the grinding cavity by utilizing the liquid inlet; and when the grinding liquid in the grinding cavity submerges the semiconductor structure on the grinding machine, grinding the semiconductor structure to remove oxidized parts in the semiconductor structure.
Optionally, inert gas is filled in the grinding cavity, a pressure disc is arranged at the top of the grinding cavity, and the pressure disc is used for adjusting the pressure of the inert gas when moving longitudinally, and the method further comprises:
the position of the pressure plate in the longitudinal direction is adjusted to adjust the pressure of the inert gas.
Optionally, the inert gas is doped with HF gas or HCl gas.
Optionally, the method further comprises:
and controlling the grinder to rotate so as to drive the semiconductor structure to rotate.
Optionally, the method further comprises:
ultrasound or megasonic is applied to the slurry.
Optionally, the method further comprises:
and heating the grinding fluid.
Optionally, the low temperature oxidizing the semiconductor structure includes:
and carrying out ozone oxidation on the semiconductor structure.
Optionally, before performing low-temperature oxidation on the semiconductor structure, the method further includes:
and performing surface activation treatment on the semiconductor structure by utilizing plasma.
Optionally, the semiconductor structure is a source drain in a fin field effect transistor device, and the ion implantation is used for realizing shallow junction implantation or source drain doping.
The embodiment of the application provides a doping defect removing method, a semiconductor structure is provided, the semiconductor is subjected to ion implantation and annealing treatment, the semiconductor structure is provided with a sharp corner, defects exist at the sharp corner, then the semiconductor structure can be subjected to low-temperature oxidation to oxidize the defects at the sharp corner, and as more suspension bonds exist at the defects, the activity is higher, the semiconductor structure is easy to oxidize, oxidized parts in the semiconductor structure can be removed, so that the defects formed during doping of the semiconductor structure can be effectively removed, and the device performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a twin defect;
FIG. 2 is a flowchart of a method for removing doping defects according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a polishing apparatus according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of another doping defect removal method according to an embodiment of the present disclosure;
fig. 5-7 are schematic diagrams illustrating the processing of a semiconductor structure in an embodiment of the present application.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the schematic drawings, wherein the cross-sectional views of the device structure are not to scale for the sake of illustration, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
As described in the background art, in the semiconductor manufacturing process, there is a process of doping a semiconductor structure by ion implantation, however, when there is a sharp corner in the semiconductor result, twin defects are formed at the sharp corner after ion implantation and annealing, which affects the electrical performance of the semiconductor structure.
Based on the above technical problems, the embodiment of the application provides a doping defect removal method, a semiconductor structure is provided, the semiconductor is subjected to ion implantation and annealing treatment, the semiconductor structure has sharp corners, defects exist at the sharp corners, then the semiconductor structure can be subjected to low-temperature oxidation to oxidize the defects at the sharp corners, and the oxidized parts in the semiconductor structure can be removed because more dangling bonds exist at the defects, the activity is higher, so that the defects formed during doping of the semiconductor structure can be effectively removed, and the performance of a device is improved.
A specific implementation manner of a doping defect removal method in the embodiments of the present application is described in detail below by way of examples with reference to the accompanying drawings.
Referring to fig. 2, a flowchart of a doping defect removal method according to an embodiment of the present application is shown, where the method may include:
s101, providing a semiconductor structure.
In the embodiment of the application, the semiconductor structure can be subjected to ion implantation and annealing treatment, the ion implantation can drive doped ions into the semiconductor structure, and the annealing treatment can activate impurities, so that the doping of the semiconductor structure is realized. Then, when the semiconductor structure has sharp corners, ion implantation and annealing processes are prone to defects at the sharp corners, which affect the electrical properties of the semiconductor structure.
The semiconductor structure may be a source drain of a semiconductor device, which may be a Fin Field effect transistor (FinFet). Specifically, the ion implantation may be shallow junction implantation (Light doped Drain, LDD) or source-drain doping of the source-drain region, that is, the semiconductor structure of the source-drain region subjected to the shallow junction implantation may be used as the aforementioned semiconductor structure, and the semiconductor structure of the source-drain region subjected to the source-drain doping may be used as the aforementioned semiconductor structure.
The material of the semiconductor structure may include at least one of silicon and germanium, and the dopant ions may include N-type dopant ions or P-type dopant ions.
S102, performing low-temperature oxidation on the semiconductor structure to oxidize defects at sharp corners.
The inventor finds that the defects at the sharp corners of the semiconductor structure have more dangling bonds, so the semiconductor structure has higher activity and is easier to oxidize, and therefore, in the embodiment of the application, the semiconductor structure can be oxidized at a low temperature to oxidize the defects at the sharp corners, and other areas except the sharp corners cannot be oxidized or are oxidized in a small amount. The low-temperature oxidation may be ozone oxidation, for example.
The surface active treatment of the semiconductor structure can also be performed by utilizing plasma before the low-temperature oxidation of the semiconductor structure, so that the surface activity of the semiconductor structure is improved, and the oxidation of the surface of the semiconductor structure is facilitated.
S103, removing oxidized parts in the semiconductor structure.
In the embodiment of the application, after the semiconductor structure is subjected to low-temperature oxidation, the oxidized part in the semiconductor structure can be removed, so that the doped part in the semiconductor structure can be exposed, and the defect at the sharp corner is completely removed after the oxidized part is removed because the sharp corner is completely oxidized, so that the defect can be removed on the premise of not affecting the doping effect, and the device performance is improved.
The removal of the oxidized portion of the semiconductor structure may be performed by, for example, placing the semiconductor structure in a polishing apparatus, thereby removing the oxidized portion of the semiconductor structure with the polishing apparatus.
Specifically, referring to fig. 3, which is a schematic structural diagram of a polishing apparatus according to an embodiment of the present application, the polishing apparatus may include a polishing cavity 10, the polishing cavity 10 is a sealable cavity, a polishing table 110 is disposed in the polishing cavity 10, and the polishing table 110 is used for placing a semiconductor structure. The grinder 110 can rotate in a horizontal plane to rotate the semiconductor structure.
The side wall of the grinding cavity 10 is provided with a liquid inlet 141 and a liquid outlet 142, the liquid inlet 141 is used for introducing grinding liquid into the grinding cavity 10, the liquid outlet 142 is used for flowing out the grinding liquid in the grinding cavity 10, and when the grinding liquid in the grinding cavity 10 submerges the semiconductor structure on the grinding table 110, the surface to be ground of the semiconductor structure can be ground, and the surface to be ground of the semiconductor structure is an oxidized part. This is because the polishing liquid contains a component that erodes the surface to be polished, and abrasive grains are present, and the polishing liquid reacts with the substance on the surface to be polished, thereby polishing the surface to be polished. As the semiconductor structure rotates with the platen 110, there is relative motion between the semiconductor structure and the polishing liquid, and the polishing rate is increased. The composition of the polishing liquid may be determined according to actual needs and is mainly used for reacting with the oxidized portion of the semiconductor structure, which is not illustrated herein.
Therefore, the oxidized portion of the semiconductor structure may be removed by the polishing apparatus, specifically, the polishing liquid may be introduced into the polishing chamber through the liquid inlet, and when the semiconductor structure on the polishing platen is immersed in the polishing liquid in the polishing chamber, the semiconductor structure may be polished to remove the oxidized portion of the semiconductor structure.
In addition, the grinder 110 can be controlled to rotate to drive the semiconductor structure to rotate, thereby increasing the polishing rate. Of course, ultrasonic or megasonic can be applied to the grinding liquid, so that the grinding liquid is fully contacted with the surface to be ground under the action of hydraulic pressure and reacts, the grinding rate is improved, meanwhile, the surface damage is reduced, the grinding uniformity is improved, and the grinding rate can be adjusted by adjusting the frequency and the power of ultrasonic or megasonic. The grinding fluid can be heated to increase the reaction rate of the grinding fluid and the substance on the surface to be ground, thereby increasing the grinding rate. Thus, the polishing rate of the surface to be polished can be controlled by controlling at least one of the rotational speed of the polishing table 110, the ultrasonic frequency, the megasonic frequency, the ultrasonic power, the megasonic power, the temperature of the polishing liquid, and the pressure of the inert gas.
The liquid inlet 141 may be connected to a polishing liquid output device, the liquid outlet 142 may be connected to a polishing liquid processing device, and when the pressure in the polishing chamber 10 is high, the liquid inlet 141 may have a certain liquid input pressure so that the polishing liquid is introduced into the polishing chamber 10. The liquid inlet 141 may be located higher than the liquid outlet 142. In the grinding process of the surface to be ground, the grinding liquid can flow in real time to ensure the uniformity of the grinding rate, and the grinding liquid can be replaced according to a certain period.
Generally, the liquid in the polishing cavity 10 does not fill the polishing cavity 10, and the polishing cavity 10 may be filled with an inert gas, wherein the inert gas is located above the polishing cavity 10, and the polishing liquid is located below the polishing cavity 10. Among them, inert gases such as nitrogen, argon, and the like. In order to adjust the polishing rate of the surface to be polished by the polishing liquid, the inert gas may be mixed with HF gas or HCl gas, which is mixed into the polishing liquid, so that the polishing rate of the surface to be polished by the polishing liquid may be increased.
In this embodiment, the top of the grinding cavity 10 may further be provided with a pressure disc 120, where the pressure disc 120 is tightly combined with the sidewall of the grinding cavity 10, and the grinding cavity 10 is divided into a portion above the pressure disc 120 and a portion below the pressure disc 120, so that when the pressure disc 120 moves longitudinally, the air pressure in the cavity below the pressure disc 120 will change. For example, when the cavity below the pressure plate 120 is filled with the inert gas, the pressure of the inert gas may change along with the longitudinal movement of the pressure plate 120, the inert gas is located above the polishing liquid, and when the pressure of the inert gas increases, the inert gas may apply pressure to the polishing liquid, so that the pressure of the polishing liquid increases, and the polishing rate may be increased.
The inert gas is filled in the grinding cavity 10, and when the pressure disc 120 is arranged at the top of the grinding cavity 10, the position of the pressure disc 120 in the longitudinal direction can be adjusted to adjust the pressure of the inert gas, so that the internal pressure of the grinding fluid is improved, and the grinding rate is improved.
In order to realize the longitudinal movement of the pressure disc 120, a piston rod 121 may be disposed above the pressure disc 120, the bottom of the piston rod 121 is connected to the pressure disc 120, and a linkage 122 is connected above the piston rod 121, and the piston rod 121 and the pressure disc 120 may be longitudinally moved by the linkage 122. The number of the piston rods 121 may be one or plural, for example, two, and the piston rods 121 may extend through the top of the polishing chamber 10 to the outside of the polishing chamber 10, and the linkage 122 may be disposed outside the polishing chamber 10. A first pressure gauge 123 may be provided above the pressure disc 120 for detecting the air pressure above the pressure disc 120, indicative of the longitudinal position of the pressure disc 120.
In this embodiment, the side wall of the grinding cavity 10 may be further provided with a pressure adjusting valve 131 for releasing the inert gas in the grinding cavity 10 to reduce the pressure of the inert gas, so that the pressure of the inert gas can be finely adjusted when the pressure of the inert gas is relatively large. A second pressure gauge 124 may also be provided on the side wall of the grinding chamber 10 for sensing the pressure of the gas below the pressure plate 120 and characterizing the pressure of the inert gas.
The embodiment of the application provides a doping defect removing method, a semiconductor structure is provided, the semiconductor is subjected to ion implantation and annealing treatment, the semiconductor structure is provided with a sharp corner, defects exist at the sharp corner, then the semiconductor structure can be subjected to low-temperature oxidation to oxidize the defects at the sharp corner, and as more suspension bonds exist at the defects, the activity is higher, the semiconductor structure is easy to oxidize, oxidized parts in the semiconductor structure can be removed, so that the defects formed during doping of the semiconductor structure can be effectively removed, and the device performance is improved.
In order to better understand the technical solution and the technical effects of the present application, a method for removing doping defects provided in the embodiments of the present application will be described below with reference to specific examples, in which the semiconductor structure is a FinFet device, fig. 4 is a flowchart of another method for removing doping defects provided in the embodiments of the present application, and fig. 5 to 7 are schematic diagrams during the processing of the semiconductor structure in the embodiments of the present application. The doping defect removal method may include the steps of:
s201, providing a substrate 300, forming a fin 310 extending along a first direction AA on the substrate 300, and forming a dummy gate 320 extending along a second direction BB on the fin 310 and covering a middle portion of the fin 310, wherein the first direction AA and the second direction BB are orthogonal in a plane of the substrate 300, as shown in fig. 5 and 6.
In the embodiment of the present application, the substrate 300 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator ) or GOI (germanium on insulator, germanium On Insulator), a group iii-v compound, a group ii-iv compound semiconductor, or the like. In this embodiment, the substrate 300 is a silicon substrate.
In this embodiment, the fin 310 on the substrate may be obtained by etching an original substrate, and the etching manner for forming the fin 310 may be a sidewall transfer technology, specifically, a semiconductor layer may be formed on the original substrate, a sidewall is formed on a sidewall of the semiconductor layer, the semiconductor layer is removed, and then the original substrate is etched with the sidewall as a mask to form the fin 310 on the substrate 300. The material of fin 310 is consistent with the material of the substrate. Of course, in other embodiments, the fins on the substrate may also be obtained by epitaxial growth, and the material may also be inconsistent with the substrate.
On the substrate on both sides of the fins 310, isolation layers 311 may be formed, constituting shallow trench isolation (shallow trench isolation, STI for short) structures between different fins 310.
For convenience of description and understanding, in this application, the extending direction of the etched fin 310 is referred to as a first direction AA, and in the plane of the substrate 300, a direction orthogonal to the first direction AA is referred to as a second direction BB.
A dummy gate 320 is formed on the fin 310 to cover a middle portion of the fin 310, and may specifically be formed by depositing a dummy gate material, etching the dummy gate material through an anisotropic etching process, and retaining the dummy gate material in the middle portion of the fin 310 to form the dummy gate 320. The dummy gate 320 may be, for example, polysilicon or monocrystalline silicon. The area where the fins on two sides of the dummy gate 320 are located is a source-drain area and is exposed.
S202, shallow junction implantation is conducted in the source-drain region.
Shallow junction implantation in the source and drain regions may include ion implantation in the source and drain regions, wherein the ion implantation may drive dopant ions into the fins 310 of the source and drain regions, and an annealing process may activate the impurities, thereby achieving shallow junction implantation in the source and drain regions. The fin 310 of the source and drain region has a sharp corner, so that defects are easily caused at the sharp corner after the shallow junction implantation, and thus the semiconductor structure formed after the shallow junction implantation in the source and drain region may be used as the semiconductor structure in S101, and then the removal of defects at the sharp corner may be performed with reference to S102 and S103.
Specifically, the semiconductor structure can be oxidized at a low temperature to oxidize defects at the sharp corners, and then oxidized parts in the semiconductor structure can be removed, so that doped parts in the semiconductor structure are exposed. Of course, the surface active treatment of the semiconductor structure may also be performed by using plasma prior to the low temperature oxidation, so as to improve the surface activity of the semiconductor structure and facilitate the oxidation of the surface of the semiconductor structure.
S203, forming a sidewall 321 on the sidewall of the dummy gate 120, as shown in fig. 7.
Forming the sidewall 321 on the sidewall of the dummy gate 320 may specifically be depositing a sidewall material, etching the sidewall material by an anisotropic etching process, and retaining a certain thickness of the sidewall material on the sidewall of the dummy gate 320 to form the sidewall 321. The sidewall 321 may be a single layer or a multi-layer structure and may be a low-k dielectric material, such as a silicon nitride material.
S204, performing source-drain doping in the source-drain region.
The source-drain doping in the source-drain region may include performing an ion implantation and an annealing process in the source-drain region, wherein the ion implantation may implant dopant ions into the fin 310 of the source-drain region, and the annealing process may activate impurities, thereby achieving source-drain doping in the source-drain region, and of course, the source-drain doped region is smaller than the shallow junction implanted region and the concentration of the source-drain doping is greater than the concentration of the shallow junction implanted region. The fin 310 of the source-drain region has a sharp corner, so that defects are easily caused at the sharp corner after source-drain doping, and thus the semiconductor structure formed after source-drain doping in the source-drain region can be used as the semiconductor structure in S101, and then the defects at the sharp corner can be removed with reference to S102 and S103.
Specifically, the semiconductor structure can be oxidized at a low temperature to oxidize defects at the sharp corners, and then oxidized parts in the semiconductor structure can be removed, so that doped parts in the semiconductor structure are exposed. Of course, the surface active treatment of the semiconductor structure may also be performed by using plasma prior to the low temperature oxidation, so as to improve the surface activity of the semiconductor structure and facilitate the oxidation of the surface of the semiconductor structure.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing is merely a preferred embodiment of the present application, and although the present application has been disclosed in the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art may make many possible variations and modifications to the technical solution of the present application, or modify equivalent embodiments, using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application, which do not depart from the content of the technical solution of the present application, still fall within the scope of the technical solution of the present application.

Claims (7)

1. A doping defect removal method, comprising:
providing a semiconductor structure; the semiconductor structure is subjected to ion implantation and annealing treatment, the semiconductor structure is provided with a sharp corner, and a defect exists at the sharp corner;
performing low-temperature oxidation on the semiconductor structure to oxidize defects at the sharp corners;
placing the semiconductor structure in a polishing apparatus; the grinding device comprises a grinding cavity; a grinding machine is arranged in the grinding cavity and is used for placing the semiconductor structure; the side wall of the grinding cavity is provided with a liquid inlet and a liquid outlet; the liquid inlet is used for introducing grinding liquid into the grinding cavity, and the liquid outlet is used for flowing out the grinding liquid in the grinding cavity;
introducing grinding liquid into the grinding cavity by utilizing the liquid inlet; when the grinding liquid in the grinding cavity submerges the semiconductor structure on the grinding machine, the semiconductor structure is ground so as to remove oxidized parts in the semiconductor structure;
the grinding cavity is filled with inert gas, and the top of the grinding cavity is provided with a pressure disc which is used for adjusting the position of the pressure disc in the longitudinal direction when adjusting the pressure of the inert gas during longitudinal movement so as to adjust the pressure of the inert gas;
the inert gas is doped with HF gas or HCl gas.
2. The method according to claim 1, wherein the method further comprises:
and controlling the grinder to rotate so as to drive the semiconductor structure to rotate.
3. The method according to claim 1, wherein the method further comprises:
ultrasound or megasonic is applied to the slurry.
4. The method according to claim 1, wherein the method further comprises:
and heating the grinding fluid.
5. The method of any of claims 1-4, wherein the low temperature oxidizing the semiconductor structure comprises:
and carrying out ozone oxidation on the semiconductor structure.
6. The method of any of claims 1-4, wherein prior to subjecting the semiconductor structure to low temperature oxidation, the method further comprises:
and performing surface activation treatment on the semiconductor structure by utilizing plasma.
7. The method of any of claims 1-4, wherein the semiconductor structure is a source drain in a fin field effect transistor device, and the ion implantation is used to achieve shallow junction implantation or source drain doping.
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