JPH1174527A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to suppress a concentration of an electric field at the edge corner of an element region and prevent the deterioration of transistor characteristic. SOLUTION: A method of manufacturing the semiconductor comprises a process for forming a first film and a second film, a process for forming a first groove by selectively removing an upper part of the second film, the first film, and a semiconductor substrate 101, a process for embedding a first insulation film 107 in the first groove and forming an element separation region, a process for patterning the second film surrounded by the element separation region and forming a dummy gate layer, a process for entering impurity to the semiconductor substrate 101 with masking by the dummy gate layer, a process for forming a second insulation film 113 on the semiconductor substrate 101 surrounded by the dummy gate layer and the first insulation film 107, a process for forming a second groove by removing the dummy gate layer and the first film, a process for forming a gate insulation film on the semiconductor substrate 101 in the second groove, and a process for forming a gate electrode on the gate insulation film in the second groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a semiconductor device including a step of forming a dummy gate.

[0002]

2. Description of the Related Art Miniaturization of an element size plays an important role in improving the performance and cost of a semiconductor integrated circuit using MOS transistors. The miniaturization of the element size can be realized by using STI (Shallow Trench Isolation) technology, but in order to solve the problem that the wiring resistance increases due to the miniaturization, a metal material having a low resistance is used for the gate electrode. A method for reducing the wiring resistance has been proposed.

However, when the source / drain regions are formed after the formation of the gate insulating film and the gate electrode as in the prior art, a high-temperature heating step and a thermal oxidation step are required, which increases the resistance of the metal electrode and deteriorates the reliability of the gate insulating film. There was such a problem.

As a means for solving these problems, a step of forming a source / drain region requiring a high-temperature step is first performed, and a gate insulating film is formed in a groove formed in a self-aligned manner with respect to the source / drain region. In addition, a method of burying a gate electrode has been proposed.

An example of the above technique (Japanese Patent Application No. 8-356493) will be described below with reference to FIGS. 67 and 68 are cross-sectional views of the transistor in the L direction (channel length direction), and FIG. 69 is a cross-sectional view of the transistor in the W direction (channel width direction).

First, a transistor formation region 502 is formed on a Si substrate 501 by using a trench isolation (STI) technique.
Then, an element isolation region 503 is formed (FIGS. 67A and 69A).

Next, an SiO ₂ film 504 having a thickness of about 10 nm is formed on the exposed surface of the Si substrate 501, and this S
Poly-Si for dummy gate pattern on the SiO ₂ film 504
A film is deposited to a thickness of about 300 nm, and processed using, for example, a lithography method and an RIE method to form a dummy gate pattern 505 (FIG. 67B).

Next, using the dummy gate pattern 505 as a mask, for example, phosphorus ions are implanted into the element region surrounded by the element isolation region 503 to form an n ⁻ type diffusion region 506 (FIG. 67 (c)). )).

After depositing a Si ₃ N ₄ film on the entire surface, RIE is performed on the entire surface to form a dummy gate pattern 505.
A Si ₃ N ₄ film 507 having a thickness of about 20 nm is formed on the side wall of FIG.

Thereafter, using the dummy gate pattern 505 and the Si ₃ N ₄ film 507 as a mask, for example, arsenic ions are implanted into the n ⁻ -type diffusion region 506, and
^{A +} type diffusion region 508 is formed to form a so-called LDD structure (FIG. 67E).

Next, a CVD-SiO ₂ film 509 is formed on the entire surface.
Is deposited, for example, in a thickness of about 300 nm, and densified in an N ₂ atmosphere at about 800 ° C. for about 30 minutes, for example.
The whole surface is flattened by CMP, and the dummy gate pattern 5 is formed.
05 is exposed (FIG. 68 (f)).

Next, after the dummy gate pattern 505 is selectively removed to form a groove 510, a resist film (not shown) formed in a desired region and an interlayer film (SiO ₂ film 50) are formed.
9) and the side wall insulating film (Si ₃ N ₄ film 507) are used as a mask to perform ion implantation only in a channel planned region below the groove 510. Activation of this channel impurity
Thereafter, heat treatment at 800 ° C. for about 10 seconds is performed using, for example, RTA to form a channel impurity region 511 (FIG. 68G).

The SiO ₂ film 5 on the bottom of the groove 510
04 is removed (FIG. 68 (h), FIG. 69 (b)).

Next, a gate insulating film 512 is formed on the entire surface.
For example, a high dielectric film such as a Ta ₂ O ₅ film is deposited to a thickness of about 20 nm, and a metal film such as Ru is deposited as the gate electrode 513 on the entire surface. Thereafter, by performing CMP on the entire surface, the metal electrode 513 and the high dielectric gate film 512 are left in the trench 510 and are embedded in the trench 510 (FIG. 68 (i)).

Thereafter, SiO _{2 is used} as an interlayer insulating film on the entire surface.
After depositing a film having a thickness of about 200 nm, contacts to the source and drain regions and the gate electrode are opened in the interlayer insulating film. Further, an Al layer is formed on the entire surface and then patterned to form an Al wiring. To form Then, a passivation film is deposited on the entire surface to complete the basic structure of the transistor.

However, in the above method, FIG.
As shown in (a) and FIG. 69 (b), since the end of the element isolation region is exposed twice, when etching is performed with, for example, a hydrofluoric acid-based etchant, a large depression is formed in this portion. Edge corners of the element region are exposed. Therefore, the electric field is concentrated on the edge corners, and the characteristics of the transistor are degraded, such as a decrease in the reliability of the gate insulating film.

As described above, in the method of manufacturing a transistor, after forming the source / drain regions using the dummy gate pattern, the gate insulating film and the gate wiring are formed in the trench formed by removing the dummy gate pattern. Conventionally, there has been a problem that a large dent is formed at an end of an element isolation region and an edge corner of the element region is exposed, so that an electric field is concentrated on the edge corner and deterioration of transistor characteristics occurs.

Next, another problem of the manufacturing process of the MOS transistor using the dummy gate will be described.

The first problem is as follows.

In the process of manufacturing a MOS transistor used in a DRAM or the like, as shown in FIG. 70A, an etching-resistant side wall insulating film 507 is formed on the side surface of a dummy gate 505, and an interlayer formed later is formed. Even if there is some misalignment when forming a contact hole to the gate electrode or the source / drain region in the insulating film, the short-circuit between the gate electrode and the source / drain region is prevented by the presence of the sidewall insulating film 507. , Thereby improving the degree of integration.

Heretofore, in the manufacturing process of the damascene gate transistor, the side wall insulating film 507 is formed on the side surface (the oxide film is formed) of the dummy gate 505 composed of the amorphous silicon film 505a and the silicon nitride film 505b. Indicates that when CMP is applied to the interlayer insulating film,
In order to prevent the sidewall insulating film 507 from being exposed at the end of the MP, the height of the sidewall insulating film 507 is set to the RI at the time of forming the sidewall insulating film 507.
E had to control.

However, as shown in FIG.
If the upper portion of the sidewall insulating film 507 is exposed at the end of P,
As shown in FIG. 70C, when the dummy gate 505 was removed, the sidewall insulating film 507 also disappeared, and the margin for the etching variation was low.

In the case of a normal transistor, when a silicon nitride film is used as an etching stopper formed on the side wall insulating film 507 of the gate electrode and the gate electrode, the silicon nitride film has a very low dielectric constant, is miniaturized, and has a high speed. There was a concern that the reduction of the parasitic capacitance was insufficient to satisfy the demand for operation.

The second problem is as follows.

In the manufacturing process of the damascene gate transistor, since the dummy gate also functions as a CMP stopper when the interlayer insulating film is flattened, the dummy gate (upper layer) is shown in FIGS. 70 (a) to 70 (c). Like the example shown,
A silicon nitride film 505b is used (FIG. 71).
(A)). Normally, a silicon nitride film 520 is generally used as a liner formed on the side surface of the dummy gate 505, but in the case of a damascene gate transistor, the gate liner 5 is removed when the dummy gate is removed (FIG. 71B).
20 is also etched at the same time.

Thereafter, the polycrystalline or amorphous silicon film 505a under the dummy gate is removed (FIG. 71 (c)).
Further, when the silicon oxide film 504 used as a buffer is removed, the dummy gate 50 is formed because the silicon nitride film 520 does not have a liner above the groove where the gate is formed.
The dimension is wider than the dimension 5 by t (FIG. 71D).

In a semiconductor integrated circuit, the capacity can be increased as the individual semiconductor elements are miniaturized and the degree of integration is improved. However, in the above-described conventional example, the dimensions of the actually completed transistor are larger than the design width of the dummy gate, which is disadvantageous for miniaturization.

For example, the thickness of the buffer oxide film of the dummy gate is 10 nm, and the width of the silicon nitride film liner is 1
Assuming that the thickness is 5 nm, in addition to the thickness of the liner of 15 nm, the extension of the buried insulating film around the gate when the buffer oxide film is removed is 10 nm × 1.3 = 13 nm.
m becomes wider than the designed gate size. 0.1μ
Considering the transistor of the m generation, at a place where the gate wiring is adjacent, the distance between the gate wirings is narrower by 28 nm × 2 = 56 nm than the designed distance between the gate wirings of 0.1 μm. It is disadvantageous in frequency operation.

Also, in forming a contact to the source / drain region, the margin for patterning the interlayer insulating film for forming the contact is reduced, and the minimum design dimension must be loosened accordingly. This is also a disadvantage for high integration.

Further, in order to eliminate the above spread of the upper portion of the gate wiring, it becomes necessary to perform over-etching by CMP or the like to a level where the gate groove is not widened. Therefore, it is not possible to gain the gate height,
For example, when the dummy gate is formed of polycrystalline silicon having a thickness of 200 nm and a silicon nitride film having a thickness of 200 nm, the gate height after forming the gate is extremely low. As a result, the resistance of the gate wiring increases, the power consumption increases, and the dielectric characteristics deteriorate.

The third problem is as follows.

Semiconductor device, especially MOS using silicon
The miniaturization of the FET device has rapidly progressed since polycrystalline silicon has been adopted as a gate electrode material. The manufacturing process of the metal gate transistor that was used before adopting the polycrystalline silicon gate,
This is shown below with reference to FIG.

First, an element isolation insulating film 602 and a p-type diffusion layer 603 are formed on a silicon substrate 601 (FIG. 72).
(A)). Next, n-type diffusion layers (source and drain regions) 605 are formed by ion-implanting n-type impurities such as arsenic using the photoresist 604 as a mask (FIG. 7).
2 (b)).

After the impurities implanted in the n-type diffusion layers (source and drain regions) 605 are activated by a heat process at 900 ° C. or more, the silicon substrate 6 is subjected to a thermal oxidation process.
A silicon oxide film 606 is formed by oxidizing the surface 01, and a metal layer 607 such as aluminum is deposited. The metal layer 607 is patterned by a photolithography process while leaving a region between the n-type impurity diffusion layers (source and drain regions) to form a metal gate electrode 607.

Finally, an insulating film 6 such as a silicon oxide film is formed on the entire surface.
08, a contact hole is opened, and a metal wiring layer 6 is formed.
09 to complete the transistor.

According to such a process, it is necessary to activate the source and drain diffusion layers 605 before forming the metal gate electrode 607.
The positional relationship between the source / drain diffusion layer 605 and the gate electrode 607 is determined by a photolithographic process.
Therefore, as shown in FIGS. 72 (c) and 72 (d), the source / drain diffusion layer 605 and the gate electrode 607 need to overlap by an allowance “d” in the photolithographic process. Further, in such a process, a so-called LDD (Light) is used in which the impurity concentration of the diffusion layer at the end of the gate is reduced and the diffusion depth is reduced.
Since it is impossible to adopt a (ly Doped Drain) structure, there is also a problem that it is difficult to suppress the short channel effect.

For these reasons, polycrystalline silicon having high heat resistance and easy to be finely processed compared to metals such as aluminum has been used for the gate electrode. An example of a method for manufacturing a transistor using polycrystalline silicon for a gate electrode is described below with reference to FIGS.

First, an element isolation insulating film 702 and a p-type diffusion layer 703 are formed on a silicon substrate 701 (FIG. 73).
(A)).

Next, the silicon substrate 7 is subjected to a thermal oxidation process.
Oxidation of the surface of the silicon oxide film 704
Is formed, and a polycrystalline silicon layer 705 is deposited. The polycrystalline silicon layer 705 is patterned by a photolithographic process to form a gate electrode 705, and the surface of the silicon substrate 701 and the periphery of the polycrystalline silicon gate electrode 705 are oxidized by thermal oxidation or the like to form a silicon oxide film 706.
And ion implantation of an n-type impurity such as arsenic
Impurity activation by heat treatment at 0 ° C. or more is performed to form a shallow n ⁻ -type diffusion layer (LDD region) 7 with a relatively low impurity concentration
07 is formed (FIG. 73B).

By depositing an insulating film such as a silicon oxide film on the entire surface and performing anisotropic etching, a silicon oxide film side wall 708 is formed on the side surface of the polycrystalline silicon gate electrode 705.
Is formed, and ion implantation and impurity activation by heat treatment at 900 ° C. or more are performed again using the gate electrode 705 and the side wall 708 of the silicon oxide as a mask, whereby n ⁺
Type impurity diffusion layers (source / drain regions) 709 are formed, and the polysilicon gate electrode 705 is also n-type.
Doping is performed to the ⁺ type (FIG. 73 (c)).

Finally, an insulating film 7 such as a silicon oxide film is formed on the entire surface.
10, a contact hole is opened, and a metal wiring layer 7 is formed.
11 to complete the transistor (FIG. 73).
(D)).

According to this process, not only the processability of the gate electrode is improved as compared with the process shown in FIG. 72, but also the impurity can be activated by ion implantation using the polycrystalline gate electrode as a mask. Therefore, the alignment of the gate electrode with the source / drain diffusion layers can be performed in a self-aligned manner, and there is no need for a margin for alignment in the photolithography process. Further, as a countermeasure against the short channel effect caused by miniaturization of an element, it is easy to use a so-called LDD structure in which the impurity concentration of the source / drain diffusion layer at the end of the gate electrode is low and the depth of the diffusion layer is small. Become.

However, as devices have been miniaturized as in recent years and a transistor having a gate length of 0.1 μm or less has been manufactured, the parasitic resistance of a polycrystalline silicon gate electrode has become so large that it cannot be ignored. This is a factor of deteriorating the element performance. To solve this problem,
It is necessary to employ a low-resistance material as the material of the gate electrode, and it has been desired to employ it again as the material of the gate electrode. However, in the manufacturing method as shown in FIG. 72, since it is difficult to manufacture a fine element as described above, the alignment between the source and drain diffusion layers and the gate electrode can be performed in a self-aligned manner, and A process for forming a gate electrode after the completion of the activation has been required.

In a conventional transistor, a silicon oxide film formed by thermal oxidation has been used as a gate insulating film. However, in a generation having a gate length of 0.1 μm or less, a required gate insulating film has a thickness of 5 nm or less. Since the thickness becomes extremely thin, there arises a problem that a tunnel current is generated. In order to solve this problem, it is necessary to increase the physical film thickness using a film having a higher dielectric constant than a silicon oxide film, for example, a high dielectric film such as a tantalum oxide film (Ta ₂ O ₅ ). It becomes. For a high dielectric insulating film such as this tantalum oxide film, it is necessary to avoid a heat treatment for activating impurities from the viewpoint of heat resistance. Therefore, it is necessary to form the gate insulating film after forming the source and drain diffusion layers. Is desirable.

To satisfy such requirements, a transistor manufacturing process as shown in FIGS. 74 and 75 has been proposed.

An element isolation insulating film 8 is formed on a silicon substrate 801.
02, forming a p-type diffusion layer 803 (FIG. 74)
(A)).

Next, the silicon substrate 8 is subjected to a thermal oxidation process.
01, the silicon oxide film 804 is oxidized.
Is formed, and a silicon nitride film 805 is deposited and patterned to form a dummy gate electrode. Using the dummy gate 805 as a mask, an n-type impurity such as arsenic is ion-implanted into the p-type diffusion layer 803, and the impurity is activated by heat treatment at 900 ° C. or more, thereby forming an n ⁻ -type LDD diffusion layer 806. (FIG. 74 (b)).

By depositing a silicon oxide film on the entire surface and performing anisotropic etching, a sidewall silicon oxide film 807 is formed on the side surface of the silicon nitride dummy gate 805.
Using the gate electrode 805 and the side wall 807 of the silicon oxide film as a mask, ion
By performing impurity activation by heat treatment at 0 ° C. or more, n ⁺ -type impurity diffusion layers (source and drain regions) 8 are formed.
08 (FIG. 74 (c)).

Next, a silicon oxide film 809 is deposited on the entire surface, and the silicon oxide film 809 is polished and flattened using the dummy gate 805 made of a silicon nitride film as a stopper. In the polishing step of the silicon oxide film 809, a silicon nitride film is preferable as a material of the dummy gate to be used as a stopper (FIG. 74).
(D)).

The exposed silicon nitride film 805 is removed by treatment with hot phosphoric acid or the like to form a groove in the gate electrode formation region (FIG. 75 (e)).

Further, the silicon oxide film 804 remaining in the groove region is removed by etching with hydrofluoric acid or the like to expose the surface of the silicon substrate 801 (FIG. 75 (f)).

A high dielectric insulating film 810 such as a tantalum oxide film is deposited on the entire surface, and a titanium nitride film 8 as a diffusion barrier layer is formed.
11. An aluminum layer 812 as a gate electrode is deposited, and the aluminum and titanium nitride films other than the groove portions are removed by CMP polishing or the like (FIG. 75 (g)).

A silicon oxide film 813 is deposited on the entire surface, a contact hole is opened, a metal wiring layer 814 is formed, and a transistor is completed (FIG. 75 (h)).

According to the above-described process, a gate electrode using a low-resistance metal can be formed after the formation of the source and drain diffusion layers, and the alignment between the source and drain diffusion layers and the gate electrode can be performed in a self-aligned manner. become.

However, in this process, as shown in FIG. 75 (f), when the dummy gate 805 is removed and the silicon substrate 801 is exposed, the dimension (L) of the dummy gate pattern formed first by fine processing Since the width (L ') of the groove is wider than that of the groove, it is difficult to form a fine gate. This problem is caused by the fact that the buried material 810 around the sidewall insulating film 807 and the dummy gate pattern is etched with an etching selectivity with respect to the silicon nitride film as the material of the dummy gate pattern 805 and the silicon oxide film 804 under the dummy gate electrode. Although the use of a material seems to be good or can be solved, it is extremely difficult to newly adopt a material having such characteristics in a semiconductor manufacturing process.

[0056]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to alleviate the electric field concentration at the edge corners of the element region and prevent the transistor characteristics from deteriorating. It is an object of the present invention to provide a possible method for manufacturing a semiconductor device.

Another object of the present invention is to increase a margin for variation in forming a side wall on a side surface of a gate electrode,
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which makes it possible to manufacture a semiconductor device with high yield.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can manufacture a fine semiconductor device without expanding a groove when removing a dummy gate layer. .

Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can manufacture a fine semiconductor device without increasing the parasitic capacitance of an element.

[0060]

In order to solve the above-mentioned problems, the present invention provides a method of forming a first film and a second film on a semiconductor substrate, and a method of forming the first film and the second film on a semiconductor substrate. Forming a first trench by selectively removing an upper portion of the semiconductor substrate; filling a first insulating film in the first trench to form an element isolation region; Patterning the second film surrounded by a to form a dummy gate layer, and introducing an impurity into the semiconductor substrate using the dummy gate layer as a mask;
Forming a second insulating film on the semiconductor substrate surrounded by the dummy gate layer and the first insulating film; removing the dummy gate layer and the first film;
Forming a second groove, forming a gate insulating film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulating film in the second groove And a method for manufacturing a semiconductor device comprising:

According to the invention, since the exposure of the edge corner portion of the element region can be suppressed, it is possible to prevent the characteristic deterioration of the transistor due to the electric field concentration at the edge corner portion. In addition, since exposure of the substrate surface is suppressed even in the channel plane portion, the roughness of the interface between the substrate and the gate insulating film is reduced, so that a transistor with a high operation speed can be obtained.

After the step of forming the gate electrode, the method may further include a step of forming a wiring portion connected to the gate electrode on at least the gate electrode and the first insulating film.

Preferably, at least a part of the second film is a semiconductor film (silicon film), particularly an amorphous silicon film. By using a silicon film, a dummy pattern can be removed with high selectivity to a silicon oxide film, a silicon nitride film, or the like. Further, by using an amorphous silicon film, it is possible to reduce processing variations when processing a dummy pattern.

Further, the present invention provides a step of forming a gate insulating film and a first conductive film on a semiconductor substrate, and selectively forming the first conductive film, the gate insulating film and the upper portion of the semiconductor substrate on the semiconductor substrate. Removing, forming a first trench, burying a first insulating film in the first trench to form an element isolation region, and forming a first isolation film on the first conductive film and the element isolation region. Forming a dummy film; and forming the dummy film and the first film.
Forming an island-like layer by patterning the conductive film of step (a), introducing an impurity into the semiconductor substrate using the island-like layer as a mask, and forming the island-like layer and the first layer.
Forming a second insulating film on the gate insulating film surrounded by the insulating film; removing the dummy film to form a second groove; and forming the second groove in the second groove. Forming a second conductive film on the first conductive film, and forming a gate electrode including the first conductive film and the second conductive film. I do.

According to the invention, since the exposure of the edge corner portion of the element region can be suppressed, it is possible to prevent the deterioration of the transistor characteristics due to the electric field concentration at the edge corner portion. Further, since the upper surface of the gate forming pattern can be flattened (the depression on the element region can be eliminated), the step of forming the second insulating film and the subsequent steps become easy, and the gate wiring can be easily formed. Planarization can be achieved.

The present invention also provides a step of forming a first groove in a semiconductor substrate, a step of burying a first insulating film in the first groove to form an element isolation region, Forming a first film and a second film on the surface of the enclosed semiconductor substrate;
Forming a film, forming a dummy gate layer by patterning the second film, introducing an impurity into the semiconductor substrate using the dummy gate layer as a mask, Forming a second insulating film on the first film surrounded by a gate layer and the first insulating film; removing the dummy gate layer and a portion of the first film below the dummy gate layer; Forming a second groove, forming a gate insulating film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulating film in the second groove And a method for manufacturing a semiconductor device comprising:

The present invention also provides a step of forming a dummy gate layer on a semiconductor substrate, a step of forming a dummy sidewall on a side surface of the dummy gate layer, a step of depositing an interlayer insulating film on the entire surface, Removing the insulating film until the upper surface of the dummy gate layer is exposed; removing the dummy gate layer to form a groove; forming a gate electrode in the groove; A method of manufacturing a semiconductor device, comprising: removing a cavity to form a cavity; and filling the cavity with a sidewall material to form a sidewall.

The present invention also provides a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of forming a dummy sidewall on a side surface of the gate electrode. Depositing an interlayer insulating film on the entire surface, removing the interlayer insulating film until the upper surface of the gate electrode is exposed, removing the dummy dummy sidewall to form a cavity, Forming a sidewall by filling with a sidewall material.

Further, according to the present invention, there is provided a side wall insulating film having an etching selectivity between a step of forming a dummy gate layer on a semiconductor substrate and a material forming the dummy gate layer on a side surface of the dummy gate layer. Forming an interlayer insulating film over the entire surface; and removing the interlayer insulating film until the upper surface of the dummy gate layer is exposed.
Removing the dummy gate layer and forming a groove, forming a gate insulating film on the bottom surface of the groove, and forming a gate electrode in the groove having the gate insulating film formed on the bottom surface. Provided is a method for manufacturing a semiconductor device having the same.

Further, according to the present invention, there is provided a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and the gate electrode formed on a side surface of the gate electrode. A semiconductor device includes an insulating layer made of the same material as a gate insulating film and a silicon nitride film formed on the insulating layer.

Further, according to the present invention, a step of forming a dummy gate made of a first silicon nitride film on a semiconductor substrate, a step of forming a first silicon oxide film on the entire surface, and a step of forming a second silicon Forming a nitride film, forming an interlayer insulating film on the entire surface, polishing the interlayer insulating film until the dummy gate is exposed, and removing the upper portions of the first and second silicon nitride films. Removing, forming a first groove, filling the first groove with a second silicon oxide film, and performing anisotropic etching on the second silicon oxide film to form the second groove. Exposing the dummy gate while leaving the second silicon oxide film on the silicon nitride film;
Forming a groove, forming a gate insulating film on the bottom surface and side surfaces of the second groove, and forming a gate electrode in the second groove having the gate insulating film formed on the bottom surface and side surfaces. And a method for manufacturing a semiconductor device comprising:

[0072]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described.

FIG. 1A to FIG. 3I are cross-sectional views showing the manufacturing steps of the first embodiment. In these figures, the figure on the left shows a cross section of the transistor in the gate length direction.
The diagram on the right shows a cross section of the transistor in the gate width direction.

First, an SiO ₂ film 102 having a thickness of about 10 nm is formed on the surface of a Si substrate 101 by a thermal oxidation method or the like, and then an amorphous Si film 103 and a Si ₃ film are formed by an LPCVD method.
An N ₄ film 104 is deposited to a thickness of about 200 nm and about 100 nm, respectively. The amorphous Si film 103 may contain an impurity such as phosphorus or arsenic (FIG. 1A).

Next, for example, lithography and RIE
SiO ₂ film 102, amorphous Si
The film 103 and the Si ₃ N ₄ film 104 are processed into an island shape (FIG. 1B).

Next, the Si substrate 101 is etched in a self-aligned manner with respect to the previously formed island pattern by the RIE method to form the island portion 105 and the groove portion 106 for element isolation. Subsequently, after forming a SiO ₂ film (not shown) on the groove surface by a thermal oxidation method, for example,
The SiO ₂ film is formed in the groove 10 by the PCVD method and the CMP method.
6 to form a buried element isolation insulating film 107. After thermal oxidation or after removing the thermal oxide film by dilute hydrofluoric acid treatment or the like, a thin Si ₃ N ₄ film (not shown) of about 10 nm is deposited by LPCVD or the like. May be formed. By forming the Si ₃ N ₄ film on the side wall of the groove 106 in this manner, it becomes difficult to expose the element isolation end in a dummy pattern removing step described later, thereby improving the reliability. Further, since the channel width can be fixed, variation in a subsequent step can be suppressed (FIG. 1C).

Next, by partially removing the Si ₃ N ₄ film 104 and the amorphous Si film 103 by lithography, RIE, or the like, a dummy gate electrode pattern 108 is formed in the gate electrode formation planned region, and Grooves 109 are formed on both sides (FIG. 2D).

Next, using the dummy gate electrode pattern 108 as a mask, for example, phosphorus ion implantation is performed at 70 keV,
The process is performed at about × 10 ¹³ cm ⁻² to form the n ⁻ type diffusion layer 110. Subsequently, after depositing a Si ₃ N ₄ film on the entire surface, RIE is performed on the entire surface to form a sidewall insulating film 111 having a thickness of about 20 nm on the sidewall of the dummy gate electrode pattern 108. Thereafter, using the dummy gate electrode pattern 108 and the sidewall insulating film 111 as a mask, for example, arsenic ion implantation is performed at about 30 keV and 5 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type diffusion layer 112, thereby forming a so-called LDD structure. (FIG. 2E).

Next, the CV to be the interlayer insulating film 113 is formed on the entire surface.
A D-SiO ₂ film is deposited, for example, in a thickness of about 300 nm, and densification is performed in an N ₂ atmosphere at, for example, about 800 ° C. for about 30 minutes. Thereafter, the entire surface is planarized by CMP to expose the surface of the amorphous Si film 103 of the dummy gate electrode pattern. Subsequently, the exposed amorphous Si film 10
3 is selectively removed using RIE or KOH aqueous solution or the like to form a groove 114. Thereafter, a resist film (not shown) is formed in a desired region, and channel ions of impurities are implanted only into the channel region using this resist film, interlayer insulating film 113 (SiO ₂ film) and sidewall insulating film 111 as a mask. . Then, for example, 800
C. for about 10 seconds to form a channel impurity layer 11
5 is activated (FIG. 2 (f)).

Next, the dummy insulating film 102 (SiO ₂ film) formed in the groove 114 is removed (FIG. 3).
(G)).

Subsequently, a high dielectric film such as Ta ₂ O _{5 is} deposited on the entire surface as a gate insulating film 116 to a thickness of about 20 nm, and a metal film such as Ru is deposited on the entire surface as a gate electrode 117 thereon. . After that, the entire surface is subjected to CMP to form the gate insulating film 116 and the gate electrode 11.
7 is buried in the groove 114 (FIG. 3H).

Next, a metal film of, for example, Al is deposited on the entire surface, and is patterned to form a wiring 118 (FIG. 3I).

Thereafter, a SiO ₂ film is deposited to a thickness of about 200 nm as an interlayer insulating film, and contacts to the source / drain and gate electrodes are opened. Further, wiring is patterned and a passivation film is deposited to obtain a basic structure of the transistor.

According to the above-described manufacturing method, since the device isolation end of the channel region is exposed only once, a recess is hardly formed between the device region of the Si substrate and the device isolation insulating film. The reliability of the gate insulating film at the end is improved. Further, since the surface of the silicon substrate is exposed only once in the channel plane portion, a transistor having a smooth interface between the silicon substrate and the gate insulating film and having a high operation speed can be formed.

Next, a second embodiment of the present invention will be described.

First, a first specific example of the second embodiment will be described with reference to FIGS. 4 to 6 and FIG. FIGS. 4A to 5H are cross-sectional views in the gate length direction (cross-sectional views taken along line AA ′ in FIG. 18) illustrating the manufacturing process.
FIG. 6 is a cross-sectional view in the gate width direction corresponding to FIG. 5H (a cross-sectional view taken along the line BB ′ in FIG. 18).

First, an amorphous silicon film 203 serving as a dummy gate pattern is deposited to a thickness of 100 nm on a silicon substrate 201 via a buffer oxide film 202 (FIG. 4).
(A)).

Next, a resist pattern (not shown) for forming an element region is formed, and the amorphous silicon film 203 and the buffer oxide film 2 are formed using this resist pattern as a mask.
02 and the silicon substrate 201 are etched by the reactive ion etching method, and
4 and a groove 205 to be an element isolation region are formed (FIG.
(B)).

Next, a buried insulating film 206 is deposited on the entire surface, and is flattened to the upper surface of the amorphous silicon film 203 by chemical mechanical polishing or the like, thereby burying the element isolation region. In the present invention, since the amorphous silicon film 203 is not removed here, the corner of the element region is not exposed (FIG. 4C).

Next, a gate resist pattern (not shown) is formed, and RIE is performed using this resist pattern as a mask.
The dummy gate pattern 207 and the groove 208
To form Subsequently, impurity ions are implanted into the silicon substrate 201 using the dummy gate pattern 207 as a mask to form a source / drain diffusion layer (not shown) of the transistor (FIG. 4D).

Next, a buried insulating film 209 is deposited,
The upper surface of the amorphous silicon film 203 serving as a dummy gate pattern is polished by MP and buried in the groove 208 (FIG. 4E).

Subsequently, the amorphous silicon film 203 serving as a dummy gate pattern is removed by RIE, CDE or the like to form a groove 210 (FIG. 4F). Next, if necessary, ions are implanted only into the channel portion to control the impurity concentration. Further, the exposed buffer oxide film 202 is
It is removed using H ₄ F or the like (FIG. 5 (g)).

Next, a gate insulating film 211 is formed by thermally oxidizing the surface of the silicon substrate 201 or depositing a gate insulating material by CVD or the like. Subsequently, a gate electrode material is deposited on the entire surface, and the gate electrode material is buried through the gate insulating film 211 at the place where the dummy gate pattern was formed. Thereafter, a gate wiring resist pattern (not shown) is formed, and the gate electrode material is processed into a desired shape to complete the gate wiring 212 (FIGS. 5 (g) and 6).

Thereafter, the process is the same as in a normal transistor manufacturing process. After depositing an interlayer insulating film, a contact hole and a wiring are formed as necessary.

Next, a second specific example of the second embodiment will be described with reference to FIGS. 7 to 9 and FIG. FIGS. 7A to 8H are cross-sectional views (cross-sectional views taken along the line AA ′ in FIG. 19) showing the manufacturing process in the gate length direction.
FIG. 9 is a cross-sectional view in the gate width direction (a cross-sectional view taken along line BB ′ of FIG. 19) corresponding to FIG.

In this embodiment, the side wall insulating film is formed in the first embodiment. Components that are substantially the same as or correspond to the first specific example are denoted by the same reference numerals, and detailed description thereof will be omitted.

The steps up to the step shown in FIG. 7A and the step in the middle of FIG. 7B are the same as those shown in FIGS. 4A and 4B shown in the first specific example.

After the step shown in FIG. 4B, a silicon nitride film is deposited to a thickness of 100 nm, and the silicon nitride film is receded by RIE to cover the periphery of the island portion 204.
21 are formed. The height of the side wall insulating film 221 is higher than the upper surface of the island-shaped semiconductor substrate, and
3 (FIG. 7B).

The subsequent steps are basically the same as in the first embodiment. That is, the buried insulating film 206 is buried in the element isolation region (FIG. 7C). Subsequently, a dummy gate pattern 207 and a trench 208 are formed, and a source / drain diffusion layer (not shown) is formed by ion implantation using the dummy gate pattern 207 as a mask (FIG. 7D). Subsequently, a buried insulating film 209 is deposited and buried in the trench 208 by CMP (FIG. 7E). Next, the amorphous silicon film 203 is removed and the trench 21 is removed.
0 (FIG. 7F), and the exposed buffer oxide film 202 is further removed (FIG. 8G). In this example, Si
_{Since the 3} N ₄ film surrounds the periphery of the element region as the side wall insulating film 221, corners of the element region are hardly exposed when the amorphous silicon film 203 and the buffer oxide film 202 are removed. Next, if necessary, ions are implanted only into the channel portion to control the impurity concentration. Subsequently, a gate insulating film 211 and a gate wiring 212 are formed (FIGS. 8H and 9). Thereafter, as in the normal transistor manufacturing process, an interlayer insulating film is deposited, and contact holes and aluminum wiring are formed as necessary.

Next, a third specific example of the second embodiment will be described with reference to FIG. FIG. 10 (a),
(B) is a sectional view in the gate length direction showing a part of the manufacturing process.

In this embodiment, the oxide film 222 is formed as shown in FIG. 10A immediately before the formation of the sidewall Si ₃ N ₄ film 221 in the process of FIG. 7B of the second embodiment. It is characterized by doing. By this oxide film 222, Si
The adhesion between the ₃ N ₄ film 221 and the interface of the element region is improved,
_The 3N ₄ film can be prevented from peeling off. Other steps are basically the same as those of the second specific example, and finally, a shape as shown in FIG. 10B is obtained.

Next, a fourth example of the second embodiment will be described with reference to FIGS. 11 to 13 and FIG. FIGS. 11A to 12I are cross-sectional views (cross-sectional views taken along the line AA ′ in FIG. 20) showing the manufacturing process, and FIG. 13 is a gate corresponding to FIG. FIG. 21 is a cross-sectional view in the width direction (a cross-sectional view taken along line BB ′ of FIG. 20).

First, an amorphous silicon film 203 serving as a dummy gate pattern is deposited to a thickness of 100 nm on a silicon substrate 201 via a buffer oxide film 202 (FIG. 11).
(A)).

Next, a resist pattern (not shown) for forming an element region is formed, and the amorphous silicon film 203, the buffer oxide film 2
02 and the silicon substrate 201 are etched by the reactive ion etching method, and
4 and a trench 205 serving as an element isolation region are formed (FIG. 1).
1 (b)).

Next, a buried insulating film 206 is deposited on the entire surface and planarized to the upper surface of the amorphous silicon film 203 by CMP or the like to bury the element isolation region (FIG. 11C).

Next, an amorphous silicon film 23 is formed on the entire surface.
1 is deposited. At this time, the amorphous silicon film 20
3 and the amorphous silicon film 231 are in close contact with each other (FIG. 11D).

Next, a resist pattern (not shown) for a gate wiring is formed, and RIE, CDE, etc. are performed using this resist pattern as a mask to form an amorphous silicon film 2.
03 and the amorphous silicon film 231 are simultaneously etched to form a dummy gate pattern 207 and a groove 208. Subsequently, impurity ions are implanted into the silicon substrate 201 using the dummy gate pattern 207 as a mask to form a source / drain diffusion layer (not shown) of the transistor (FIG. 11E).

Next, a buried oxide film 209 is deposited,
The upper surface of the amorphous silicon film 231 serving as a dummy gate pattern is polished by MP (FIG. 11F).

Next, the amorphous silicon film 203 and the amorphous silicon film 2 serving as dummy gate patterns are formed.
31 is removed by RIE, CDE or the like to form a groove 210. At this time, since the amorphous silicon film 203 and the amorphous silicon film 231 are in close contact with each other, they are simultaneously removed (FIG. 12G).

Next, if necessary, ions are implanted only into the channel portion to control the impurity concentration. Then, the exposed buffer oxide film 202 is removed using NH ₄ F or the like (FIG. 12H).

Subsequently, a gate insulating film 211 is formed by thermally oxidizing the surface of the silicon substrate 201 or depositing a gate insulating material by CVD or the like. Subsequently, a gate electrode material is deposited on the entire surface, and the gate electrode material is buried through the gate insulating film 211 at the place where the dummy gate pattern was formed. Thereafter, a gate electrode material is buried and an oxide film 209 is embedded.
The gate wiring 212 is formed by performing CMP up to the upper surface of the substrate. The gate wiring 212 thus formed
Has no dent on the element region as shown in the first specific example (see FIG. 6), and is flattened as shown in FIG. 13 (FIGS. 12 (i) and 13).

After that, the process is the same as in a normal transistor manufacturing process. After an interlayer insulating film is deposited, a contact hole and an aluminum wiring are formed as necessary.

Next, a fifth example of the second embodiment will be described with reference to FIGS. 14 to 16 and FIG. FIGS. 14A to 15H are cross-sectional views (cross-sectional views taken along the line AA ′ in FIG. 21) showing the manufacturing process, and FIG. 16 is a gate corresponding to FIG. FIG. 22 is a cross-sectional view in the width direction (a cross-sectional view taken along line BB ′ of FIG. 21).

In this embodiment, the side wall insulating film is formed in the fourth embodiment. Components that are substantially the same as or correspond to the fourth specific example are given the same numbers, and detailed descriptions thereof are omitted.

The steps up to the step of FIG. 14A and the step in the middle of FIG. 14B are the same as those of FIGS. 11A and 11B shown in the fourth specific example.

After the step shown in FIG. 11B, a silicon nitride film is deposited to a thickness of 100 nm, and this is receded by RIE to form a sidewall insulating film 221 so as to cover the periphery of the island portion 204. The height of the sidewall insulating film 221 is higher than the upper surface of the island-shaped semiconductor substrate, and
03 or below (FIG. 14B).

The subsequent steps are basically the same as in the fourth embodiment. That is, the buried insulating film 206 is buried in the element isolation region (FIG. 14C), and the amorphous silicon film 231 is deposited (FIG. 14D). Subsequently, a dummy gate pattern 207 and a trench 208 are formed, and a source / drain diffusion layer (not shown) is formed by ion implantation using the dummy gate pattern 207 as a mask (FIG. 14E). Subsequently, the buried insulating film 209
(FIG. 14F), the amorphous silicon films 203 and 231 are removed to form a groove 210 (FIG. 15G).

Next, if necessary, ions are implanted only into the channel portion to control the impurity concentration. Further, the exposed buffer oxide film 202 is removed (FIG. 15H). In this example, since the Si ₃ N ₄ film surrounds the periphery of the element region as the sidewall insulating film 221, the corner of the element region is hardly exposed when the amorphous silicon film 203 and the buffer oxide film 202 are removed. Subsequently, a gate insulating film 211 and a gate wiring 212 are formed (FIG. 15).
(I), FIG. 16). Also in this example, as in the fourth specific example, the gate wiring 212 is flattened. Thereafter, as in the normal transistor manufacturing process, an interlayer insulating film is deposited, and contact holes and aluminum wiring are formed as necessary.

Next, a sixth specific example of the second embodiment will be described with reference to FIG. FIG. 17 (a),
(B) is a sectional view in the gate length direction showing a part of the manufacturing process.

This example is different from the fifth example shown in FIG.
In this step, an oxide film 242 is formed as shown in FIG. 17A immediately before the formation of the sidewall Si ₃ N ₄ film 221. With this oxide film 242, S
The adhesion between the i ₃ N ₄ film 221 and the interface of the element region is improved,
Peeling of the i ₃ N ₄ film can be prevented. Other steps are basically the same as those of the fifth specific example, and finally a shape as shown in FIG. 17B is obtained.

In each of the specific examples of the second embodiment, the flattening method is not limited to CMP but may be etch-back by chemical dry etching, and the source / drain regions may be formed by ion implantation. The gas diffusion method may be used without limitation. Further, the gate insulating film is not limited to a single layer, and may have a laminated structure such as a combination of a silicon insulating film and a high dielectric film.

Next, a third embodiment of the present invention will be described.

First, a first specific example of the third embodiment will be described with reference to FIGS. 22 to 24 and FIG. FIGS. 22A to 23H are cross-sectional views (cross-sectional views taken along the line AA ′ in FIG. 35) showing the manufacturing process, and FIG. 24 is a gate corresponding to FIG. FIG. 36 is a cross-sectional view in the width direction (a cross-sectional view taken along line BB ′ of FIG. 35).

First, a silicon film 303 made of polycrystalline silicon or amorphous silicon containing impurities to be a part of a gate wiring is deposited on a silicon substrate 301 via a gate insulating film 302 to a thickness of 100 nm. Further, if necessary, an impurity is implanted into the substrate before depositing the gate electrode to control the substrate concentration (FIG. 22A).

Next, a resist pattern (not shown) for forming an element region is formed, and using this resist pattern as a mask, the silicon film 303, the gate insulating film 302, and the silicon substrate 301 are etched by reactive ion etching. , An island portion 304 and a groove portion 305 are formed.
After removing the resist pattern, the periphery of the island formed as necessary is oxidized to improve the surface condition (FIG. 2).
2 (b)).

Next, a buried insulating film 306 is deposited on the entire surface and planarized to the upper surface of the silicon film 303 by CMP or the like to bury the element isolation region. In the present invention, since the silicon film 303 is not removed at this time, the corner of the element region is not exposed (FIG. 22C).

Next, a Si ₃ N ₄ film 308 is deposited on the entire surface. At this time, the silicon film 303 and the Si ₃ N ₄ film 308
And the upper surface of the Si ₃ N ₄ film 308 is finished flat (FIG. 22D).

Next, a resist pattern (not shown) is formed, and the silicon film 303 and the Si ₃ N ₄ film 308 are simultaneously etched by RIE or the like using the resist pattern as a mask, thereby forming a gate forming pattern 309. And a groove 310 are formed. After removing the resist pattern, the side portions are oxidized as necessary to improve the surface condition. Subsequently, using the gate forming pattern 309 as a mask, impurity ions are implanted into the silicon substrate 301 to form a source / drain diffusion region (not shown) of the transistor (FIG. 22E).

Next, a buried oxide film 311 is deposited on the entire surface, and is planarized to the upper surface of the Si ₃ N ₄ film 308 by CMP or the like. At this time, the buried insulating film 311 does not remain on the upper surface of the Si ₃ N ₄ film 308 (FIG. 22F).

Next, the Si ₃ N ₄ film 308 is heated with hot phosphoric acid.
Is removed to expose the upper surface of the silicon film 303, and the groove 31 is removed.
2 (FIG. 23 (g)).

Next, in order to improve the connection between the silicon film 303 and the gate wiring material to be buried later, the upper surface of the silicon film 303 is subjected to a cleaning treatment as needed, and the gate wiring material 313 is buried in the groove 312. Thereafter, planarization is performed to the upper surface of the buried oxide film 311 by CMP or the like, and a gate wiring including the electrode portion 303 and the wiring portion 313 is formed. At this time, the upper surface of the gate wiring (the upper surface of the wiring portion 313) is finished flat (FIGS. 23 (h) and 24).

If the material forming the wiring member 313 is a metal such as W, for the purpose of preventing a reaction with a-Si or the like forming the electrode portion 303, as shown in FIGS.
The barrier metal 321 may be provided.

The subsequent steps are the same as those in the normal transistor manufacturing process. After depositing an interlayer insulating film, contact holes and aluminum wiring are formed as necessary.

Next, a second specific example of the third embodiment will be described with reference to FIGS. FIG.
37 (a) to (d) are cross-sectional views (cross-sectional views taken along the line AA 'in FIG. 37) showing the manufacturing process in the gate length direction.

In this embodiment, a side wall oxide film is formed in the first embodiment. Components that are substantially the same as or correspond to the first specific example are denoted by the same reference numerals, and detailed description thereof will be omitted. Note that the steps up to the middle are basically the same as the steps of FIGS. 22A to 22E shown in the first specific example, and thus the description is omitted.

After the gate forming pattern 309 is formed in the step of FIG. 22E, a silicon oxide film is deposited to a thickness of 100 nm, and this silicon oxide film is receded by RIE so as to cover the periphery of the gate forming pattern. A sidewall insulating film 331 is formed. Here, the substrate profile in the source / drain regions can be controlled by performing the ion implantation of the impurity again (FIG. 26A).

The subsequent steps are the same as those in the first example, and are performed through the steps shown in FIGS. 26 (b) and (c).
A structure as shown in FIG. 26D is obtained.

In this embodiment, a barrier metal 321 may be provided as shown in FIGS. 27 and 38 in the same manner as shown in FIG. 25 of the first embodiment.

Next, a third specific example of the third embodiment will be described with reference to FIGS. FIG.
29A to 29H are cross-sectional views (cross-sectional views taken along the line AA ′ in FIG. 35) showing the manufacturing process in the gate length direction.

First, a silicon film 303 made of polycrystalline silicon or amorphous silicon containing impurities to be a part of a gate wiring is deposited on a silicon substrate 301 via a gate insulating film 302 to a thickness of 100 nm. If necessary, an impurity is implanted into the substrate before depositing the gate electrode to control the substrate concentration (FIG. 28A).

Next, a resist pattern (not shown) for forming an element region is formed, and using this resist pattern as a mask, the silicon film 303, the gate insulating film 302 and the silicon substrate 301 are etched by reactive ion etching. , An island portion 304 and a groove portion 305 are formed.
After removing the resist pattern, the periphery of the island formed as necessary is oxidized to improve the surface condition (FIG. 2).
8 (b)).

Next, a buried insulating film 306 is deposited on the entire surface, and is flattened to the upper surface of the silicon film 303 by CMP or the like to bury the element isolation region. In the present invention, since the silicon film 303 is not removed at this time, the corner of the element region is not exposed (FIG. 28C).

Next, a buffer oxide film 341 and a silicon film 34 made of polycrystalline silicon or amorphous silicon
Form 2 At this time, the silicon film 303 and the silicon film 342 are in close contact with each other via the buffer oxide film 341, and the upper surface of the silicon film 342 is finished flat (FIG. 28D).

Next, a resist pattern (not shown) is formed, and the silicon film 342, the buffer oxide film 341 and the silicon film 303 are simultaneously etched by RIE or the like using the resist pattern as a mask, thereby forming a gate forming pattern. 309 and a groove 310 are formed. After removing the resist pattern, the side portions are oxidized as necessary to improve the surface condition. Subsequently, impurity ions are implanted into the silicon substrate 301 by using the gate formation pattern 309 as a mask, so that the source
A drain diffusion region (not shown) is formed (FIG. 28)
(E)).

Next, a buried oxide film 311 is deposited on the entire surface, and the upper surface of the silicon film 342 is planarized by CMP or the like. At this time, the buried insulating film 311 does not remain on the upper surface of the silicon film 342 (FIG. 28F).

Next, the silicon film 342 is removed by the CDE method, and the buffer oxide film 341 is further removed by the RIE method to expose the upper surface of the silicon film 303, thereby forming a groove 312 (FIG. 29 (g)).

Next, in order to improve the connection between the silicon film 303 and a gate wiring material to be buried later, the upper surface of the silicon film 303 is subjected to a cleaning process as necessary, and the gate wiring material 313 is buried in the groove 312. Thereafter, planarization is performed to the upper surface of the buried oxide film 311 by CMP or the like, and a gate wiring including the electrode portion 303 and the wiring portion 313 is formed. At this time, the upper surface of the gate wiring (the upper surface of the wiring portion 313) is finished flat (FIG. 29H).

When the material forming the wiring member 313 is a metal such as W, as shown in FIGS. 30 and 36, for the purpose of preventing a reaction with a-Si or the like forming the electrode portion 303,
The barrier metal 321 may be provided.

The subsequent steps are the same as those in a normal transistor manufacturing process. After depositing an interlayer insulating film, a contact hole and an aluminum wiring are formed as necessary.

Next, a fourth specific example of the third embodiment will be described with reference to FIGS. FIG.
37 (a) to (d) are cross-sectional views (cross-sectional views taken along the line AA 'in FIG. 37) showing the manufacturing process in the gate length direction.

In this embodiment, the side wall nitride film is formed in the third embodiment. Components substantially the same as or corresponding to those of the third specific example are denoted by the same reference numerals, and detailed description thereof will be omitted. Note that the steps up to the middle are basically the same as the steps of FIGS. 28A to 28E shown in the third specific example, and thus the description is omitted.

After the gate formation pattern 309 is formed in the step of FIG. 28E, a silicon nitride film is deposited to a thickness of 100 nm, and this silicon nitride film is receded by RIE so as to cover the periphery of the gate formation pattern. A sidewall insulating film 331 is formed. Here, the substrate profile in the source / drain region can be controlled by performing the ion implantation of the impurity again (FIG. 31A).

The subsequent steps are the same as those in the first specific example, and are performed through the steps shown in FIGS. 31 (b) and (c).
A structure as shown in FIG. 31D is obtained.

In this embodiment, a barrier metal 321 may be provided as shown in FIGS. 32 and 38 in the same manner as shown in FIG. 25 of the first embodiment.

This embodiment is also effective when the source / drain contacts are formed by a self-alignment method. In this case, as shown in FIG. 33, the upper surface of the buried gate wiring is recessed by etching. There silicon nitride film 3
After embedding 51, it may be planarized by CMP or the like.

Next, a fifth specific example of the third embodiment will be described with reference to FIG. FIG. 34 (a),
3B is a cross-sectional view in the gate length direction showing a manufacturing process (FIG.
7 is a sectional view taken along line AA ′ of FIG.

In this example, the oxide film 361 is formed by oxidizing the periphery of the gate forming pattern immediately before forming the side wall insulating film in the fourth example (FIG. 34).
(A)). The oxide film 361 makes the Si ₃ N ₄ film 331
The adhesion at the interface with the element region is improved, and peeling of the Si ₃ N ₄ film can be prevented (FIG. 34B). Other steps are basically the same as in the fourth specific example.

In each specific example of the third embodiment, the flattening method is not limited to CMP but may be etched back by chemical dry etching, and the source / drain regions may be formed by ion implantation. The gas diffusion method may be used without limitation.

The silicon film 303 serving as a part of the gate electrode may be formed by depositing a silicon film containing no impurity to form a groove 312 and then introducing an impurity by ion implantation or the like. In this case, by performing patterning as needed, the type and amount of impurities can be locally changed, and the threshold value can be controlled.

Next, a fourth embodiment of the present invention will be described.

First, a first specific example of the fourth embodiment will be described with reference to FIGS. 39 to 42 are cross-sectional views in the gate length direction showing the manufacturing process, and FIGS. 43 and 44 are cross-sectional views in the gate width direction. Although the figure shows an NMOS structure, a PMOS can also be formed in a similar manner.

First, a Si substrate is prepared, and a trench having a depth of about 200 nm is formed in the element isolation region by RIE.
Subsequently, after TEOS is deposited, it is buried and flattened by CMP to form an island portion 401 made of a Si substrate and an element isolation region 402 having an STI structure. Thereafter, the substrate surface is oxidized by about 5 nm to form a dummy gate oxide film 403. In the NMOS region in the substrate, P
A mold well (peak concentration of about 1 × 10 ¹⁸ cm ⁻³ ) is formed in advance (FIGS. 39A and 43A).

Next, an amorphous silicon (a-Si) film 404 of about 20 nm and a silicon nitride film (Si ₃ N ₄ film) 405 of about 100 nm are deposited by LPCVD. Subsequently, a resist (not shown) is applied, patterned into the shape of a dummy gate by photolithography or EB (electron beam) drawing, and the Si ₃ N ₄ film 405 and the a-Si film 404 are processed by RIE. A dummy gate 421 is formed (FIG. 39B, FIG. 43).
(B)).

Here, since the dummy gate 421 has a two-layer structure, RIE can be easily performed. This is because the a-Si film 404 serves as a stopper when etching the Si ₃ N ₄ film 405. For this reason, there is no fear that the silicon substrate is scraped by the etching over. In addition, since the etching of the Si ₃ N ₄ film 405 can be performed for a sufficiently long time, there is a merit that SiN does not remain at a difference portion such as an STI edge. In addition, the s-Si film 404 is crystallized in a high-temperature process at the time of depositing the Si ₃ N ₄ film 405, but the size of each crystal grain is reduced by sufficiently reducing the thickness of the a-Si film. be able to. Therefore, the unevenness of the side surface caused by the grain can be reduced, and the gate length processing dimension can be easily controlled.

Next, when an LDD structure is formed, n ⁻
The impurity for forming the layer 406 is introduced by ion implantation, solid layer diffusion, or gas phase diffusion. Finally this n ^- layer 4
The impurity is doped so that the impurity concentration of No. 06 becomes about 1 × 10 ²⁰ cm ⁻³ (FIG. 39C).

Next, a step of forming a silicon nitride film on the gate side wall is started. That is, the silicon oxide film 407 is formed to a thickness of about 5 nm and the silicon nitride
The silicon nitride film 408 is deposited to a thickness of about 0 nm, and is left only on the side of the dummy gate by RIE.
(D)).

Next, the process proceeds to a source / drain formation step. Here, an elevated source / drain is formed by selective epitaxial growth, and a structure in which a cobalt silicide 410 is bonded thereto is adopted. The n ⁺ layer 409 can be formed by ion implantation or solid phase diffusion from an elevated source / drain so that the impurity concentration becomes about 1 × 10 ²¹ cm ⁻³ (FIG. 40E).

Next, an interlayer insulating film 411 is formed on the source / drain and on the element isolation region. First, TEOS is deposited to a thickness of about 150 nm, and this is etched back by CMP to flatten it. At this time, the Si ₃ N ₄ film 4
05 is a CMP stopper (FIG. 40 (f), FIG.
3 (f)).

Next, the process for forming the groove 422 by removing the dummy gate 421 and the dummy oxide film 403 is started.
The Si ₃ N ₄ film 405 constituting the dummy gate can be removed by hot phosphoric acid, and the a-Si film 404 can be removed by CDE or RIE. Hot phosphoric acid can selectively remove only the SiN film, and since the a-Si film is as thin as 20 nm, it can be removed by short-time etching. Therefore, there is no need to form a thick etching stopper film as a base, and the thickness of the dummy oxide film 403 can be reduced. If the dummy oxide film 403 can be made thinner, the amount of hydrofluoric acid-based wet etching for removing the dummy oxide film 403 can be reduced, and the end of the STI 402 does not need to be depressed much. Also,
Since the amount of hydrofluoric acid wet etching is small, the groove width (gate length) for embedding the gate does not have to be widened,
It is easy to control the gate length processing dimensions. In this structure, since the an Si ₃ N ₄ film 408 on the side surfaces of the dummy gate, wherein the etching is stopped, but there is no fear that too spread groove width, the greater the amount of wet etching, the Si ₃ There is a risk that the oxide film 403 under the N ₄ film 408 is eroded from the side. If erosion occurs, it is difficult to form a gate insulating film thereafter (FIG. 41 (g),
FIG. 44 (g)).

Next, a gate insulating film 412 having an effective film thickness of 3 to 4 nm is formed, and a barrier metal 4 having an effective film thickness of about 5 to 10 nm is formed.
A metal gate wiring 414 is buried via a 13 (reaction prevention film). Here, Si is used as the gate insulating film.
TiN or tungsten nitride is used as an ON film and a barrier metal, and W (tungsten) is used as a metal gate material. Ta ₂ O ₅ is used as the gate insulating film.
A high dielectric film or a ferroelectric film such as a film or a (Ba, Sr) TiO ₃ film can be applied. In that case, it is necessary to select a gate electrode material according to the type of the gate insulating film to be used, and Al, Ru, TiN, etc. can be used (FIG. 41).
(H), FIG. 44 (h)).

Next, the surface of the metal gate 414 is
Depress about 30 nm by DE or RIE to obtain a Si ₃ N ₄ film 41.
Embed 5 The embedding of the Si ₃ N ₄ film 415 includes C
VD and CMP are used. In the steps so far, the upper and side surfaces of the metal gate 414 are covered with the silicon nitride film (FIG. 41 (i)).

Thereafter, TEOS is used as the interlayer insulating film 416.
Is deposited to a thickness of about 150 nm, contact holes are formed on the source and drain, and a barrier metal 41 such as Ti / TiN is formed.
Then, a metal wiring 418 of Al or Cu is formed via the gate 7 (FIG. 42 (j)).

According to the above steps, the gate characteristic is hardly dropped at the STI edge portion, and the transistor characteristics are improved. That is, since the formation of the parasitic transistor at the STI edge portion is suppressed, there is no hump in the sub-threshold characteristic and the gate withstand voltage is improved.

Next, a second specific example of the fourth embodiment will be described with reference to FIGS. FIGS. 45 to 47 are cross-sectional views in the gate length direction showing the manufacturing process, and FIGS. 48 and 49 are cross-sectional views in the gate width direction. Although the figure shows an NMOS structure, a PMOS can also be formed in a similar manner.

First, a Si substrate is prepared, and a trench having a depth of about 200 nm is formed in the element isolation region by RIE.
Subsequently, after TEOS is deposited, it is buried and flattened by CMP to form an island portion 401 made of a Si substrate and an element isolation region 402 having an STI structure. Thereafter, the substrate surface is oxidized by about 15 nm to form a dummy gate oxide film 403. The dummy gate oxide film 403 is made thicker than in the first specific example so as to serve as an etching stopper when the dummy gate is later processed by RIE. A P-type well (peak concentration of about 1 × 10 ¹⁸ cm ⁻³ ) is formed in the NMOS region in the substrate (FIG. 4).
5 (a), FIG. 48 (a)).

Next, the Si ₃ N ₄ film 40 is formed by LPCVD.
5 is deposited to a thickness of about 120 nm. Subsequently, a resist (not shown) is applied, patterned into the shape of a dummy gate by photolithography or EB (electron beam) drawing, and the Si ₃ N ₄ film 405 is processed by RIE to form a dummy gate 421. . Since the Si ₃ N ₄ film is amorphous, unlike the case of etching polysilicon, there is no problem of unevenness on the side surface caused by grains. Therefore, it is easy to control the gate length processing size (FIGS. 45B and 48B).

Next, when an LDD structure is formed, n ⁻
The impurity for forming the layer 406 is introduced by ion implantation, solid layer diffusion, or gas phase diffusion. Finally this n ^- layer 4
The impurity doping is performed so that the impurity concentration of No. 06 becomes approximately 1 × 10 ²⁰ cm ⁻³ (FIG. 45C).

Next, a step of forming a silicon nitride film on the side wall of the gate is started. That is, the silicon oxide film 407 is formed to a thickness of about 5 nm and the silicon nitride
The silicon nitride film 408 is deposited to a thickness of about 0 nm, and is left only on the side of the dummy gate by RIE (FIG. 46).
(D)).

Next, the process proceeds to a source / drain formation step. Here, an elevated source / drain is formed by selective epitaxial growth, and a structure in which cobalt silicide 410 is adhered thereto is adopted. The n ⁺ layer 409 can be formed by ion implantation or solid phase diffusion from an elevated source / drain so that the impurity concentration becomes about 1 × 10 ²¹ cm ⁻³ (FIG. 46E).

Next, an interlayer insulating film 411 is formed on the source / drain and on the element isolation region. First, TEOS is deposited to a thickness of about 150 nm, and this is etched back by CMP to flatten it. At this time, the Si ₃ N ₄ film 4
05 serves as a CMP stopper (FIG. 46 (f), FIG.
8 (f)).

Next, a process for forming the groove 422 by removing the dummy gate 421 and the dummy oxide film 403 is started.
The Si ₃ N ₄ film 405 constituting the dummy gate is removed by hot phosphoric acid, and the dummy oxide film 403 is removed by hydrofluoric acid wet etching. Si _{3 on} the side of the dummy gate
Since the N ₄ film 408 is formed, the wet etching stops here, and there is no fear that the groove width is too wide. At the time of hydrofluoric acid wet etching, the vicinity of the edge of the STI 402 is dented, and the edge corner portion of silicon to be an element region is exposed. Then, the silicon substrate 4 is formed by RIE.
01 is dug down by about 60 nm. By doing so, the surface of the silicon substrate 401 in the channel region is
2 is lower than the TEOS surface, and the edge corner portion of the silicon substrate 401 is not exposed (FIG. 47G).
FIG. 49 (g)).

Next, a gate insulating film 412 having an effective thickness of 3 to 4 nm is formed, and a barrier metal 4 having an effective thickness of about 5 to 10 nm is formed.
Then, a metal gate wiring 414 is buried through the semiconductor substrate 13. Here, an SiON film is used as a gate insulating film, TiN or tungsten nitride is used as a barrier metal, and tungsten is used as a metal gate material. As a gate insulating film, a Ta ₂ O ₅ film or (Ba, Sr) Ti
A high dielectric film such as an O ₃ film or a ferroelectric film can also be applied. In that case, it is necessary to select a gate electrode material according to the type of the gate insulating film to be used, and Al, Ru, Ti
N can be used (FIG. 47 (h), FIG. 49).
(H)).

Next, the surface of the metal gate 414 is
Depress about 30 nm by DE or RIE to obtain a Si ₃ N ₄ film 41.
Embed 5 The embedding of the Si ₃ N ₄ film 415 includes C
VD and CMP are used. In the steps so far, the upper and side surfaces of the metal gate 414 are covered with the silicon nitride film (FIG. 47 (i)).

The subsequent steps are the same as in the first example. That is, 150 nm of TEOS is used as an interlayer insulating film.
To form contact holes on the source / drain, and Al or C through a barrier metal such as Ti / TiN.
u metal wiring is formed.

According to the above steps, the gate does not drop at the STI edge portion, but rather the gate is lifted from the element region to the element isolation region, and the transistor characteristics are improved. That is, the formation of the parasitic transistor at the edge of the STI region is prevented.
There is no hump in the sub-threshold characteristic, and the gate breakdown voltage is improved.

The following fifth to eighth embodiments are examples using dummy gate side walls.

FIGS. 50 to 53 are cross-sectional views showing the steps of manufacturing the semiconductor device according to the fifth embodiment of the present invention.

First, a shallow trench isolation (STI) region 12 is formed on a semiconductor substrate 11 made of silicon by a known method, and an element region separated from other regions by the STI region 12 is formed (FIG. 11). 50 (a)).

This step is performed, for example, as follows. That is, a silicon nitride film serving as a mask is deposited on the silicon substrate 11 via a buffer oxide film, a resist pattern for transfer is formed, and then the silicon nitride film is patterned by RIE to form an element region pattern. Next, using the silicon nitride film pattern as a mask, the silicon substrate 11 in the element isolation region is etched to form a trench. After removing the resist, an insulating film such as a silicon oxide film is deposited on the entire surface, and is planarized by CMP or the like to the upper surface of the silicon nitride film pattern serving as a mask. Thereafter, by removing the silicon nitride film and the buffer oxide film, an element isolation region in which an insulating film is buried in the trench and an element region separated from other regions by the element isolation region are formed.

Next, for example, a silicon nitride film is deposited on the element region via a buffer oxide film 14 such as a silicon oxide film, and this silicon nitride film is subjected to RIE using a resist pattern (not shown) as a mask. The dummy gate 13 is formed by etching with a method such as that shown in FIG.
0 (b)). Before and after the formation of the dummy gate 13, impurity ion implantation may be performed to control the channel and diffusion layer profiles.

Next, polycrystalline or amorphous silicon is deposited on the entire surface, and dummy sidewalls 15 are formed on the side surfaces of the dummy gate 13 by RIE (FIG. 50 (c)). Thereafter, ion implantation for forming a source / drain is performed (not shown).

An interlayer insulating film 16 is deposited on the entire surface (FIG. 50).
(D)), planarization is performed to the upper surface of the dummy gate 13 by CMP or the like (FIG. 51E). The dummy gate 13 and the exposed buffer oxide film 14 are removed (FIG. 51F).
Thereafter, a new gate insulating film 17 is formed, and a gate electrode 18 is further deposited (FIG. 51G). If the gate electrode 18 is made of metal, the gate insulating film 17 may be used if necessary.
A reaction prevention layer is formed between the gate electrode and the gate electrode.

The gate electrode 18 is flattened (FIG. 51).
(H) Then, the upper surfaces of the gate insulating film 17 and the gate electrode 18 are slightly etched as necessary so that the dummy sidewalls 15 are sufficiently exposed (FIG. 52 (i)).

In this case, the dummy side wall 15 may be exposed when the gate electrode 18 is flattened. At this time, it may not be necessary to etch the upper surface of the gate electrode 18 again.

Next, the exposed dummy side wall 15 is removed by etching using, for example, KOH or the like, and a cavity 19 is formed. The cavity 19 becomes a mold for forming a new side wall later (FIG. 52 (j)).

Next, RIE for forming a contact hole, that is, a material 20 having a high selectivity with respect to RIE of an interlayer insulating film is poured into the cavity 19 (FIG. 52 (k)). . Such a material includes, for example, Si ₃ N _4. However, when a lower dielectric constant side wall is to be formed, an organic material having an insulating property can be used.

Thereafter, the side wall material protruding outside the cavity 19 is removed by using, for example, CMP, and at the same time, is flattened to complete the embedding of the side wall 20 (FIG. 53).
(L)).

Thereafter, through a well-known transistor manufacturing process, the transistor is completed. That is, after the interlayer insulating film 21 is deposited, a contact hole for contact is formed by RIE using the resist pattern as a mask.
(FIG. 53 (m)).

In the present embodiment, since the side wall 20 is provided, even if the patterning is slightly shifted during the formation of the resist pattern, the contact hole for the source / drain does not open directly on the upper surface of the gate electrode. A short circuit between the electrode and the source / drain region can be prevented.

The contact to the gate electrode is
After a reaction prevention layer is formed in the contact holes of the gate electrode and the source / drain regions which are tolerant of misalignment, for example, Al is buried in the contact holes. Thereafter, a resist pattern is separately formed, and the Al layer is etched using the resist pattern as a mask, thereby forming the first-layer wiring 22 (FIG. 53 (n)).

Sixth Embodiment FIGS. 54 to 56 are cross-sectional views showing the steps of manufacturing a semiconductor device according to a sixth embodiment of the present invention.

This embodiment is different from the fifth embodiment in that
This is a case where the dummy gate has a two-layer structure of polycrystalline or amorphous silicon and a silicon nitride film.

As in the fifth embodiment, a shallow trench isolation (STI) region 12 is formed on a semiconductor substrate 11 made of silicon by a known method, and is separated from other regions by the STI region 12. (FIG. 54)
(A)). Next, a dummy gate layer made of, for example, an amorphous silicon film and a silicon nitride film is deposited on the element region via a buffer layer 14 made of, for example, a silicon oxide film. Using a mask (not shown) as a mask and etching by RIE or the like, the dummy gate 13 composed of the amorphous silicon film 23 and the silicon nitride film 24 is formed (FIG. 54).
(B)). Note that before and after the formation of the dummy gate, impurity ion implantation may be performed to control the channel and diffusion layer profiles.

Next, a thin silicon oxide film 25 is deposited on the entire surface (FIG. 54 (c)), and polycrystalline or amorphous silicon is further deposited, and dummy sidewalls 15 are formed on the dummy gate side surfaces by RIE. (FIG. 54 (d)). Thereafter, ion implantation for forming source / drain regions (not shown) is performed.

An interlayer insulating film 16 is deposited on the entire surface (FIG. 55).
(E)), planarization is performed to the upper surface of the dummy gate 13 by CMP or the like (FIG. 55 (f)). At this time, the dummy side wall 1
5 is exposed, the exposed portion of the dummy side wall 15 is oxidized and an oxide film 26 is formed, thereby forming the dummy side wall 1.
5 (FIG. 55 (g)).

Next, the dummy gate 13 and the buffer oxide film 14 are removed. Even when the dummy side wall 15 is made of amorphous silicon, only the dummy gate 13 is removed because the dummy side wall 15 is covered with the oxide film. (FIG. 55 (h)). When removing buffer oxide film 14, oxide film 25 is also etched.

The subsequent steps are the same as in the case of the fifth embodiment. That is, the gate insulating film 17 and the gate electrode 18 are newly deposited (FIG. 56 (i)), the gate electrode 18 is flattened (FIG. 45J), and the upper surface of the gate electrode is so exposed that the dummy side wall 15 is sufficiently exposed. Is slightly etched (FIG. 56 (k)). Then, the exposed dummy side wall is removed by etching using, for example, KOH or the like to form a cavity. A material having a high insulating property and a high selectivity to RIE for a contact hole, that is, an RIE for an oxide film is poured into the cavity. Thereafter, the protruding side wall material is removed by using, for example, CMP, and at the same time, planarization is performed to complete the embedding of the side wall.

FIGS. 57 and 58 are cross-sectional views showing the steps of manufacturing the semiconductor device according to the seventh embodiment of the present invention.

First, a shallow trench element isolation (STI) region 12 is formed on a semiconductor substrate 11 made of silicon by a known method, and an element region separated from other regions by the STI region 12 is formed. Here, the channel profile may be controlled by ion implantation of impurities.

Next, after a silicon oxide film 17 is formed as a gate insulating film on the element region, conductive polycrystalline silicon containing phosphorus serving as a gate electrode 18 is deposited.
After patterning the gate, the gate electrode 18 is formed by etching with RIE or the like. Here, impurity ion implantation may be performed to control the profile of a diffusion layer (not shown).

Next, after depositing a silicon nitride film, R
Etching by IE or the like, the side wall 1 on the side surface of the gate electrode 18
5 is formed (FIG. 57A). Next, ion implantation for forming source / drain regions (not shown) is performed. Then, after depositing the interlayer insulating film 16 (FIG. 57)
(B)), planarization is performed by CMP or the like, and the upper surface of the gate electrode 18 is exposed (FIG. 57 (c)).

After the gate electrode 18 is recessed by etching (FIG. 57D), the exposed silicon nitride film side wall 15 is removed by, for example, hot phosphoric acid treatment, and a cavity is formed as a mold in which a new side wall is formed. 19 (FIG. 58)
(E)).

Next, an insulating organic material 20 having an etching selectivity with respect to a silicon oxide film, which is a side wall material, and having a lower dielectric constant than a silicon nitride film is poured into the cavity 19 (FIG. 46F). Thereafter, the protruding side wall material is removed by using, for example, CMP, and at the same time, planarization is performed to complete the embedding of the side wall 20 (FIG. 58 (g)).

Thereafter, the transistor is completed through a known transistor process. That is, after depositing an interlayer insulating film, a contact hole for forming a contact is formed by RIE using a resist pattern as a mask. Here, since there is a side wall formed in the present embodiment, even if the resist pattern is slightly displaced, the source / drain contact hole does not open directly on the upper surface of the gate electrode, and the gate and the source / drain are short-circuited. Can be prevented.

Then, after forming a reaction preventing layer in the gate and the contact hole of the source / drain, for example, A
Embed l. The first layer wiring is completed by etching this Al film using the resist pattern as a mask.

Next, the eighth embodiment in which the present invention is applied to the formation of wirings will be described.
An embodiment will be described.

Polycrystalline silicon is deposited on the interlayer insulating film deposited on the lower wiring, and the polycrystalline silicon film is etched using a resist pattern as a mask to form a dummy wiring. Next, a silicon nitride film is deposited and etched to form a dummy sidewall on a side surface of the dummy wiring.

Next, after depositing an interlayer insulating film, the interlayer insulating film is planarized by CMP or the like to expose the upper surface of the dummy wiring. After that, the dummy wiring is removed to form a groove for receiving the wiring, a wiring material (eg, aluminum, tungsten, copper, etc.) is deposited, flattened by CMP or the like, and the wiring material is embedded in the groove.

Further, the upper portion of the embedded wiring is receded by dry etching or the like to expose the dummy side wall. The dummy side wall is removed by hot phosphoric acid treatment or the like to form a cavity in which the side wall material enters. Next, an organic material having a high etching selectivity with respect to the silicon oxide film and having a lower dielectric constant than the silicon nitride film is poured into the cavity. Then, the protruding side wall material is removed by, for example, CMP or the like, and at the same time, flattening is performed, and the embedding of the side wall is completed.

In the above fifth and sixth embodiments, the side wall material is not limited to the organic material, but may be any insulating material having a high etching selectivity with the silicon oxide film as the interlayer insulating film. At this time, a low dielectric constant is particularly preferable in terms of electrical characteristics such as high-frequency characteristics. Further, not only wet etching but also dry etching may be used for removing the dummy side wall.

When the side wall is formed directly on the dummy gate by the RIE by the damascene process, the RIE for forming the side wall is performed.
Also, the CMP margin at the time of flattening becomes extremely narrow. However, in the methods described in the fifth to eighth embodiments,
RIE of the dummy side wall is performed by using the dummy side wall.
It is possible to widen the margin for the time and the variation of the flattening CMP. This is ultimately advantageous for product yield. In the damascene gate transistor, the conventional transistor, and the method of forming the side wall of the wiring described in the fifth to eighth embodiments, since there is no high-temperature step such as activation of the diffusion layer after the formation of the side wall, the organic insulating film is formed on the side wall. Because a low dielectric constant film such as
This is advantageous in reducing the parasitic capacitance which is important when operating at a high frequency.

The following ninth and tenth embodiments show the case where Ta ₂ O ₅ is used as a gate liner.

FIGS. 59 to 61 are sectional views showing the steps of manufacturing a semiconductor device according to the ninth embodiment of the present invention.

First, a shallow trench isolation (STI) region 12 is formed on a semiconductor substrate 11 made of silicon by a known method, and an element region separated from other regions by the STI region 12 is formed (FIG. 59 (a)).

Next, for example, a silicon oxide film 14 is formed as a buffer layer, and an amorphous or polycrystalline silicon film serving as a dummy gate and a silicon nitride film are deposited thereon to form a dummy gate layer. Thereafter, the dummy gate layer is etched by RIE or the like using a resist pattern (not shown) as a mask, thereby forming a dummy gate 13 composed of the amorphous silicon film 23 and the silicon nitride film 24 (FIG. 59 ( b)). Before and after the formation of the dummy gate, impurity ion implantation may be performed to control the profile of a channel and a diffusion layer (not shown).

Next, tantalum oxide is deposited on the entire surface to a thickness of 10 nm to form a gate (dummy gate) liner 31 (FIG. 59 (c)). Thereafter, after depositing, for example, an oxide film, the side wall 15 is formed on the side surface of the dummy gate 13 by etching back by RIE or the like (FIG. 47D), and the portion not covered by the side wall 15 is formed by dry etching. The tantalum oxide film 31 is removed (FIG. 60E).
It has been confirmed that tantalum can be removed under the etching conditions at which ordinary silicon is etched.

Further, ion implantation is performed to form source / drain regions (not shown), an interlayer insulating film 16 is deposited on the entire surface, and a dummy gate is buried (FIG. 60 (f)).
Flatten by CMP or the like (FIG. 60 (g)). At this time, the upper surface of the dummy gate 13 is exposed. The silicon nitride film 24 above the dummy gate 13 is removed by hot phosphoric acid treatment (FIG. 61 (h)), and the polycrystalline or amorphous silicon 23 under the dummy gate 13 is removed by KOH or mixed acid (FIG. 61). (I)).

Finally, the silicon oxide film formed as a buffer is removed with dilute hydrofluoric acid to obtain a trench 32 for forming a gate (FIG. 61 (j)). Note that tantalum oxide is also etched with hydrofluoric acid, but its etching rate is 1/25 of that of a silicon oxide film.
It can be considered that substantially tantalum oxide is hardly etched.

After that, the process is the same as the ordinary damascene gate forming process. That is, a gate insulating film is formed by oxidizing the silicon substrate 11 or depositing an insulating film (in addition, tantalum oxide can be used as the insulating film). If necessary, a reaction preventing layer is formed, and an electrode material is deposited on the entire surface. By flattening by CMP or the like, a gate electrode is formed in the groove from which the dummy gate has been removed.

This embodiment is different from the ninth embodiment in that
The case where a gate liner is formed as a side wall directly on the side surface of a dummy gate is shown. That is, similar to the ninth embodiment, the STI
After forming a dummy gate on the device region separated by the region, a gate liner is deposited. In the case of this embodiment, since it is formed as a side wall, a substantial width is larger than ordinary SiO _{2 in} terms of electrical characteristics after formation, and therefore it is desirable to use a film having a dielectric constant lower than that of tantalum oxide. Used. After the deposition, the side wall 15 is formed on the side surface of the dummy gate by anisotropic etching (FIG. 62).
(A)).

After ion implantation is performed using the dummy gate and the side wall 15 as a mask to form source / drain regions, an interlayer insulating film 16 is deposited and the dummy gate is buried. The surface is flattened by CMP or the like, and the upper surface of the dummy gate is exposed (FIG. 62B).

The exposed dummy gate is removed, and a groove for forming the gate is formed. For example, when the configuration of the dummy gate is the silicon nitride film 24 and the amorphous silicon 23, as in the ninth embodiment, the dummy gate is removed by hot phosphoric acid treatment and mixed acid treatment.

Next, hydrofluoric acid treatment is performed to remove the silicon oxide film 14 formed as a buffer. However, yttrium oxide does not dissolve in hydrofluoric acid. There is no need to worry about the side wall 15 being cut off.

After that, the process is the same as the ordinary damascene gate forming process. That is, a gate insulating film is formed by oxidizing a silicon substrate or depositing an insulating film. Note that tantalum oxide may be used as the insulating film.) If necessary, a reaction prevention layer is formed, and an electrode material is deposited on the entire surface. By flattening by CMP or the like, a gate electrode is formed in the groove from which the dummy gate has been removed.

In the ninth and tenth embodiments, the material used for the liner is not limited to tantalum oxide, but niobium oxide, yttrium oxide, and cerium oxide can also be used. Further, tantalum oxide, niobium oxide, or cerium oxide may be used instead of the side wall. Further, the dummy gate may be a multilayer or a single layer.

As described above, the transistors obtained according to the ninth and tenth embodiments have the following advantages in removing the dummy gate.
Since a groove in which a gate is to be formed later does not expand more than necessary, it is very advantageous in miniaturization. For example, the minimum inter-gate-wiring dimension does not become smaller than the design dimension, and the inter-wiring capacitance, which becomes a problem when high-frequency operation is considered, does not increase. In addition, since the gate wiring is finished to the design dimensions with respect to the source / drain contact, it is not necessary to include the spread of the gate wiring in the patterning margin of the contact, which is advantageous for high integration. Further, in the case where the spread of the upper part of the gate is suppressed in the conventional technique, the final gate thickness must be reduced, and the gate wiring resistance increases. On the other hand, in the present embodiment, the gate thickness is reduced. It is not necessary to reduce the gate wiring resistance.
It consumes less power and has less effect on the dielectric properties.

A method for manufacturing a semiconductor device according to the eleventh embodiment of the present invention will be described with reference to FIGS.

First, an element isolation insulating film 42 and a p-type diffusion layer 43 are formed on a silicon substrate 41.
(A)). Next, the silicon substrate 4 is subjected to a thermal oxidation process.
A silicon oxide film 44 is formed by oxidizing one surface by about 5 nm, and a silicon nitride film 45 of about 200 nm is deposited thereon and patterned to form a dummy gate electrode 45. Thereafter, the dummy gate electrode 45
Is used as a mask, an n-type impurity such as arsenic is ion-implanted, and impurity activation is performed by heat treatment at 750 ° C. or more, thereby forming an n ⁻ -type LDD diffusion layer 46 (FIG. 6).
3 (b)).

Next, a silicon oxide film 47 of about 10 nm and a silicon nitride film 48 of about 10 nm are deposited on the entire surface.
After covering the dummy gate electrode, a silicon oxide film 49 of about 50 nm is deposited again, and anisotropic etching is performed to form a side wall silicon oxide film 49.

Thereafter, ion implantation and impurity activation by heat treatment at 900 ° C. or more are performed again using the dummy gate electrode 45 and the insulating films 47, 48, and 49 on the side surfaces thereof as a mask, whereby an n ⁺ -type impurity diffusion layer is formed. (Source, drain regions) 50 are formed (FIG. 63C).

Next, a silicon oxide film 51 is deposited on the entire surface, and the silicon oxide film 51 is polished and flattened using the silicon nitride film 48 or 45 as a stopper. In the drawings of the present embodiment, the silicon nitride film 48 on the dummy gate electrode 45 disappears when the silicon oxide film 51 is polished, and the polishing is stopped at the dummy gate electrode 45. Even if the polishing is stopped at the silicon nitride film 48, substantially the same result can be obtained through the following steps (FIG. 63 (d)).

Exposed silicon nitride film dummy gate 45
And silicon nitride film 48 is treated with hot phosphoric acid or the like to
Etch about 0 nm to form two grooves having widths L and d. Then, a silicon oxide film 52 of about 10 nm is formed on the entire surface.
Is deposited. At this time, the thickness of the silicon oxide film 52 must be at least １ ／ or less of the width (L) of the dummy gate electrode and １ ／ or more of the thickness d of the silicon nitride film 48 (FIG. 64 (e)). That is, it is necessary that the film thickness be such that the groove above the silicon nitride film 48 is filled, but the groove above the dummy gate 45 is not filled.

Next, the upper portion of dummy gate electrode 45 is exposed by etching back silicon oxide film 52 by anisotropic etching. At this time, the silicon nitride film 48
Is not exposed because it is covered with the silicon oxide film 52 (FIG. 64 (f)).

Thereafter, the exposed silicon nitride film dummy gate 45 is removed by treatment with hot phosphoric acid or the like to form a groove in the gate electrode formation region, and then the silicon oxide film remaining in the groove region by etching with hydrofluoric acid or the like. 47, and the silicon oxide film 52 left in the etch back step is removed to expose the surface of the silicon substrate 41 (FIG. 64).
(G)).

Then, a high dielectric insulating film 53 such as a tantalum oxide film is deposited on the entire surface, a titanium nitride film 54 as a diffusion barrier layer and an aluminum layer 55 as a gate electrode are deposited, and the groove is formed by CMP polishing or the like. The remaining aluminum film 55, titanium nitride film 54, and tantalum oxide film 53 are removed (FIG. 64 (h)).

A silicon oxide film 56 is deposited on the entire surface, a contact hole is opened, a metal wiring layer 57 is formed, and a transistor is completed (FIG. 64 (i)).

As described above, according to the method according to the present embodiment, it is possible to form a gate electrode having a very low resistance without any problem in microfabrication, and to deteriorate the element performance due to parasitic resistance. Can be suppressed.

A method for manufacturing a semiconductor device according to the twelfth embodiment of the present invention will be described with reference to FIGS.

First, an element isolation insulating film 42 and a p-type diffusion layer 43 are formed on a silicon substrate 41.
(A)). Next, the silicon substrate 4 is subjected to a thermal oxidation process.
A silicon oxide film 44 is formed by oxidizing one surface by about 5 nm, and a silicon nitride film 45 of about 250 nm is deposited thereon and patterned to form a dummy gate electrode 45. Thereafter, the dummy gate electrode 45
Is used as a mask, an n-type impurity such as arsenic is ion-implanted, and impurity activation is performed by heat treatment at 750 ° C. or more, thereby forming an n ⁻ -type LDD diffusion layer 46 (FIG. 6).
5 (b)).

Next, a silicon oxide film 47 of about 10 nm and a silicon nitride film 48 of about 10 nm are deposited on the entire surface.
After covering the dummy gate electrode, a silicon oxide film 49 of about 50 nm is deposited again, and anisotropic etching is performed to form a side wall silicon oxide film 49.

Thereafter, the exposed silicon nitride film 48 is removed by anisotropic etching, and ion implantation and heat treatment at 900 ° C. or more are performed again using the dummy gate electrode 45 and the insulating films 47, 48, and 49 on the side surfaces thereof as a mask. By performing the impurity activation, an n ⁺ -type impurity diffusion layer (source and drain regions) 50 is formed (FIG. 50).
C).

Next, a silicon oxide film 51 is deposited on the entire surface.
The silicon oxide film 51 is polished and flattened using the silicon nitride film 45 as a stopper (FIG. 65 (d)).

Exposed silicon nitride film dummy gate 4
5 and the silicon nitride film 48 are etched by about 50 nm by treatment with hot phosphoric acid or the like to form grooves having different widths, and a silicon oxide film 52 of about 10 nm is deposited on the entire surface. At this time, the thickness of the silicon oxide film 52 must be at least １ ／ or less of the width (L) of the dummy gate electrode and １ ／ or more of the thickness d of the silicon nitride film 48 (FIG. 6 (e)).

Next, the upper portion of the dummy gate electrode 45 is exposed by etching back the silicon oxide film 52 by anisotropic etching. At this time, the silicon nitride film 48
Is not exposed because it is covered with the silicon oxide film 52 (FIG. 66 (f)).

Thereafter, the exposed silicon nitride film dummy gate 45 is removed by treatment with hot phosphoric acid or the like to form a groove in the gate electrode formation region, and then the silicon oxide film remaining in the groove region by etching with hydrofluoric acid or the like. 47 and the silicon oxide film 52 left in the etch back step are removed to expose the surface of the silicon substrate 41 (FIG. 66).
(G)).

Then, a high dielectric insulating film 53 such as a tantalum oxide film is deposited on the entire surface, a titanium nitride film 54 as a diffusion barrier layer and an aluminum layer 55 as a gate electrode are deposited, and the groove is formed by CMP or the like. The other portions of the tungsten film 55, the titanium nitride film 54, and the tantalum oxide film 53 are removed (FIG. 66H).

A silicon oxide film 56 is deposited on the entire surface, a contact hole is opened, a metal wiring layer 57 is formed, and a transistor is completed (FIG. 66 (i)).

As described above, according to the present embodiment, the first
As in the first embodiment, it is possible to always form a low-resistance gate electrode without any problems in microfabrication, and it is possible to suppress deterioration of device performance due to parasitic resistance.
In addition, since the silicon nitride film 48 covers the shallow diffusion layer 46 around the gate electrode, a silicon oxide film etching technique having a high selectivity to the silicon nitride film when forming the contact opening is used. If it is used, for example, even if the position of the contact opening is shifted, the metal wiring layer 57 is not connected to the shallow diffusion layer portion, so that the junction leakage current does not increase. Therefore, the element area can be designed to be smaller. .

As described above, according to the eleventh and twelfth embodiments, the resistance to the heat step required to activate the impurities in the source and drain regions is not necessarily impaired without impairing the fine workability of the gate electrode. It is no longer necessary to use a material with a certain material for the gate electrode material or the gate insulating film material. As a result, the parasitic resistance of the element can be reduced and the driving force can be improved.

[0261]

As described above, according to the present invention,
Since the exposure of the edge corner portion of the element region can be suppressed, deterioration of transistor characteristics due to electric field concentration at the edge corner portion can be prevented.

Further, by using the dummy side wall,
It is possible to widen the margin for the dummy sidewalls during RIE and for variations in the planarization CMP. This is ultimately advantageous for product yield. In particular, since a low dielectric constant film such as an organic insulating film can be used for the side wall, it is advantageous in reducing a parasitic capacitance which is important when operating at a high frequency.

Further, when Ta ₂ O ₅ or the like is used as the gate liner, it is not necessary to reduce the gate thickness, so that the gate wiring resistance can be suppressed, the power consumption can be reduced, and the dielectric characteristics can be reduced. The impact on the environment is small.

[Brief description of the drawings]

FIG. 1 is a view showing a part of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a view showing a part of a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a view showing a part of the manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the second embodiment of the present invention.

FIG. 5 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the second embodiment of the present invention.

FIG. 6 is a view showing a cross section in a gate width direction of a gate corresponding to FIG. 5H for a first specific example of the second embodiment of the present invention;

FIG. 7 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a second specific example of the second embodiment of the present invention.

FIG. 8 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a second specific example of the second embodiment of the present invention.

FIG. 9 is a view showing a cross section in a gate width direction of a gate corresponding to FIG. 8H for a second specific example of the second embodiment of the present invention;

FIG. 10 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a third specific example of the second embodiment of the present invention.

FIG. 11 is a diagram showing a cross section of a gate in a gate length direction for a part of a manufacturing process according to a fourth specific example of the second embodiment of the present invention.

FIG. 12 is a diagram illustrating a cross section of a gate in a gate length direction in a part of a manufacturing process according to a fourth specific example of the second embodiment of the present invention.

FIG. 13 is a view showing a cross section in a gate width direction of a gate corresponding to FIG. 12 (i) in a fourth specific example of the second embodiment of the present invention;

FIG. 14 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a fifth specific example of the second embodiment of the present invention.

FIG. 15 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a fifth specific example of the second embodiment of the present invention.

FIG. 16 is a view showing a cross section in a gate width direction of a gate corresponding to FIG. 15 (i) in a fifth specific example of the second embodiment of the present invention;

FIG. 17 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a sixth specific example of the second embodiment of the present invention.

FIG. 18 is a diagram showing a planar configuration according to a first specific example of the second embodiment of the present invention.

FIG. 19 is a diagram showing a planar configuration according to a second specific example of the second embodiment of the present invention.

FIG. 20 is a diagram showing a plan configuration according to a fourth specific example of the second embodiment of the present invention.

FIG. 21 is a diagram showing a plan configuration according to a fifth specific example of the second embodiment of the present invention.

FIG. 22 is a diagram illustrating a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the third embodiment of the present invention.

FIG. 23 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the third embodiment of the present invention.

FIG. 24 is a view showing a cross section in the gate width direction of the gate corresponding to FIG. 23H for the first specific example of the third embodiment of the present invention;

FIG. 25 is a diagram showing a cross section of a gate in a gate length direction according to a modification of the first specific example of the third embodiment of the present invention.

FIG. 26 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a second specific example of the third embodiment of the present invention.

FIG. 27 is a diagram showing a cross section of a gate in a gate length direction according to a modification of the second specific example of the third embodiment of the present invention.

FIG. 28 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a third specific example of the third embodiment of the present invention.

FIG. 29 is a diagram showing a cross section of a gate in a gate length direction for a part of a manufacturing process according to a third specific example of the third embodiment of the present invention.

FIG. 30 is a diagram showing a cross section of a gate in a gate length direction according to a modification of the third specific example of the third embodiment of the present invention.

FIG. 31 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a fourth specific example of the third embodiment of the present invention.

FIG. 32 is a diagram showing a cross section of a gate in a gate length direction according to a modification of the fourth specific example of the third embodiment of the present invention.

FIG. 33 is a view showing a cross section of a gate in a gate length direction according to a modification of the fourth specific example of the third embodiment of the present invention.

FIG. 34 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a fifth specific example of the third embodiment of the present invention.

FIG. 35 is a diagram showing a planar configuration according to first and third specific examples of the third embodiment of the present invention.

FIG. 36 is a diagram showing a planar configuration of a modification of the first specific example and a modification of the third specific example of the third embodiment of the present invention.

FIG. 37 is a diagram showing a planar configuration according to second, fourth, and fifth specific examples of the third embodiment of the present invention.

FIG. 38 is a diagram showing a plan configuration of a modified example of the second specific example and a modified example of the fourth specific example of the third embodiment of the present invention.

FIG. 39 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the fourth embodiment of the present invention.

FIG. 40 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the fourth embodiment of the present invention.

FIG. 41 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the fourth embodiment of the present invention.

FIG. 42 is a diagram showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a first specific example of the fourth embodiment of the present invention.

FIG. 43 is a view showing a cross section of a gate in a gate width direction for a part of a manufacturing process according to a first specific example of the fourth embodiment of the present invention;

FIG. 44 is a view showing a cross section of a gate in a gate width direction in a part of a manufacturing process according to a first specific example of the fourth embodiment of the present invention;

FIG. 45 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a second specific example of the fourth embodiment of the present invention.

FIG. 46 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a second specific example of the fourth embodiment of the present invention.

FIG. 47 is a view showing a cross section of a gate in a gate length direction in a part of a manufacturing process according to a second specific example of the fourth embodiment of the present invention.

FIG. 48 is a view showing a cross section of a gate in a gate width direction in a part of a manufacturing process according to a second specific example of the fourth embodiment of the present invention.

FIG. 49 is a view showing a cross section of a gate in a gate width direction in a part of a manufacturing process according to a second specific example of the fourth embodiment of the present invention;

FIG. 50 is a sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 51 is a sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 52 is a sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 53 is a sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention;

FIG. 54 is a sectional view showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 55 is a sectional view showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 56 is a sectional view showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 57 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 58 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 59 is a sectional view showing the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 60 is a sectional view showing the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 61 is a sectional view showing the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 62 is a sectional view showing the manufacturing process of the semiconductor device according to the tenth embodiment of the present invention;

FIG. 63 is a sectional view showing the manufacturing process of the semiconductor device according to the eleventh embodiment of the present invention;

FIG. 64 is a sectional view showing the manufacturing process of the semiconductor device according to the eleventh embodiment of the present invention;

FIG. 65 is a sectional view showing the manufacturing process of the semiconductor device according to the twelfth embodiment of the present invention;

FIG. 66 is a sectional view showing the manufacturing process of the semiconductor device according to the twelfth embodiment of the present invention;

FIG. 67 is a sectional view showing the manufacturing process of the semiconductor device according to the prior art of the present invention;

FIG. 68 is a sectional view showing the manufacturing process of the semiconductor device according to the prior art of the present invention;

FIG. 69 is a sectional view showing the manufacturing process of the semiconductor device according to the related art of the present invention;

FIG. 70 is a sectional view showing the manufacturing process of the semiconductor device according to another conventional technique of the present invention;

FIG. 71 is a sectional view showing the manufacturing process of the semiconductor device according to the prior art of the present invention;

FIG. 72 is a sectional view showing a manufacturing process of a semiconductor device according to another conventional technique of the present invention;

FIG. 73 is a sectional view showing the manufacturing process of the semiconductor device according to the conventional technique of the present invention;

FIG. 74 is a sectional view showing the manufacturing process of the semiconductor device according to the related art of the present invention;

FIG. 75 is a sectional view showing a manufacturing process of a semiconductor device according to another conventional technique of the present invention;

[Explanation of symbols]

 Reference Signs List 101 silicon substrate (semiconductor substrate) 102 silicon oxide film (dummy film) 103 amorphous silicon film (material film) 104 silicon nitride film (material film) 105 island part 106 first groove 107 buried insulating film (First insulating film) 108 dummy gate pattern 109 second groove 110, 112 source / drain diffusion layer 111 sidewall insulating film 113 layer insulating film (second insulating film) 114 third Groove 116: Gate insulating film 117: Gate electrode 201: Silicon substrate (semiconductor substrate) 202: Buffer oxide film (dummy film) 203: Amorphous silicon film (first material film) 204: Island portion 205: First groove 206 .. Buried insulating film (first insulating film) 207 dummy gate pattern 208 second trench 209 buried insulating film (second Insulating film) 210: Third trench 211: Gate insulating film 212: Gate wiring 221: Side wall insulating film 231: Amorphous silicon film (second material film) 301: Silicon substrate (semiconductor substrate) 302: Gate insulating film 303 Silicon film (first conductive film, first material film) 304 island portion 305 first groove portion 306 embedded insulating film (first insulating film) 308 silicon nitride film (second material film) 309 ... Gate forming pattern 310. Second trench 311. Embedded insulating film (second insulating film) 312. Third trench 313. Gate wiring material (second conductive film) 321. Barrier metal 331. Reference numeral 401: silicon substrate (island) 402: element isolation region (first insulating film) 403: silicon oxide film (dummy film) 404: amorphous silicon film (material film) 40 5: Silicon nitride film (material film) 406, 409: Source / drain diffusion layer 408: Side wall insulating film 411: Interlayer insulating film (second insulating film) 412: Gate insulating film 413: Barrier metal (reaction preventing film) 414 ... Tungsten film (gate wiring) 421 ... Dummy gate pattern 422 ... Groove

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Atsushi Yagishita 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Toshiba Yokohama Office

Claims (8)

[Claims] A step of forming a first film and a second film on a semiconductor substrate; and selectively removing an upper portion of the second film, the first film and the semiconductor substrate to form a first film. Forming a trench, forming a device isolation region by filling a first insulating film in the first trench, patterning the second film surrounded by the device isolation region, forming a dummy Forming a gate layer; introducing an impurity into the semiconductor substrate using the dummy gate layer as a mask; forming a gate electrode on the semiconductor substrate surrounded by the dummy gate layer and the first insulating film; Forming the second insulating film; removing the dummy gate layer and the first film;
Forming a trench, forming a gate insulating film on the semiconductor substrate in the second trench, and forming a gate electrode on the gate insulating film in the second trench. A method for manufacturing a semiconductor device provided. A gate insulating film and a first insulating film on the semiconductor substrate;
Forming a first groove by selectively removing an upper portion of the first conductive film, the gate insulating film, and the semiconductor substrate; and forming a first groove on the first groove. Embedding a first insulating film to form an element isolation region; forming a dummy film on the first conductive film and the element isolation region; patterning the dummy film and the first conductive film Forming an island-like layer, introducing impurities into the semiconductor substrate using the island-like layer as a mask, and forming the gate surrounded by the island-like layer and the first insulating film. Forming a second insulating film on the insulating film; removing the dummy film to form a second groove; and forming a second groove on the first conductive film in the second groove. A first conductive film and a second conductive film. The method of manufacturing a semiconductor device including a step of forming a gate electrode. A step of forming a first groove in the semiconductor substrate; a step of burying a first insulating film in the first groove to form an element isolation region; and a semiconductor surrounded by the element isolation region. Forming a first film and a second film on a surface of a substrate, patterning the second film to form a dummy gate layer, and using the dummy gate layer as a mask to form the semiconductor. Introducing an impurity into a substrate; forming a second insulating film on the first film surrounded by the dummy gate layer and the first insulating film; Removing a portion of the first film to form a second groove; forming a gate insulating film on the semiconductor substrate in the second groove; and forming a gate insulating film in the second groove. Step of forming a gate electrode on a gate insulating film The method of manufacturing a semiconductor device having a. A step of forming a dummy gate layer on a semiconductor substrate; a step of forming a dummy sidewall on a side surface of the dummy gate layer; a step of depositing an interlayer insulating film over the entire surface; Removing the dummy gate layer until the upper surface thereof is exposed; removing the dummy gate layer to form a groove; forming a gate electrode in the groove; removing the dummy sidewall to form a cavity; Forming a sidewall, and filling the cavity with a sidewall material to form a sidewall. 5. A step of forming a gate insulating film on a semiconductor substrate; a step of forming a gate electrode on the gate insulating film; a step of forming a dummy sidewall on a side surface of the gate electrode; Depositing a film; removing the interlayer insulating film until the upper surface of the gate electrode is exposed; removing the dummy sidewall to form a cavity; filling the cavity with a sidewall material; Forming a side wall. 6. A step of forming a dummy gate layer on a semiconductor substrate, and a step of forming a sidewall insulating film having an etching selectivity on a side surface of the dummy gate layer between a material forming the dummy gate layer. Depositing an interlayer insulating film on the entire surface; removing the interlayer insulating film until an upper surface of the dummy gate layer is exposed; removing the dummy gate layer to form a groove; A method for manufacturing a semiconductor device, comprising: a step of forming a gate insulating film on a bottom surface of a groove; and a step of forming a gate electrode in the groove having the gate insulating film formed on the bottom surface. 7. A semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and the gate insulating film formed on a side surface of the gate electrode. A semiconductor device comprising: an insulating layer made of the same material; and a silicon nitride film formed on a side surface of the insulating layer. 8. A step of forming a dummy gate made of a first silicon nitride film on a semiconductor substrate; a step of forming a first silicon oxide film on the entire surface; and forming a second silicon nitride film on the entire surface. Forming an interlayer insulating film on the entire surface; polishing the interlayer insulating film until the dummy gate is exposed; removing the upper portions of the first and second silicon nitride films; Forming a first groove, filling the first groove with a second silicon oxide film, performing anisotropic etching on the second silicon oxide film,
Exposing the dummy gate while leaving the second silicon oxide film on the second silicon nitride film; removing the dummy gate to form a second groove; Forming a gate insulating film on the bottom surface and side surface of the trench, and forming a gate electrode in the second groove having the gate insulating film formed on the bottom surface and side surface.