JP2000150633A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an element separation insulating film from etched even if, at opening a contact hole, an opening region of the contact hole and an element separation insulating film of STI(shallow trench isolation) type comprises an overlap region. SOLUTION: An STI-type element separation insulating film STI where a semiconductor substrate 10 comprising an active region is formed, an inter- layer insulating film of silicon oxide is formed on its upper layer, a contact hole CH is so opened as to connect to the active region of the semiconductor substrate through the inter-layer insulating film, and an embedded electrode 34 is so formed in the contact hole as to connect to the active region of the semiconductor substrate. Here, at least, a part of the region near the interface between the element separation region and the active region, the element separation insulating film is formed, or coated, of a material 23a whose etching selection ratio is different from the insulating film (an insulating body such as silicon nitride, a conductive body such as metal film).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device which is isolated by a trench element isolation method and has a contact connection with a substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a typical method for element isolation of a semiconductor device, LOCOS (local oxidation of silic
on) method, SIMOX (separati
on byimplanted oxigen) or STI (Shallow
Various methods such as a Trench Isolation method have been developed.

In particular, among the above, the element isolation insulating film formed by the STI method can form the element isolation insulating film with the minimum line width in the manufacturing process, and can increase the degree of integration of the semiconductor device. The semiconductor device can be miniaturized and miniaturized. A semiconductor device having an element isolation insulating film formed by the STI method and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 29 is a plan view of a semiconductor device having an element isolation insulating film formed by the STI method. The trench for element isolation formed on the semiconductor substrate is buried with an insulator to form a trench-type element isolation insulating film STI, and a region separated by the element isolation insulating film STI becomes an active region AR. A gate electrode G is formed in a direction orthogonal to the formation direction of the element isolation insulating film STI, and a source / drain region is formed in the active region AR on both sides of the gate electrode G,
An active region immediately below the gate electrode G becomes a channel forming region, and is formed by a MOS field effect transistor (MO).
SFET; MOS Field Effect Transistor). In addition, a contact hole CH reaching the source / drain region is opened and connected to an upper wiring (not shown).

FIG. 3 is a sectional view taken along line AA ′ in FIG.
0 is shown. An element isolation groove is formed in the silicon semiconductor substrate 10 in which the well 11 is formed, and silicon oxide is buried therein, so that an element isolation insulating film 22a (ST
I) is formed. The region separated by the element isolation insulating film 22a becomes the active region. The lower gate electrode 30a of polysilicon and the upper gate electrode 3 of tungsten silicide are formed on the upper layer of the semiconductor substrate 10 via the gate insulating film 24.
A gate electrode 32 having a polycide structure, which is a laminate of 1a, is formed. On both sides of the gate electrode 32, the active region has a low concentration diffusion layer 12 containing a conductive impurity at a low concentration.
LDD composed of a high concentration diffusion layer 13 and a high concentration diffusion layer 13
(Lightly Doped Drain) source / drain diffusion layers are formed to constitute a MOSFET.
A gate coating film 25 of silicon oxide is formed to cover the gate electrode 32, and an interlayer insulating film 26 made of silicon oxide is formed on the entire surface of the gate coating film 25. A contact hole CH penetrating through the interlayer insulating film 26 and the gate coating film 25 and reaching the source / drain diffusion layer is opened, and a buried electrode 34 made of, for example, tungsten buried in the contact hole CH is formed. For example, the upper wiring 35 made of aluminum is connected to the source / drain diffusion layers by contact.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 31A, a silicon oxide layer is formed to a thickness of about 10 nm on the silicon semiconductor substrate 10 by, for example, a thermal oxidation method to form a sacrificial oxide film 20.

Next, as shown in FIG. 31B, for example, a CVD (Chemical Vapor Dep.)
silicon nitride is deposited to a thickness of about 150 nm by an osition method, a mask layer 21 is formed, and a resist film having a pattern for opening an element isolation region is formed by a photolithography process, and RIE (reactive ion etching) is performed. ), And the mask layer 21 is patterned so as to open the element isolation region.

Next, as shown in FIG. 31C, etching such as RIE is performed using the mask layer 21 as a mask.
A trench-shaped groove reaching above the semiconductor substrate 10 is formed, and is used as an element isolation groove T. The depth of the groove formed in the semiconductor substrate 10 is, for example, about 400 nm.

Next, as shown in FIG. 32D, after a not-shown trench inner wall protective film is formed on the inner wall of the isolation trench T by, for example, a thermal oxidation method, for example, a high density plasma CV is formed.
Silicon oxide is deposited on the entire surface by the method D, and the trench T for device isolation is buried.
To form According to the high-density plasma CVD method, the silicon oxide in the isolation trench T has good coverage.

Next, as shown in FIG. 32E, in order to improve the polishing uniformity in the next step, a resist film (not shown) is patterned by a photolithography step.
Etching such as RIE is performed to reduce the thickness of the thick silicon oxide element isolation insulating film layer deposited on a wide active region such as the region B.

Next, as shown in FIG.
By a (Chemical Mechanical Polishing) method, the upper surface of the element isolation insulating film layer 22 is polished and removed until about half the thickness of the mask layer 21 is removed, thereby forming an individually separated element isolation insulating film 22a.

Next, as shown in FIG. 33 (g), the mask layer 21 is removed by wet etching such as hot phosphoric acid at 80 ° C. using the sacrificial oxide film 20 as a stopper. At this time, the mask layer 21 after the above-described CMP process is used.
The element isolation insulating film 22a has a shape that protrudes from the surface of the semiconductor substrate 10 corresponding to the thickness (for example, about 50 nm) of the semiconductor substrate 10, and the shoulder of the element isolation insulating film 22a by etching when the mask layer 21 is removed. The portion (region near the interface between the element isolation region and the active region) is processed into a step shape.

Next, as shown in FIG. 33 (h), a resist film (not shown) for opening a well formation region is patterned and a well 11 is formed by ion-implanting a conductive impurity D1.

Next, as shown in FIG. 33 (i), after removing, for example, the sacrificial oxide film 20 by etching such as wet etching, a silicon oxide layer is formed with a thickness of several nm by, for example, a thermal oxidation method. The gate insulating film 24 is used.
Next, polysilicon is deposited on the upper layer of the gate insulating film 24 by, for example, a CVD method, a lower gate electrode layer 30 is formed, and tungsten silicide is further deposited to form an upper gate electrode layer 31. Next, a resist film R1 is formed in a pattern of the gate electrode by a photolithography process.

Next, as shown in FIG. 34 (j), etching such as RIE is performed using the resist film R1 as a mask, and the upper gate electrode layer 31 and the lower gate electrode layer 30 are sequentially patterned to form A gate electrode 32 having a polycide structure including a lower gate electrode 30a of silicon and an upper gate electrode 31a of tungsten silicide
To form At this time, the thin gate insulating film 24 is also processed into a gate electrode pattern.

Next, as shown in FIG. 34 (k), for example, C is produced using TEOS (tetraethylorthosilicate) as a raw material.
Silicon oxide is deposited on the entire surface by the VD method to form a gate coating film 25.

Next, as shown in FIG. 34 (l), a conductive impurity D2 is ion-implanted using the gate electrode 32 as a mask, and a low concentration diffusion layer is formed in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. 12 is formed.

Next, as shown in FIG. 35 (m), the gate electrode 32 is covered by, for example, a CVD method, and polysilicon is deposited on the entire surface to form a sidewall mask layer 33.

Next, as shown in FIG. 35 (n), etch back is performed by, for example, RIE or the like, leaving the sidewall mask layer 33 on both sides of the gate electrode 32 and removing the other portions. The wall mask layer 33a is formed.

Next, as shown in FIG. 35 (o), the conductive impurities D are formed using the sidewall mask layer 33a as a mask.
3 is ion-implanted to form a high-concentration diffusion layer 13 connected to the low-concentration diffusion layer 12 in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. As a result, a source / drain diffusion layer having an LDD structure is formed.

Next, as shown in FIG. 36 (p), etching such as RIE is performed using the gate coating film 25 as a stopper to remove the sidewall mask layer 33a.

Next, as shown in FIG. 36 (q), silicon oxide such as BPSG is deposited by, for example, a CVD method, and an interlayer insulating film 26 is formed.

Next, as shown in FIG. 37 (r), the upper surface of the interlayer insulating film 26 is polished by, for example, a CMP method to flatten the interlayer insulating film 26. Alternatively, the surface can be flattened by a method such as reflow or etch back.

Next, as shown in FIG. 37 (s), a resist film R2 having a contact hole opening pattern is formed on the interlayer insulating film 26 by photolithography.

Next, as shown in FIG. 38 (t), an etching process such as RIE or plasma etching is performed using the resist film R2 as a mask to open a contact hole CH exposing the source / drain diffusion layer.

Next, as shown in FIG. 38 (u), a conductive impurity D4 is ion-implanted in order to compensate for the connection by the contact. In the subsequent steps, for example, the inside of the contact hole is filled with tungsten to form a buried electrode 34 connected to the source / drain diffusion layer, and an upper layer wiring such as aluminum is formed thereover. To the device.

[0027]

However, when the semiconductor device having the element isolation insulating film formed by the STI method is further miniaturized as described above, the width of the wiring such as the gate electrode of the transistor formed on the substrate is reduced. In addition, the space between the STI type element isolation insulating films, that is, the width of the active region also becomes narrow. When a contact hole connecting the active region and the upper layer wiring is opened in a semiconductor device in which the distance between the wiring such as the gate electrode and the distance between the element isolation insulating films are narrowed as described above, when forming a resist film for opening the contact hole, There is almost no margin for misalignment, and further, as shown in FIG. 29, it is necessary to design on the assumption that the contact hole CH and the element isolation insulating film STI have an overlapping region.

When the contact hole CH and the element isolation insulating film STI have an overlapping region as described above, the interlayer insulating film 26 and the element isolation insulating film 24a are usually formed of a silicon oxide-based insulator. As shown in t), in the contact hole opening step, the silicon oxide forming the element isolation insulating film 24a in the region where the contact hole CH overlaps the element isolation insulating film 24a (STI) is also etched. At this time, since it is difficult to control the etch stop of the contact hole, the etching proceeds to the bottom of the element isolation groove at the time of over-etching, and a slit-shaped groove S is formed as shown in the drawing. Will be. The reason why the slit-shaped groove S is formed is that if the contact hole CH and the element isolation insulating film STI are not designed on the assumption that they have an overlapping area, there is no margin for misalignment, This can occur even if a slight misalignment occurs.

When the slit-shaped groove S is formed as described above, a buried electrode buried in the contact hole has a structure penetrating the source / drain diffusion layer of the transistor, so that a leak current is generated.
In order to prevent this, in the ion implantation step for contact compensation shown in FIG. 38 (u), a conductive impurity is introduced at a high concentration, which is as deep as the depth of the isolation trench, and the contact compensation impurity region 14 is formed. Need to be formed so as to cover the slit-shaped groove S.

As described above, when a conductive impurity is introduced at a high concentration, which is as deep as the depth of the isolation trench for contact compensation, the semiconductor device is miniaturized. The fourteen impurities affect the impurity profile in the channel formation region immediately below the gate electrode 32, and deteriorate the transistor characteristics as compared with the design.

In the step of removing the mask layer 21 shown in FIG. 33 (g), the shoulder of the element isolation insulating film 22a (the area near the interface between the element isolation region and the active region) is processed into a step shape. When the step shape is large, in the etching process of processing the gate electrode, which is a subsequent process, FIG.
As shown in FIG. 9A, for example, a residue 30b of polysilicon forming the lower gate electrode 30a may remain in the step-shaped portion, which may cause a short circuit of the wiring. FIG. 39 (b) corresponds to a cross-sectional view taken along the line CC ′ of FIG. 29, and as shown in FIG. If the residue 30b is left on the step-shaped portion of the shoulder of the element isolation insulating film, a short circuit between the gate electrodes 32 formed in parallel occurs.

The present invention has been made in view of the above-described problems. Therefore, the present invention has an overlapping region between the opening region of the contact hole and the STI type element isolation insulating film when the contact hole is opened. In particular, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can prevent the element isolation insulating film from being etched.

[0033]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate having an active region and an element formed on the semiconductor substrate in an element isolation region separating the active region. An isolation groove, an element isolation insulating film embedded in the element isolation groove, an insulating film formed on the semiconductor substrate, and penetrating the insulating film so as to be connected to an active region of the semiconductor substrate. An open contact hole, and a buried electrode buried in the contact hole and formed so as to be connected to an active region of the semiconductor substrate, and at least a region near an interface between the element isolation region and the active region. In part, the element isolation insulating film is formed or covered with a material having a different etching selectivity from the insulating film.

In the above-described semiconductor device of the present invention, the element isolation insulating film is formed of a material having a different etching selectivity from the insulating film in at least a part of the region near the interface between the STI type element isolation region and the active region. Due to the covering, in the manufacturing process, when a contact hole connected to the active region of the semiconductor substrate is opened by etching, a material portion having an etching selectivity different from that of the insulating film can serve as an etching stopper. Therefore, when the opening region of the contact hole and the STI type element isolation insulating film overlap due to misalignment, or when the STI type element isolation insulating film has an overlapping area by design, the element isolation insulating film is prevented from being etched. can do.

The above-described semiconductor device of the present invention is preferably
The semiconductor device has an overlapping region of the element isolation region and the opening region of the contact hole, and the element isolation insulating film in the overlapping region is formed or covered with a material having an etching selectivity different from that of the insulating film. When the contact hole is opened, the opening area of the contact hole and S
Even if the TI type element isolation insulating film has an overlapping region,
Etching of the element isolation insulating film can be prevented.

The semiconductor device of the present invention is preferably
The insulating film is formed of silicon oxide, and in a region near an interface between the device isolation region and the active region, at least a surface layer of the device isolation insulating film is formed of silicon nitride. In the region near the interface between the element isolation region and the active region, the etching selectivity between the surface layer of the element isolation insulating film and the insulating film can be made different.

The above-described semiconductor device of the present invention is preferably
The insulating film is formed of silicon oxide, and in a region near an interface between the device isolation region and the active region, at least a portion of the device isolation insulating film that is in contact with an inner wall surface of the device isolation groove is formed of silicon nitride. ing. In the region near the interface between the element isolation region and the active region, the etching selectivity between the element isolation insulating film and the insulating film at the portion in contact with the inner wall surface of the element isolation groove can be made different.

The above-described semiconductor device of the present invention is preferably
The insulating film is formed of silicon oxide, and the element isolation insulating film is covered with a conductive film in at least a part of a region near an interface between the element isolation region and the active region. More preferably, the conductive film covers an active region of the semiconductor substrate in the contact hole. More preferably, the conductive film is a metal film or a silicon-containing film such as polysilicon or a high melting point metal silicide. In at least a part of the region near the interface between the element isolation region and the active region, the element isolation insulating film may be covered with a material having a different etching selectivity from the insulating film.

The above semiconductor device of the present invention is preferably
An active region of the semiconductor substrate having a channel forming region;
A field effect transistor is further formed, further comprising a gate insulating film formed above the channel formation region, and a gate electrode formed above the gate insulating film. When a semiconductor device including a field-effect transistor is manufactured, the semiconductor device can be formed without deteriorating characteristics of the transistor due to impurities for contact compensation.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a mask layer having a pattern for opening an element isolation region on a semiconductor substrate having an active region; Forming a device isolation groove in the semiconductor substrate using the mask as a mask, forming a main element isolation insulating film by filling the element isolation groove with an insulator, removing the mask layer, A step of forming a sub-element isolation insulating film at least above the main element isolation insulating film in a region near the interface between the main element isolation region and the active region; and Forming an insulating film over the semiconductor substrate, and opening a contact hole in the insulating film exposing an active region of the semiconductor substrate;
Forming a buried electrode connected to an active region of the semiconductor substrate by burying the conductor in the contact hole.

The method of manufacturing a semiconductor device of the present invention described above
A mask layer having a pattern for opening an element isolation region is formed on a semiconductor substrate having an active region, an element isolation groove is formed in the semiconductor substrate using the mask layer as a mask, and the element isolation groove is buried with an insulator. An element isolation insulating film is formed, and the mask layer is removed. Next, in a region near the interface between the main element isolation region and the active region, a sub-element isolation insulating film is formed at least above the main element isolation insulating film. Next, an insulating film is formed on the semiconductor substrate using a material having a different etching selectivity from the sub-element isolation insulating film, a contact hole is formed in the insulating film to expose an active region of the semiconductor substrate, and a conductor is formed in the contact hole. To form an embedded electrode connected to the active region of the semiconductor substrate.

According to the method of manufacturing a semiconductor device of the present invention, after forming the main element isolation insulating film in the element isolation trench, at least the main element isolation region is formed in the region near the interface between the main element isolation region and the active region. A sub-element isolation insulating film is formed on the insulating film, and an insulating film is formed on the semiconductor substrate using a material having a different etching selectivity from the sub-element isolation insulating film. It can play a role of an etching stopper at the time of etching opening, and when an opening region of a contact hole and an STI element isolation insulating film overlap due to misalignment, or when an overlapping region is provided by design. In addition, it is possible to prevent the element isolation insulating film from being etched.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the main element isolation region and the opening region of the contact hole have an overlapping region, and in the step of forming the sub-element isolation insulating film, the main element isolation insulating film in the overlapping region is Formed to cover. Even when the opening region of the contact hole overlaps with the STI-type element isolation insulating film at the time of opening the contact hole, the element isolation insulating film can be prevented from being etched.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, in the step of removing the mask layer, a step is formed at a shoulder of the main element isolation insulating film which is a region near an interface between the main element isolation region and the active region, and the sub element isolation insulating layer is formed. The step of forming a film includes forming a sub-element isolation insulating film layer over the entire surface by covering the step-shaped portion, and etching back while leaving the sub-element isolation insulating film layer in the step-shaped portion. And As a result, a sub-element isolation insulating film can be formed on the upper layer of the main element isolation insulating film, and since the shoulder at the shoulder of the main element isolation insulating film is buried with an insulator, the gate can be formed in a later step. In the step of forming a wiring such as an electrode, it is possible to prevent the etching residue of the conductor that causes a short circuit from remaining in the step-shaped portion.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming the main element isolation insulating film, a step of burying the element isolation groove to form an insulator over the entire surface; and forming the insulator embedded in the element isolation groove. Removing the insulator while leaving. More preferably, the step of removing the insulator while leaving the insulator embedded inside the element isolation groove is performed by a chemical mechanical polishing process. As a result, a main element isolation insulating film buried in the element isolation trench can be formed.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the sub-element isolation insulating film is formed of silicon nitride, and the insulating film is formed of silicon oxide. Thus, the etching selectivity between the sub-element isolation insulating film and the insulating film can be made different.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the active region of the semiconductor substrate has a channel forming region, after the step of forming the sub-element isolation insulating film,
Before the step of forming the insulating film, the method further includes a step of forming a gate insulating film over the channel formation region, and a step of forming a gate electrode over the gate insulating film. Form. When a semiconductor device including a field-effect transistor is manufactured, the semiconductor device can be formed without deteriorating characteristics of the transistor due to impurities for contact compensation.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a mask layer having a pattern for opening an element isolation region on a semiconductor substrate having an active region; Forming a device isolation groove in the semiconductor substrate using the mask as a mask, forming an auxiliary element isolation insulating film by covering an inner wall of the element isolation groove with an insulator, and forming the sub element isolation insulating film. Forming a main element isolation insulating film by filling the element isolation trench with an insulator, removing the mask layer, and forming the semiconductor using a material having an etching selectivity different from that of the sub element isolation insulating film. Forming an insulating film on an upper layer of the substrate; opening a contact hole in the insulating film exposing an active region of the semiconductor substrate; embedding a conductive material in the contact hole In a step of forming a buried electrode connected to the active region of the semiconductor substrate.

The method of manufacturing a semiconductor device according to the present invention described above
A mask layer having a pattern for opening an element isolation region is formed on a semiconductor substrate having an active region, and an element isolation groove is formed in the semiconductor substrate using the mask layer as a mask. Next, a sub-element isolation insulating film is formed by covering the inner wall of the element isolation groove with an insulator. Next, the element isolation trench in which the sub-element isolation insulating film is formed is filled with an insulator to form a main element isolation insulating film, the mask layer is removed, and a material having a different etching selectivity from the sub-element isolation insulating film. As a result, an insulating film is formed on the semiconductor substrate. Next, a step of opening a contact hole for exposing the active region of the semiconductor substrate in the insulating film, filling the contact hole with a conductor to form a buried electrode connected to the active region of the semiconductor substrate.

According to the method of manufacturing a semiconductor device of the present invention described above, after forming the sub-element isolation insulating film by covering the inner wall of the element isolation groove with the insulator, the element having the sub-element isolation insulating film formed thereon is formed. The isolation trench is filled with an insulator to form a main element isolation insulating film, and an insulating film is formed on the semiconductor substrate using a material having a different etching selectivity from the sub-element isolation insulating film. The sub-element isolation insulating film formed on the inner wall portion of the substrate can serve as an etching stopper when opening the contact hole by etching.
Due to misalignment, contact hole opening area and ST
When the I-type element isolation insulating film has an overlapping region or has an overlapping region by design, the element isolation insulating film can be prevented from being etched.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, the main element isolation region and the opening region of the contact hole have an overlap region, and in the step of forming the sub-element isolation insulating film, the inside of the element isolation trench in the overlap region is formed. It is formed by embedding. Even when the opening region of the contact hole overlaps with the STI-type element isolation insulating film at the time of opening the contact hole, the element isolation insulating film can be prevented from being etched.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming the main element isolation insulating film, a step of burying the element isolation groove to form an insulator over the entire surface; and forming the insulator embedded in the element isolation groove. Removing the insulator while leaving. More preferably, the step of removing the insulator while leaving the insulator embedded inside the element isolation groove is performed by a chemical mechanical polishing process. As a result, a main element isolation insulating film buried in the element isolation trench can be formed.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the sub-element isolation insulating film is formed of silicon nitride, and the insulating film is formed of silicon oxide. Thus, the etching selectivity between the sub-element isolation insulating film and the insulating film can be made different.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, the active region of the semiconductor substrate has a channel forming region, and after the step of removing the mask layer and before the step of forming the insulating film, a gate insulating film is formed above the channel forming region. The method further includes a step of forming and a step of forming a gate electrode on the gate insulating film, thereby forming a field effect transistor. When a semiconductor device including a field-effect transistor is manufactured, the semiconductor device can be formed without deteriorating characteristics of the transistor due to impurities for contact compensation.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a mask layer having a pattern for opening an element isolation region on a semiconductor substrate having an active region; Forming a device isolation groove in the semiconductor substrate using a mask as a mask, forming an element isolation insulating film by filling the device isolation groove with an insulator, removing the mask layer, A step of covering at least an upper layer of the element isolation insulating film with a conductive film in a region near an interface between the isolation region and the active region; and forming an insulating film on the semiconductor substrate using a material having a different etching selectivity from the conductive film. Opening a contact hole through the insulating film so as to connect to the active region of the semiconductor substrate in the insulating film; It embeds a conductor within Lumpur and a step of forming a buried electrode connected to the active region of the semiconductor substrate.

The method for manufacturing a semiconductor device of the present invention described above
A mask layer having a pattern for opening an element isolation region is formed on a semiconductor substrate having an active region, an element isolation groove is formed in the semiconductor substrate using the mask layer as a mask, and the element isolation groove is filled with an insulator. An isolation insulating film is formed, and the mask layer is removed. Next, in a region near the interface between the element isolation region and the active region, at least the upper layer of the element isolation insulating film is covered with a conductive film. Next, an insulating film is formed on the semiconductor substrate using a material having a different etching selectivity from the conductive film, and a contact hole is formed in the insulating film so as to connect to the active region of the semiconductor substrate. A buried electrode connected to the active region of the semiconductor substrate is formed by burying the inside with a conductor.

According to the above-described method for manufacturing a semiconductor device of the present invention, after forming the element isolation insulating film and removing the mask layer, the region near the interface between the element isolation region and the active region is removed.
At least the upper layer of the element isolation insulating film is covered with a conductive film, and the insulating film is formed on the semiconductor substrate using a material having a different etching selectivity from the conductive film. When the opening region of the contact hole and the STI type element isolation insulating film overlap each other due to misalignment, or when the element isolation insulating film has an overlapping area by design, it can serve as a stopper. Etching can be prevented.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, the main element isolation region and the opening region of the contact hole have an overlapping region, and the step of forming the conductive film covers an upper layer of the element isolation insulating film in the overlapping region. Formed. When opening the contact hole, the contact hole opening area and ST
Even when the I-type element isolation insulating film has an overlapping region, the element isolation insulating film can be prevented from being etched.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, in the step of forming the conductive film, the conductive film is formed so as to cover an active region of the semiconductor substrate in the contact hole. The conductive film functioning as an etching stopper can be formed as a pad electrode of a contact connecting to the active region.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming the element isolation insulating film, a step of burying the element isolation groove to form an insulator over the entire surface, and leaving the insulator embedded inside the element isolation groove. Removing the insulator.
More preferably, the step of removing the insulator while leaving the insulator embedded inside the element isolation groove is performed by a chemical mechanical polishing process. Thereby, an element isolation insulating film embedded in the element isolation groove can be formed.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the conductive film is formed of a metal film or a silicon-containing film such as polysilicon or refractory metal silicide, and the insulating film is formed of silicon oxide.
Thus, the etching selectivity between the conductive film and the insulating film can be made different.

The method for manufacturing a semiconductor device according to the present invention described above
Preferably, the active region of the semiconductor substrate has a channel forming region, and after the step of removing the mask layer and before the step of forming the insulating film, a gate insulating film is formed above the channel forming region. The method further includes a step of forming and a step of forming a gate electrode on the gate insulating film, thereby forming a field effect transistor. When a semiconductor device including a field-effect transistor is manufactured, the semiconductor device can be formed without deteriorating characteristics of the transistor due to impurities for contact compensation.

[0063]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a plan view of a semiconductor device having an element isolation insulating film formed by the STI method according to the present embodiment. The trench for element isolation formed on the semiconductor substrate is buried with an insulator to form a trench-type element isolation insulating film STI, and a region separated by the element isolation insulating film STI becomes an active region AR.
A gate electrode G is formed in a direction orthogonal to the formation direction of the element isolation insulating film STI, source / drain regions are formed in active regions AR on both sides of the gate electrode G, and an active region in a portion directly below the gate electrode G is formed. As a channel forming region, a MOS type field effect transistor (MOSF
ET; MOS Field Effect Transistor). In addition, a contact hole CH reaching the source / drain region is opened and connected to an upper wiring (not shown).

In the above-described semiconductor device, the element isolation insulating film STI is formed of the main element isolation insulating film S made of silicon oxide.
TI1 and a sub-element isolation insulating film ST made of silicon nitride
I2 and the main element isolation insulating film STI1
The sub-element isolation insulating film ST is formed on the shoulder of the main element isolation insulating film STI1 which is a region near the interface between the active element AR and the active element AR.
I2 is formed. Further, in order to miniaturize the semiconductor device, the design is such that the contact hole CH and the element isolation insulating film STI have an overlapping region.

FIG. 2 is a sectional view taken along the line AA ′ in FIG. Silicon semiconductor substrate 10 with well 11 formed
An element isolation groove is formed therein, and a main element isolation insulating film 22a made of silicon oxide therein and a shoulder portion of the main element isolation insulating film 22a serving as a region near an interface between the main element isolation region 22a and the active region. The element isolation insulating film STI is formed from the sub-element isolation insulating film 23a made of silicon nitride formed in the step-shaped portion. Element isolation insulating film STI
The region separated by becomes the active region. A gate electrode 32 having a polycide structure, which is a laminate of a lower gate electrode 30a of polysilicon and an upper gate electrode 31a of tungsten silicide, is formed on the upper layer of the semiconductor substrate 10 with a gate insulating film 24 interposed therebetween. Source / drain of an LDD (Lightly Doped Drain) structure composed of a low concentration diffusion layer 12 containing a conductive impurity at a low concentration and a high concentration diffusion layer 13 containing a high concentration at both sides of the gate electrode 32 in the active region. A diffusion layer is formed, and a MOSFET is configured.

A gate coating film 25 of silicon oxide is formed to cover the gate electrode 32, and an interlayer insulating film 26 made of silicon oxide is formed on the entire surface of the gate coating film 25. A contact hole CH penetrating through the interlayer insulating film 26 and the gate coating film 25 and reaching the source / drain diffusion layer is opened, and the buried electrode 3 made of, for example, tungsten buried in the contact hole CH.
4 is formed on the upper wiring 3 made of, for example, aluminum.
5 and the source / drain diffusion layers are contact-connected.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 3A, a silicon oxide layer is formed on a silicon semiconductor substrate 10 by, for example, a thermal oxidation method.
The sacrificial oxide film 20 is formed with a thickness of 0 nm.

Next, as shown in FIG. 3B, a CVD (Chemical Vapor Depos)
Silicon nitride is deposited to a thickness of about 150 nm by the ition method, a mask layer 21 is formed, and a resist film having a pattern for opening an element isolation region is formed by a photolithography process, and RIE (reactive ion etching) is performed. )
The mask layer 21 is patterned so as to open the element isolation region.

Next, as shown in FIG. 3C, etching such as RIE is performed using the mask layer 21 as a mask to form a trench-shaped groove reaching above the semiconductor substrate 10.
This shall be an element isolation groove T. The depth of the groove formed in the semiconductor substrate 10 is, for example, about 400 nm.

Next, as shown in FIG. 4D, after a not-shown trench inner wall protective film is formed on the inner wall of the isolation trench T by, for example, a thermal oxidation method, for example, high-density plasma CVD is performed.
Silicon oxide is deposited on the entire surface by a method, and the trench T for device isolation is buried.
To form According to the high-density plasma CVD method, the silicon oxide in the isolation trench T has good coverage.

Next, as shown in FIG. 4E, in order to improve the polishing uniformity in the next step, a resist film (not shown) is patterned by a photolithography step, and R
Etching such as IE is performed to thin the main element isolation insulating film layer 22 of thick silicon oxide deposited on a wide active region such as the region B, for example.

Next, as shown in FIG.
By a (Chemical Mechanical Polishing) method, the main element isolation insulating film 22a is individually polished and removed from the upper surface of the main element isolation insulating film layer 22 until a film thickness of about half of the mask layer 21 is removed, thereby forming an individually separated main element isolation insulating film 22a. .

Next, as shown in FIG.
By wet etching such as hot phosphoric acid at 0 ° C,
The mask layer 21 is removed using the sacrificial oxide film 20 as a stopper. At this time, the main element isolation insulating film 22a has a shape that protrudes from the surface of the semiconductor substrate 10 corresponding to the thickness (for example, about 50 nm) of the mask layer 21 after the above-described CMP step. By etching at the time of removing 21, the shoulder 22b (region near the interface between the element isolation region and the active region) of the main element isolation insulating film 22a is processed into a stepped shape.

Next, as shown in FIG.
By the VD method, silicon nitride is deposited to a thickness of about 100 nm on the entire surface by covering the shoulder portion 22b of the main element isolation insulating film 22a to form the sub element isolation insulating film layer 23.

Next, as shown in FIG. 5I, the shoulder 2 of the main element isolation insulating film 22a is etched by RIE or the like.
Sub-element isolation insulating film layer 23 except for the portion covering 2b
Is etched back to form a sub-element isolation insulating film layer 23a. Main element isolation insulating film 22a and sub element isolation insulating film layer 23
a forms an element isolation insulating film STI.

Next, as shown in FIG. 6J, a resist film (not shown) for opening a well formation region is formed by patterning, and a conductive impurity D1 is ion-implanted to form a well 11.

Next, as shown in FIG. 6K, for example, after removing the sacrificial oxide film 20 by etching such as RIE, a silicon oxide layer is formed to a thickness of several nm by, for example, thermal oxidation, and the gate is removed. The insulating film 24 is used. Next, polysilicon is deposited on the upper layer of the gate insulating film 24 by, for example, a CVD method, a lower gate electrode layer 30 is formed, and tungsten silicide is further deposited to form an upper gate electrode layer 31. Next, a resist film R1 is formed in a pattern of the gate electrode by a photolithography process.

Next, as shown in FIG. 7L, etching such as RIE is performed using the resist film R1 as a mask.
Upper gate electrode layer 31 and lower gate electrode layer 30
Are sequentially patterned to form a gate electrode 32 having a polycide structure including a lower gate electrode 30a of polysilicon and an upper gate electrode 31a of tungsten silicide. At this time, the thin gate insulating film 24 is also processed into a gate electrode pattern.

Next, as shown in FIG.
CV made from EOS (tetraethylorthosilicate)
A gate oxide film 25 is formed by depositing silicon oxide on the entire surface by the method D.

Next, as shown in FIG. 7 (n), a conductive impurity D2 is ion-implanted using the gate electrode 32 as a mask, and a low concentration diffusion layer is formed in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. 12 is formed.

Next, as shown in FIG.
The gate electrode 32 is covered by the VD method, and polysilicon is deposited on the entire surface to form a sidewall mask layer 33.

Next, as shown in FIG.
Etchback is performed by etching such as IE, and the other portions except the sidewall mask layer 33 on both sides of the gate electrode 32 are removed to form a sidewall mask layer 33a.

Next, as shown in FIG. 8 (q), the conductive impurity D3 is formed using the sidewall mask layer 33a as a mask.
To form a high concentration diffusion layer 13 connected to the low concentration diffusion layer 12 in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. As a result, a source / drain diffusion layer having an LDD structure is formed.

Next, as shown in FIG. 9 (r), etching such as RIE is performed using the gate coating film 25 as a stopper to remove the silowall mask layer 33a.

Next, as shown in FIG.
Silicon oxide such as BPSG is deposited by VD method,
An interlayer insulating film 26 is formed.

Next, as shown in FIG. 10 (t), the upper surface of the interlayer insulating film 26 is polished by, for example, a CMP method to flatten the interlayer insulating film 26. Alternatively, the surface can be flattened by a method such as reflow or etch back.

Next, as shown in FIG. 10 (u), a resist film R2 having a contact hole opening pattern is formed on the interlayer insulating film 26 by photolithography.

Next, as shown in FIG. 11 (v), an etching process such as RIE or plasma etching is performed using the resist film R2 as a mask to open a contact hole CH exposing the source / drain diffusion layer.

Next, as shown in FIG. 11 (w), a conductive impurity D4 is ion-implanted to compensate for the connection by the contact. In the subsequent steps, for example, the contact hole is buried with tungsten to form a buried electrode 34 connected to the source / drain diffusion layer, and an upper layer wiring such as aluminum is further formed thereon to form the semiconductor shown in FIG. To the device.

According to the method of manufacturing a semiconductor device of the present embodiment, the main isolation insulating film 22a is formed in the isolation trench T.
Is formed, a sub-element isolation insulating film 23a of silicon nitride is formed on the shoulder of the main element isolation insulating film 22a near the interface between the main element isolation region and the active region. Since the interlayer insulating film 26 is formed in the upper layer of the semiconductor substrate using silicon oxides having different ratios, the sub-element isolation insulating film 23a serves as an etching stopper when the contact hole is opened by etching, and the opening region of the contact hole and the STI Even if the element isolation insulating film of the mold has an overlapping region, the element isolation insulating film can be prevented from being etched. Further, even when the opening region of the contact hole and the STI element isolation insulating film are not designed to have an overlapping region, an overlapping region of the opening region of the contact hole and the STI element isolation insulating film occurs due to misalignment. Sometimes, it is possible to prevent the element isolation insulating film from being etched. Therefore, it is not necessary to increase the amount of impurities introduced for contact compensation.

In the above-described method for manufacturing a semiconductor device, the step-shaped portion at the shoulder of the main element isolation insulating film is buried with silicon nitride. It is possible to prevent the etching residue of polysilicon which causes a short circuit from remaining in the shape portion.

Second Embodiment A plan view of a semiconductor device in which element isolation is performed by the STI method according to the present embodiment is substantially the same as that of the first embodiment, and a description thereof will be omitted. FIG. 12 is a sectional view taken along line AA ′ in FIG. An element isolation groove is formed in the silicon semiconductor substrate 10 in which the well 11 is formed, and a sub-element isolation insulating film 28a made of silicon nitride is formed to cover an inner wall surface of the element isolation groove. A main element isolation insulating film 22a made of silicon oxide is buried in the element isolation groove in which the element isolation insulating film 28a is formed,
An element isolation insulating film STI is composed of the main element isolation region 22a and the sub element isolation insulating film 28a. The region separated by the element isolation insulating film STI becomes the active region. A gate electrode 32 having a polycide structure, which is a laminate of a lower gate electrode 30a of polysilicon and an upper gate electrode 31a of tungsten silicide, is formed on the upper layer of the semiconductor substrate 10 with a gate insulating film 24 interposed therebetween. Source / drain diffusion layers having an LDD structure including a low concentration diffusion layer 12 containing a low concentration of conductive impurities and a high concentration diffusion layer 13 containing a high concentration are formed in the active region on both sides of the gate electrode 32. And a MOSFET is configured.

A gate coating film 25 of silicon oxide is formed to cover the gate electrode 32, and an interlayer insulating film 26 made of silicon oxide is formed on the entire surface of the gate coating film 25. A contact hole CH penetrating through the interlayer insulating film 26 and the gate coating film 25 and reaching the source / drain diffusion layer is opened, and the buried electrode 3 made of, for example, tungsten buried in the contact hole CH.
4 is formed on the upper wiring 3 made of, for example, aluminum.
5 and the source / drain diffusion layers are contact-connected.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 13A, a silicon oxide layer is formed to a thickness of about 10 nm on the silicon semiconductor substrate 10 by, for example, a thermal oxidation method to form a sacrificial oxide film 20.

Next, as shown in FIG. 13B, polysilicon is deposited on the sacrificial oxide film 20 by, for example, the CVD method, a lower mask layer 36 is formed, and the CVD is performed.
Silicon nitride is deposited by a method to form an upper mask layer 27. The lower mask layer 36 and the upper mask layer 27 form a mask layer. Next, a resist film having a pattern for opening an element isolation region is formed by a photolithography step, and an etching process such as RIE (reactive ion etching) is performed to separate the upper mask layer 27 and the lower mask layer 36 from each other. Pattern processing is performed to open the region.

Next, as shown in FIG. 13 (c), etching such as RIE is performed using the upper mask layer 27 as a mask to form a trench-shaped groove reaching above the semiconductor substrate 10, and a trench T for element isolation is formed. And The depth of the groove formed in the semiconductor substrate 10 is, for example, about 400 nm.

Next, as shown in FIG. 14D, the upper mask layer 2 is formed by wet etching such as hot phosphoric acid at 80 ° C. using the lower mask layer 36 as a stopper.
7 is removed.

Next, as shown in FIG. 14E, a not-shown trench inner wall protection film is formed on the inner wall of the isolation trench T by, for example, a thermal oxidation method, and then a trench-like element isolation is formed by, for example, a CVD method. Cover the inner wall of the groove T
Silicon nitride is deposited to a thickness of nm to form a sub-element isolation insulating film layer 28.

Next, as shown in FIG. 14F, the entire surface is etched back by etching such as RIE, except for the sub-element isolation insulating film layer 28 which covers the inner wall of the isolation trench T. Then, a sub-element isolation insulating film layer 28a covering the inner wall of the element isolation trench T is formed.

Next, as shown in FIG. 15G, silicon oxide is deposited on the entire surface by, for example, a high-density plasma CVD method, and the element isolation trench T in which the sub-element isolation insulating film layer 28a is formed is buried. The main element isolation insulating film layer 22 is formed. According to the high-density plasma CVD method, the silicon oxide in the isolation trench T has good coverage.

Next, as shown in FIG. 15H, in order to improve the polishing uniformity in the next step, a resist film (not shown) is patterned by a photolithography step.
By performing etching such as RIE, the main element isolation insulating film layer 22 of thick silicon oxide deposited on a wide active region such as the region B is thinned.

Next, as shown in FIG.
By the method, the main element isolation insulating film 22a is polished and removed from the upper surface of the main element isolation insulating film layer 22 until a film thickness of about half of the lower mask layer 36 is removed, thereby forming an individually separated main element isolation insulating film 22a. The element isolation insulating film STI is composed of the main element isolation insulating film 22a and a pair of sub element isolation insulating film layers 28a covering the inner walls of the element isolation trenches T.

Next, as shown in FIG. 16J, the lower mask layer 36 is removed by etching such as RIE using the sacrificial oxide film 20 as a stopper. At this time, the thickness of the lower mask layer 36 (for example, 5
(Approximately 0 nm).
Has a shape protruding from the surface of the semiconductor substrate 10 in a convex manner.

Next, as shown in FIG. 16 (k), a resist film (not shown) for opening a well forming region is patterned and a well 11 is formed by ion-implanting a conductive impurity D1.

Next, as shown in FIG. 16 (l), for example, after removing the sacrificial oxide film 20 by etching such as RIE, a silicon oxide layer is formed with a thickness of several nm by, for example, thermal oxidation, and the gate is removed. The insulating film 24 is used. Next, polysilicon is deposited on the upper layer of the gate insulating film 24 by, for example, a CVD method, a lower gate electrode layer 30 is formed, and tungsten silicide is further deposited to form an upper gate electrode layer 31. Next, a resist film R1 is formed in a pattern of the gate electrode by a photolithography process.

Next, as shown in FIG. 17 (m), etching such as RIE is performed using the resist film R1 as a mask, and the upper gate electrode layer 31 and the lower gate electrode layer 30 are sequentially patterned to form a polycrystalline silicon film. A gate electrode 32 having a polycide structure including a lower gate electrode 30a of silicon and an upper gate electrode 31a of tungsten silicide
To form At this time, the thin gate insulating film 24 is also processed into a gate electrode pattern.

Next, as shown in FIG. 17N, silicon oxide is deposited on the entire surface by a CVD method using TEOS as a raw material, for example, to form a gate coating film 25.

Next, as shown in FIG. 17 (o), a conductive impurity D2 is ion-implanted using the gate electrode 32 as a mask, and a low concentration diffusion layer is formed in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. 12 is formed.

Next, as shown in FIG. 18 (p), the gate electrode 32 is covered by, for example, a CVD method and polysilicon is deposited on the entire surface to form a sidewall mask layer 33.

Next, as shown in FIG. 18 (q), etch-back is performed by, for example, RIE or the like, leaving the sidewall mask layer 33 on both sides of the gate electrode 32 and removing the other portions. The wall mask layer 33a is formed.

Next, as shown in FIG. 18 (r), the conductive impurities D are formed using the sidewall mask layer 33a as a mask.
3 is ion-implanted to form a high-concentration diffusion layer 13 connected to the low-concentration diffusion layer 12 in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. As a result, a source / drain diffusion layer having an LDD structure is formed.

Next, as shown in FIG. 19 (s), etching such as RIE is performed using the gate coating film 25 as a stopper to remove the silowall mask layer 33a.

Next, as shown in FIG. 19 (t), silicon oxide such as BPSG is deposited by, for example, a CVD method, and an interlayer insulating film 26 is formed.

Next, as shown in FIG. 20 (u), the upper surface of the interlayer insulating film 26 is polished by, for example, a CMP method to flatten the interlayer insulating film 26. Alternatively, the surface can be flattened by a method such as reflow or etch back.

Next, as shown in FIG. 20 (v), a resist film R2 having a contact hole opening pattern is formed in a pattern on the interlayer insulating film 26 by a photolithography process.

Next, as shown in FIG. 21 (w), an etching process such as RIE or plasma etching is performed using the resist film R2 as a mask to open a contact hole CH exposing the source / drain diffusion layers.

Next, as shown in FIG. 21 (x), a conductive impurity D4 is ion-implanted to compensate for the connection by the contact. In the subsequent steps, for example, the contact hole is buried with tungsten to form a buried electrode 34 connected to the source / drain diffusion layer, and an upper layer wiring such as aluminum is further formed thereon to form a semiconductor shown in FIG. To the device.

According to the method of manufacturing a semiconductor device of the present embodiment, after forming the sub-element isolation insulating film 28a of silicon nitride by covering the inner wall of the isolation trench T, the main element isolation film of silicon oxide is formed. The insulating film 22a is formed by burying it in the trench for element isolation, and the interlayer insulating film 26 is formed on the semiconductor substrate with silicon oxide having an etching selectivity different from that of the sub-element isolation insulating film. 28a serves as an etching stopper when opening the contact hole by etching, and prevents the element isolation insulating film from being etched even if the opening region of the contact hole overlaps the STI type element isolation insulating film. Can be prevented. Further, even when the opening region of the contact hole and the STI element isolation insulating film are not designed to have an overlapping region, an overlapping region of the opening region of the contact hole and the STI element isolation insulating film occurs due to misalignment. Sometimes, it is possible to prevent the element isolation insulating film from being etched. Further, in the structure of the semiconductor device of the present embodiment, even if the misalignment becomes large and the main element isolation insulating film is etched, the inner wall of the element isolation groove is covered with the sub element isolation insulating film. No leakage current occurs, and there is no need to increase the amount of impurities introduced for contact compensation.

Third Embodiment FIG. 22 is a plan view of a semiconductor device which has been subjected to element isolation by the STI method according to the present embodiment. The trench for element isolation formed on the semiconductor substrate is buried with an insulator to form a trench-type element isolation insulating film STI, and a region separated by the element isolation insulating film STI becomes an active region AR. A gate electrode G is formed in a direction orthogonal to the formation direction of the element isolation insulating film STI, source / drain regions are formed in active regions AR on both sides of the gate electrode G, and an active region in a portion directly below the gate electrode G is formed. A MOSFET is formed as a channel forming region. In addition, a contact hole CH reaching the source / drain region is opened and connected to an upper wiring (not shown).

In the above semiconductor device, the gate electrode G
A pad electrode P is formed by forming a metal film or a conductive film made of a silicon-containing film such as polysilicon or high-melting-point silicide on the surface of the active region AR on both sides. The contact hole is opened so as to expose the pad electrode P. Further, the pad electrode P is formed so as to cover not only the surface of the active region AR but also the surface of the element isolation insulating film STI in a region near the interface between the element isolation insulating film STI and the active region AR. The design is such that the contact hole CH and the element isolation insulating film STI have an overlapping region.

FIG. 2 is a sectional view taken along the line AA ′ in FIG.
3 is shown. Con semiconductor substrate 10 with well 11 formed
An element isolation groove is formed therein, and an element isolation insulating film 22a made of silicon oxide is buried in the element isolation groove. The region separated by the element isolation insulating film STI becomes the active region. The lower gate electrode 30a of polysilicon and the upper gate electrode 31 of tungsten silicide are formed on the upper layer of the semiconductor substrate 10 with the gate insulating film 24 interposed therebetween.
A gate electrode 32 having a polycide structure, which is a laminate of a, is formed. Source / drain diffusion layers having an LDD structure including a low concentration diffusion layer 12 containing a low concentration of conductive impurities and a high concentration diffusion layer 13 containing a high concentration are formed in the active region on both sides of the gate electrode 32. And MOSF
ET is configured.

A silicon oxide offset insulating film 29b is formed on the gate electrode 32, and a silicon oxide sidewall insulating film 29d is formed on both sides of the gate electrode 32. 29
b and the gate insulating film 29 from the sidewall insulating film 29d.
Is configured. The outer wall surface of the sidewall insulating film 29d, the surface of the active region (source / drain diffusion layer), and the surface of the element isolation insulating film 22a in the region near the interface between the element isolation insulating film 22a and the active region are covered with a metal film or poly. A pad electrode 37 is formed by forming a conductive film made of a silicon-containing film such as silicon or a high melting point silicide.

An interlayer insulating film 26 made of silicon oxide is formed to cover the entire surface of the transistor having the pad electrode 37. A contact hole CH penetrating through the interlayer insulating film 26 and the gate coating film 25 and reaching the pad electrode 37 is opened.
A buried electrode 34 made of, for example, tungsten embedded therein is formed, and an upper wiring 35 made of, for example, aluminum and a pad electrode (source / drain diffusion layer) are contact-connected.

A method for manufacturing the above semiconductor device will be described. The steps leading up to FIG. 24A are substantially the first steps.
In the embodiment, the process is the same as the process up to forming the lower layer and the upper gate electrode layer, and the description is omitted. However,
The sub-element isolation insulating film is not formed, and the element isolation insulating film is composed of only the main element isolation insulating film of silicon oxide. The difference is that the layer 29a is formed.

Next, as shown in FIG. 24B, etching such as RIE is performed using the resist film R1 as a mask to form the offset insulating film layer 29a, the upper gate electrode layer 31 and the lower gate electrode layer 30. By patterning in order, a gate electrode 32 with an offset insulating film 29b having a polycide structure including a lower gate electrode 30a of polysilicon and an upper gate electrode 31a of tungsten silicide is formed. At this time, the thin gate insulating film 24 is also processed into a gate electrode pattern.

Next, as shown in FIG. 24 (c), conductive impurities D2 are ion-implanted using the offset insulating film 29b as a mask, and lightly doped into the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. The layer 12 is formed.

Next, as shown in FIG. 25D, the gate electrode 32 and the offset insulating film 29b are covered by, for example, a CVD method and silicon oxide is deposited on the entire surface to form a side wall insulating film layer 29c. .

Next, as shown in FIG. 25E, etch back is performed by, for example, RIE or the like to remove the other portions except for the sidewall insulating film layer 29c on both sides of the gate electrode 32. A side wall insulating film 29d is formed. The gate insulating film 29 is composed of the offset insulating film 29b and the sidewall insulating film 29d.

Next, as shown in FIG. 25F, the conductive impurity D3 is formed using the sidewall insulating film 29d as a mask.
To form a high concentration diffusion layer 13 connected to the low concentration diffusion layer 12 in the active region of the semiconductor substrate 10 on both sides of the gate electrode 32. As a result, a source / drain diffusion layer having an LDD structure is formed.

Next, as shown in FIG. 26 (g), a conductive film such as TiN, a metal film, or a conductive film which is a silicon-containing film such as polysilicon or tungsten silicide is formed by, eg, CVD or sputtering. 1 on the whole surface
A pad electrode 37 is formed by depositing a film having a thickness of about 00 nm and processing it into a pad electrode pattern. Here, the pad electrode 37 is also formed by covering the surface of the active region (source / drain diffusion layer) and the surface of the element isolation insulating film 22a in the region near the interface between the element isolation insulating film 22a and the active region.

Next, as shown in FIG. 26H, silicon oxide such as BPSG is deposited by, eg, CVD to form an interlayer insulating film.

Next, as shown in FIG. 27I, the upper surface of the interlayer insulating film 26 is polished by, for example, a CMP method to flatten the interlayer insulating film 26. Alternatively, the surface can be flattened by a method such as reflow or etch back.

Next, as shown in FIG. 27 (j), a resist film R2 having a contact hole opening pattern is formed in a pattern on the interlayer insulating film 26 by a photolithography process.

Next, as shown in FIG. 28K, an etching process such as RIE or plasma etching is performed using the resist film R2 as a mask, and a contact hole CH exposing the pad electrode 37 is opened.

Next, as shown in FIG. 28 (l), a conductive impurity D4 is ion-implanted in order to compensate for the connection by the contact. The step of introducing the impurity can be omitted. In the subsequent steps, for example, the pad electrode 37 is filled with tungsten in the contact hole.
Embedded electrode 3 connected to (source / drain diffusion layer)
4 is formed, and an upper layer wiring such as aluminum is further formed thereon to reach the semiconductor device shown in FIG.

According to the method of manufacturing the semiconductor device of the present embodiment, the surface of the active region (source / drain diffusion layer) and the surface of the element isolation insulating film 22a in the region near the interface between the element isolation insulating film 22a and the active region are covered. Forming the pad electrode 37, the pad electrode 37 serves as an etching stopper when the contact hole is opened by etching, and the opening area of the contact hole and the STI
Even if the element isolation insulating film of the mold has an overlapping region, the element isolation insulating film can be prevented from being etched. Further, even when the opening region of the contact hole and the STI element isolation insulating film are not designed to have an overlapping region, an overlapping region of the opening region of the contact hole and the STI element isolation insulating film occurs due to misalignment. Sometimes, it is possible to prevent the element isolation insulating film from being etched. Therefore, it is not necessary to increase the amount of impurities introduced for contact compensation, and since the contact holes are opened with respect to the pad electrodes, the introduction of impurities for contact compensation can be omitted.

The present invention is applicable not only to a MOS transistor type semiconductor device such as a DRAM but also to a bipolar type semiconductor device and a B type semiconductor device.
The present invention can be applied to any semiconductor device, such as an iCMOS semiconductor device, having a contact by performing element isolation by the STI method.

The semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above embodiments. For example, a sub-element isolation insulating film serving as an etching stopper at the time of opening a contact hole is not limited to silicon nitride as long as it has an etching selectivity with an interlayer insulating film. As the gate electrode of the MOS transistor, either a method of forming a sidewall insulating film of silicon oxide as an LDD spacer or a method of forming a sidewall mask layer of polysilicon and removing it in a later step may be used. In addition, various changes can be made without departing from the gist of the present invention.

[0140]

According to the semiconductor device of the present invention, when an opening region of a contact hole and an STI type element isolation insulating film overlap due to misalignment, or when an overlapping region is provided by design, Etching of the element isolation insulating film can be prevented.

Further, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be easily manufactured. If the film has an overlapping area, or if the design has an overlapping area,
Etching of the element isolation insulating film can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view taken along line AA ′ in FIG.

FIGS. 3A and 3B are cross-sectional views illustrating a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3A illustrates up to a process of forming a sacrificial oxide film, and FIG. ,
(C) shows the steps up to the step of forming the element isolation groove.

FIG. 4 is a sectional view showing a step subsequent to that of FIG. 3;
(D) shows the steps up to the step of forming the main element isolation insulating film layer.
The figure shows up to the step of thinning the layer for the main element isolation insulating film, and FIG.

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;
(G) shows up to the step of removing the mask layer, (h) shows up to the step of forming a sub-element isolation insulating film layer, and (i) shows up to the step of forming a sub-element isolation insulating film.

FIG. 6 is a sectional view showing a step subsequent to that of FIG. 5;
(J) shows up to the step of forming a well, and (k) shows up to the step of forming a resist film of a gate pattern.

FIG. 7 is a sectional view showing a step subsequent to that of FIG. 6;
(L) shows up to the gate electrode processing step, (m) shows the gate coating film forming step, and (n) shows the low concentration diffusion layer forming step.

FIG. 8 is a sectional view showing a step subsequent to that of FIG. 7;
(O) shows the steps up to the step of forming the sidewall mask layer.
(P) shows the process up to the step of forming the sidewall mask layer.
(Q) shows the process up to the step of forming the high concentration diffusion layer.

FIG. 9 is a sectional view showing a step subsequent to that of FIG. 8;
(R) shows the process up to the step of removing the sidewall mask layer.
(S) shows up to the step of forming the interlayer insulating film.

10 is a cross-sectional view showing a step that follows the step shown in FIG. 9; FIG. 10 (t) shows the step up to the step of planarizing the interlayer insulating film, and FIG. 10 (u) shows the step up to the step of forming the resist film of the contact hole pattern.

FIG. 11 is a cross-sectional view showing a step that follows the step shown in FIG. 10;
(W) shows the steps up to the step of introducing impurities for contact compensation.

FIG. 12 is a sectional view of a semiconductor device according to a second embodiment.

FIGS. 13A and 13B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a second embodiment, in which FIG. 13A illustrates up to a sacrificial oxide film forming process and FIG. 13B illustrates a mask layer forming process; And (c) show the steps up to the step of forming the element isolation groove.

14 is a cross-sectional view showing a step that follows the step shown in FIG. 13; FIG. 14 (d) shows up to the step of removing the upper mask layer; FIG. 14 (e) shows the step up to the sub-element isolation insulating film forming step; ) Shows the steps up to the step of forming the sub-element isolation insulating film.

15 is a cross-sectional view showing a step that follows the step shown in FIG. 14; FIG. 15 (g) shows a step until a step of forming a main element isolation insulating layer;
(H) shows the process up to the step of thinning the main element isolation insulating film layer.
(I) shows up to the step of separating the main element isolation insulating film.

16 is a cross-sectional view showing a step subsequent to that of FIG. 15; (j) shows a step of removing a lower mask layer; (k) shows a step of forming a well; and (l) shows a resist of a gate pattern. The steps up to the step of forming a film are shown.

17 is a cross-sectional view showing a step subsequent to that of FIG. 16; FIG. 17 (m) shows a step until a gate electrode processing step, FIG. 17 (n) shows a step until a gate coating film forming step, and FIG. The steps up to the step of forming a diffusion layer are shown.

18 is a cross-sectional view showing a step that follows the step shown in FIG. 17; FIG. 18 (p) shows a step until a sidewall mask layer forming step, and FIG. 18 (q) shows a step until a sidewall mask layer forming step.
(R) shows up to the step of forming the high concentration diffusion layer.

FIG. 19 is a cross-sectional view showing a step subsequent to that of FIG. 18, in which (s) shows up to a step of removing a sidewall mask layer, and (t) shows up to a step of forming an interlayer insulating film.

20 is a cross-sectional view showing a step subsequent to that of FIG. 19, in which (u) shows up to a step of flattening the interlayer insulating film, and (v) shows up to a step of forming a resist film of a contact hole pattern.

FIG. 21 is a cross-sectional view showing a step that follows the step shown in FIG. 20. FIG.
(X) shows up to the step of introducing impurities for contact compensation.

FIG. 22 is a plan view of a semiconductor device according to a third embodiment.

FIG. 23 is a sectional view taken along the line AA ′ in FIG.

FIGS. 24A and 24B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a third embodiment, in which FIG. 24A illustrates a process up to a gate pattern resist film forming process, and FIG. (C) shows the steps up to the step of forming the low concentration diffusion layer.

25 is a cross-sectional view showing a step subsequent to that of FIG. 24. FIG. 25 (d) shows a step until a sidewall insulating film forming step, and FIG. 25 (e) shows a step until a side wall insulating film forming step.
(F) shows up to the step of forming the high concentration diffusion layer.

26 is a cross-sectional view showing a step subsequent to that of FIG. 25. FIG. 26 (g) shows up to a step of forming a pad electrode, and FIG. 26 (h) shows a step up to a step of forming an interlayer insulating film.

27 is a cross-sectional view showing a step subsequent to that of FIG. 26. FIG. 27 (i) shows up to the step of flattening the interlayer insulating film, and FIG. 27 (j) shows the step up to the step of forming a resist film of a contact hole pattern.

28 is a cross-sectional view showing a step that follows the step shown in FIG. 27. FIG.
(L) shows up to the step of introducing impurities for contact compensation.

FIG. 29 is a plan view of a semiconductor device according to a conventional example.

FIG. 30 is a sectional view taken along line AA ′ in FIG. 29;

FIGS. 31A to 31C are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a conventional example, in which FIG. 31A illustrates up to a sacrificial oxide film forming process, FIG.
(C) shows the steps up to the step of forming the element isolation groove.

FIG. 32 is a cross-sectional view showing a step that follows the step shown in FIG. 31. FIG.
(E) shows the process up to the step of thinning the element isolation insulating film layer,
Indicates the steps up to the step of separating the element isolation insulating film.

33 is a cross-sectional view showing a step subsequent to that of FIG. 32. FIG. 33 (g) shows a step until a mask layer is removed, FIG. 33 (h) shows a step until a well is formed, and FIG. 33 (i) shows a resist film of a gate pattern. Up to the formation step.

FIG. 34 is a cross-sectional view showing a step that follows the step shown in FIG. 33; (j) shows a step until a gate electrode processing step; (k) shows a step until a gate coating film forming step; The steps up to the step of forming a diffusion layer are shown.

35 is a cross-sectional view showing a step subsequent to that of FIG. 34. FIG. 35 (m) shows a step until a sidewall mask layer forming step, and FIG. 35 (n) shows a step until a sidewall mask layer forming step.
(O) shows up to the step of forming the high concentration diffusion layer.

FIG. 36 is a cross-sectional view showing a step that follows the step shown in FIG. 35. FIG. 36 (p) shows up to the step of removing the sidewall mask layer, and FIG. 36 (q) shows the step up to the step of forming the interlayer insulating film.

FIG. 37 is a cross-sectional view showing a step that follows the step shown in FIG. 36. FIG. 37 (r) shows up to the step of flattening the interlayer insulating film, and FIG.

FIG. 38 is a cross-sectional view showing a step that follows the step shown in FIG. 37. FIG.
(U) shows up to the step of introducing impurities for contact compensation.

FIGS. 39 (a) and 39 (b) are sectional views and (b) are perspective views for explaining the problems of the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Well, 12 ... Low concentration diffusion layer, 13 ... High concentration diffusion layer, 14 ... Contact compensation impurity region, 20 ... Sacrificial oxide film, 21 ... Mask layer, 22 ...
(Main) element isolation insulating film layer, 22a ... (Main) element isolation insulating film, 23, 28 ... Sub-element isolation edge film layer, 23a, 28
a: sub-element isolation insulating film, 24: gate insulating film, 25, 2
9: Gate coating film, 26: Interlayer insulating film, 27: Upper mask layer, 29a: Offset insulating film layer, 29b: Offset insulating film, 29c: Sidewall insulating film layer, 29
d: sidewall insulating film, 30: lower gate electrode layer, 30a: lower gate electrode, 30b: residue, 31: upper gate electrode layer, 31a: upper gate electrode, 32: gate electrode, 33: sidewall mask Layer, 33a ...
Sidewall mask layer, 34 ... embedded electrode, 35 ...
Upper wiring, 36: Lower mask layer, 37: Pad electrode, C
H: contact hole, T: groove for element isolation, R1, R2
... resist film, D1 to D4 ... conductive impurities, S: slit-shaped groove, STI1: main element isolation insulating film, STI2: sub element isolation insulating film, STI: element isolation insulating film, G: gate electrode, AR: active Area, P: Pad electrode.

Continued on the front page F term (reference) 4M104 BB18 CC01 EE02 FF26 GG15 GG16 HH04 HH14 HH20 5F032 AA34 AA44 AA45 AA46 AA47 AA54 AA70 AA77 AA79 BA01 CA17 DA02 DA04 DA23 DA24 DA33 DA53 5F048 AA01 AC01 AB03 AC03 BB08 BB09 BC06 BF02 BF07 BG01 BG14 5F083 AD00 GA06 GA09 GA30 JA02 JA32 JA35 JA36 JA39 JA53 JA56 MA06 MA17 MA19 MA20 NA01 PR03 PR12 PR21 PR40

Claims (29)

[Claims] A semiconductor substrate having an active region; an element isolation groove formed in the semiconductor substrate in an element isolation region separating the active region; an element isolation insulating film embedded in the element isolation groove; An insulating film formed on the semiconductor substrate; a contact hole opened through the insulating film so as to be connected to an active region of the semiconductor substrate; Having an embedded electrode formed so as to be connected to the active region, wherein at least a part of the region near the interface between the element isolation region and the active region, the element isolation insulating film has an etching selectivity with the insulating film. A semiconductor device formed or covered with a different material. 2. The semiconductor device according to claim 1, further comprising: an overlap region between the device isolation region and the contact hole opening region, wherein the device isolation insulating film in the overlap region is formed or covered with a material having an etching selectivity different from that of the insulating film. The semiconductor device according to claim 1, wherein: 3. The device according to claim 1, wherein the insulating film is formed of silicon oxide, and at least a surface portion of the device isolation insulating film is formed of silicon nitride in a region near an interface between the device isolation region and the active region. 2. The semiconductor device according to 1. 4. The device according to claim 1, wherein the insulating film is formed of silicon oxide, and in a region near an interface between the device isolation region and the active region, at least a portion of the device isolation insulating film that is in contact with an inner wall surface of the device isolation groove. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of silicon nitride. 5. The device according to claim 1, wherein the insulating film is formed of silicon oxide, and the element isolation insulating film is covered with a conductive film in at least a part of a region near an interface between the element isolation region and the active region. 2. The semiconductor device according to 1. 6. The semiconductor device according to claim 5, wherein said conductive film covers an active region of said semiconductor substrate in said contact hole. 7. The semiconductor device according to claim 5, wherein said conductive film is a metal film. 8. The semiconductor device according to claim 5, wherein said conductive film is a silicon-containing film. 9. An active region of the semiconductor substrate has a channel forming region, further comprising a gate insulating film formed on the channel forming region and a gate electrode formed on the gate insulating film. 2. The semiconductor device according to claim 1, wherein a field effect transistor is formed. 10. A step of forming a mask layer having a pattern for opening an element isolation region on a semiconductor substrate having an active region, a step of forming an element isolation groove in the semiconductor substrate using the mask layer as a mask, Forming a main element isolation insulating film by burying the inside of the element isolation groove with an insulator; removing the mask layer; at least the main element in a region near an interface between the main element isolation region and the active region. Forming a sub-element isolation insulating film on an upper layer of the isolation insulating film; forming an insulating film on the semiconductor substrate using a material having a different etching selectivity from the sub-element isolation insulating film; Opening a contact hole exposing an active region of the semiconductor substrate; and burying a conductive material in the contact hole and connecting to the active region of the semiconductor substrate. The method of manufacturing a semiconductor device having a step of forming a buried electrode that. 11. The main element isolation region and an opening region of the contact hole have an overlap region, and in the step of forming the sub-element isolation insulation film, the main element isolation insulation film in the overlap region The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is formed so as to cover the semiconductor device. 12. In the step of removing the mask layer, a step is formed at a shoulder of the main element isolation insulating film which is a region near an interface between the main element isolation region and the active region; The step of forming an insulating film includes forming a sub-element isolation insulating film layer over the entire surface by covering the step-shaped portion, and etching back while leaving the sub-element isolation insulating film layer in the step-shaped portion. And a process.
0. A method for manufacturing a semiconductor device according to item 0. 13. The step of forming the main element isolation insulating film, the step of burying the element isolation trench to form an insulator over the entire surface, and the step of forming the insulator buried inside the element isolation trench. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising: 14. The method for manufacturing a semiconductor device according to claim 13, wherein the step of removing the insulator while leaving the insulator buried inside the element isolation groove is performed by a chemical mechanical polishing process. 15. The method according to claim 10, wherein the sub-element isolation insulating film is formed of silicon nitride, and the insulating film is formed of silicon oxide. 16. The semiconductor device according to claim 1, wherein the active region of the semiconductor substrate has a channel formation region, and after the step of forming the sub-element isolation insulating film and before the step of forming the insulating film, The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a gate insulating film, and a step of forming a gate electrode on the gate insulating film, wherein the field-effect transistor is formed. 17. A step of forming a mask layer having a pattern for opening an element isolation region on a semiconductor substrate having an active region, a step of forming an element isolation groove in the semiconductor substrate using the mask layer as a mask, Forming a sub-element isolation insulating film by covering an inner wall of the element isolation groove with an insulator; and filling the element isolation groove with the sub-element isolation insulating film formed with an insulator with a main element isolation insulating film. A step of forming a film; a step of removing the mask layer; a step of forming an insulating film on the semiconductor substrate using a material having an etching selectivity different from that of the sub-element isolation insulating film; Forming a contact hole exposing an active region of the substrate; and forming a buried electrode connected to the active region of the semiconductor substrate by filling the contact hole with a conductor. The method of manufacturing a semiconductor device having a that step. 18. The method according to claim 18, wherein the main element isolation region and the opening region of the contact hole have an overlapping region, and the step of forming the sub-element isolation insulating film includes the step of forming the element isolation trench in the overlapping region. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the semiconductor device is formed by embedding. 19. The step of forming the main element isolation insulating film, the step of burying the element isolation groove to form an insulator over the entire surface, and the step of forming the insulator buried inside the element isolation groove. Removing the insulator while leaving a gap. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising: 20. The method of manufacturing a semiconductor device according to claim 19, wherein the step of removing the insulator while leaving the insulator embedded inside the element isolation groove is performed by a chemical mechanical polishing process. 21. The method of manufacturing a semiconductor device according to claim 17, wherein the sub-element isolation insulating film is formed of silicon nitride, and the insulating film is formed of silicon oxide. 22. An active region of the semiconductor substrate having a channel forming region, wherein after the step of removing the mask layer and before the step of forming the insulating film, a gate insulating film is formed above the channel forming region. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising: forming a field effect transistor; and forming a gate electrode on the gate insulating film. 23. A step of forming a mask layer having a pattern for opening an element isolation region on a semiconductor substrate having an active region; a step of forming an element isolation groove in the semiconductor substrate using the mask layer as a mask; A step of forming an element isolation insulating film by filling the inside of the element isolation groove with an insulator; a step of removing the mask layer; and at least the element isolation insulating film in a region near an interface between the element isolation region and the active region. Covering the upper layer with a conductive film, forming an insulating film on the semiconductor substrate using a material having an etching selectivity different from that of the conductive film, and connecting the insulating film to an active region of the semiconductor substrate. Opening a contact hole penetrating the insulating film, and burying a conductive material in the contact hole to contact the active region of the semiconductor substrate. The method of manufacturing a semiconductor device having a step of forming a buried electrode. 24. The main element isolation region and the opening region of the contact hole have an overlapping region. In the step of forming the conductive film, an upper layer of the element isolation insulating film in the overlapping region is covered. 24. The method for manufacturing a semiconductor device according to claim 23, wherein the semiconductor device is formed. 25. The method according to claim 23, wherein the step of forming the conductive film covers the active region of the semiconductor substrate in the contact hole. 26. The step of forming the element isolation insulating film, the step of burying the element isolation trench to form an insulator over the entire surface, and the step of forming the insulator buried inside the element isolation trench. 24. The method of manufacturing a semiconductor device according to claim 23, further comprising the step of removing the insulator while leaving it. 27. The method of manufacturing a semiconductor device according to claim 26, wherein the step of removing the insulator while leaving the insulator embedded inside the element isolation groove is performed by a chemical mechanical polishing process. 28. The method according to claim 23, wherein the conductive film is formed of a metal film or a silicon-containing film, and the insulating film is formed of silicon oxide. 29. An active region of the semiconductor substrate having a channel forming region, wherein after the step of removing the mask layer and before the step of forming the insulating film, a gate insulating film is formed above the channel forming region. 24. The method of manufacturing a semiconductor device according to claim 23, further comprising: forming a field effect transistor; and forming a gate electrode on the gate insulating film.