JPH0618235B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with an insulating film for protecting a pn junction formed on a semiconductor substrate from a short circuit due to sintering of a metal wire. Regarding

<Prior Art> FIG. 4 is a sectional view showing a typical conventional bipolar transistor. In the figure, 1 is a semiconductor substrate, 2 is a base region, and 3 is an emitter region.
A base electrode 4 is electrically connected to the base region 2 through a contact hole, while an emitter electrode 5 is in contact with the emitter region 3 through a contact hole. In such a conventional bipolar transistor, since the lithography process for forming the contact holes 7 and 8 for the base electrode 4 and the emitter electrode 5 respectively and the lithography process for forming the base electrode 4 and the emitter electrode 5 are separate, The mask used in the lithography process at the time of formation is formed with a pattern that allows for a mask alignment error in each lithography process. As a result, the base electrode 4
The distance between the emitter electrode 5 and the
The occupying area was wide. Such an increase in the area of the base region 2 is not suitable for improving the integration density, and
This increases the collector junction capacitance and further increases the base resistance due to the large distance between the base electrode 4 and the emitter electrode 5, which causes deterioration of the high frequency characteristics of the bipolar transistor.

In view of the drawbacks of the conventional bipolar transistor, the applicant of the present invention, in the patent application relating to the same application as the present application,
Exposing a region of the first conductivity type on a surface portion of the semiconductor substrate and electrically connecting a first wiring to the region of the first conductivity type;
A step of covering the conductivity type region and the first wiring with an insulating layer to form a hole in the insulating layer to expose a part of the first conductivity type region; and impurities from the hole formed in the insulating layer. A semiconductor including a step of forming a second conductivity type area by introducing it into a part of the first conductivity type area and a step of forming a second wiring electrically connected to the second conductivity type area through the hole. The method of forming the wiring of the device was proposed.

<Problems to be Solved by the Invention> In the wiring forming method for a semiconductor device according to the application filed on the same day as the present application, a mask for pattern-forming the first wiring is provided between the first wiring and the second wiring. Only the mask alignment error with the mask for forming the hole for forming the second conductivity type region may be set as a margin, and the distance between the second wiring and the first wiring electrically connected to the second conductivity type region. Could be significantly reduced.

However, in the above-described wiring forming method, in order to reduce the area of the first conductivity type region, it is necessary to position the first wiring as close to the bonding surface between the semiconductor substrate and the first conductivity type region as possible. Desirably, when the first wiring is made of metal, sintering occurs when the semiconductor substrate is heated when the second conductivity type region is formed, and the semiconductor substrate and the first conductivity type region are short-circuited. there were.

<Means for Solving Problems> The present invention provides an impurity region formed by introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into a surface portion of the semiconductor substrate defined by the first insulating film, In a semiconductor device having a metal wiring electrically connected to an impurity region and extending from the impurity region to the first insulating film, a semiconductor device that extends from above the first insulating film to a surface of the impurity region. The gist is that a second insulating film is provided, and the metal wiring is bonded to the impurity region through a hole formed in the second insulating film.

<Operation and Effect> In the semiconductor device according to the present invention, even if the position of the hole formed in the second insulating film deviates from the predetermined position, a short circuit between the semiconductor substrate and the impurity region does not occur. Further, in order to reduce the area of the impurity region, the connection position between the metal wiring and the impurity region is made as close as possible to the oxide film, and even if there is a heating step after the formation of the metal wiring, the semiconductor substrate and the impurity due to sintering are No short circuit to the area will occur. For these reasons, positioning of mask alignment when forming holes in the second insulating film can be eased, and the manufacturing yield of semiconductor devices can be improved.

That is, the second insulating film extends from above the first insulating film to the surface of the impurity region. Therefore, at the junction surface between the semiconductor substrate and the impurity region, the length from the surface of the impurity region to the upper surface of the second insulating film is equal to the thickness of the first insulating film and the thickness of the second insulating film. It is the total added. Further, the depth at which the holes are formed in the insulating film can usually be controlled by the thickness of the insulating film.

Therefore, even if the position of mask alignment of the hole of the second insulating film is deviated and the position reaches the joint surface between the semiconductor substrate and the impurity region, the first insulating film is formed at the joint surface between the semiconductor substrate and the impurity region. And a part of the second insulating film on the impurity region remains.

Therefore, even if the metal wiring is formed, the remaining second insulating film isolates the metal wiring from the bonding surface between the semiconductor substrate and the impurity region. Therefore, it is possible to ease the positioning of the mask alignment when forming the holes in the second insulating film.

Therefore, even if there is a heating step after the formation of the metal wiring, a short circuit between the semiconductor substrate and the impurity region due to sintering does not occur. Further, the manufacturing yield of semiconductor devices can be improved.

<Embodiment> FIGS. 1 and 2 are a sectional view and a plan view showing an embodiment of the present invention. This embodiment is an application of the present invention to a bipolar transistor, and 11 is a semiconductor substrate. 12
Indicates a base region, and 13 indicates an emitter region. The base region 12 is defined by a patterned oxide film 14, and a refractory metal base electrode 15 electrically connected to the base region 12 extends from the base region 12 onto the oxide film 14. . This base electrode 15
Is covered with an interlayer insulating film 16.
The aluminum emitter electrode 17 laid therethrough penetrates the interlayer insulating film 16 and is electrically connected to the emitter region 13. A thin oxide film 18 is interposed between the oxide film 14 and the base electrode 15 described above, and the oxide film 18 isolates the base electrode 15 from the bonding surface between the semiconductor substrate 11 and the base region 12.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described. First, the surface of the n-type semiconductor substrate 11 is thermally oxidized to grow an oxide film 14, and then the oxide film 14 is selectively removed by etching to expose a part of the surface of the semiconductor substrate 11. A base region 12 is formed by introducing p-type impurities into the semiconductor substrate 11. In the subsequent step, the base region 12 is thinly covered with the CVD oxide film 18,
Remove except 4 neighborhoods. Alternatively, as the step of forming the base region 12, the base region 12 may be formed and a thermal oxide film may be grown on the base region 12, and the thermal oxide film may be used instead of the CVD oxide film 18. After that, a refractory metal such as molybdenum, titanium, or tungsten is deposited on the entire surface of the CVD oxide film 18 by sputtering or the like, and the refractory metal is patterned by a lithography process to form the base electrode 15. After forming the base electrode 15, silicon dioxide is deposited to completely cover the base electrode 15. The silicon dioxide interlayer insulating film 16 is selectively removed by a lithography process to expose a part of the base region 12. After that, an n-type impurity is ion-implanted into the exposed base region 12 and annealed to form an emitter region 13, and the emitter region 13 and the interlayer insulating film 16 are entirely covered with aluminum. Patterning is performed to complete the emitter electrode 17.

Therefore, in one embodiment, the base electrode 15 and the emitter electrode 1
The distance from 7 can be determined in consideration of only the mask alignment error, and the area of the base region 12 can be reduced. Moreover, even if heated in the process of forming the emitter region 13, the oxide film 18 is interposed, so that a short circuit between the semiconductor substrate 11 and the base electrode 15 due to sintering does not occur.

FIG. 3 is a cross-sectional view showing another embodiment of the present invention, in which the same components as those in the above-mentioned one embodiment are designated by the same reference numerals and detailed description thereof will be omitted. In another embodiment of FIG. 3, after covering the base region 12 with a thin oxide film 28, the base electrode 1
A contact hole 29 is formed to connect 5 to the base region 12, and then a base electrode 15 is formed. Therefore, the oxide film 28 is provided with the contact hole 29 and the contact hole 3 for the emitter electrode, which is formed in the later step together with the interlayer insulating film 16.
The surface of the semiconductor substrate is covered except for the portion where 0 is formed.

[Brief description of drawings]

FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a plan view of one embodiment, FIG. 3 is a sectional view of another embodiment, and FIG. 4 is a sectional view of a conventional example. 11 ... Semiconductor substrate, 12 ... Impurity region, 14 ... Oxide film, 15 ... Metal wiring, 18 ... Insulating film.

Claims (1)

[Claims] 1. An impurity region formed by introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into a surface portion of the semiconductor substrate defined by a first insulating film, and electrically connected to the impurity region. A semiconductor device having a metal wiring extending from an impurity region to the first insulating film, wherein a second insulating film extending from the first insulating film to a surface of the impurity region is provided. The semiconductor device is characterized in that the wiring is joined to the impurity region through a hole formed in the second insulating film.