JPS59161864A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59161864A JPS59161864A JP3627783A JP3627783A JPS59161864A JP S59161864 A JPS59161864 A JP S59161864A JP 3627783 A JP3627783 A JP 3627783A JP 3627783 A JP3627783 A JP 3627783A JP S59161864 A JPS59161864 A JP S59161864A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- emitter
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 150000002500 ions Chemical class 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 230000035515 penetration Effects 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007363 ring formation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置に係り、特に外部イオンの絶縁膜中
への侵入を防止するための安定化構造に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a stabilizing structure for preventing external ions from entering an insulating film.
ｔｂ＋ 従来技術と問題点
半導体素子表面には、特性の安定化のための保護膜とし
て絶縁膜が設けられているが、この絶縁膜中に外部から
イオンが侵入すると界面単位が発生し、特性劣化を生し
る。これを防止するため、ベース、エミッタ及びコレク
タ電極のうちのいずれかを、上記絶縁膜上に半導体基板
表面に露出するｐ−ｎ接合の端部上洛導出して形成する
構造が多く用いられる。しかしこの構造では絶縁膜上を
完全に電極で覆うことは不可能であり、まだ高耐圧素子
の場合には絶縁膜の耐圧に限度があるため、ベース電極
をコレクタ領域上に或いはコレクタ電極をハース領域上
にまで張り出すことは出来ない。tb+ Conventional technology and problems An insulating film is provided on the surface of a semiconductor element as a protective film to stabilize the characteristics, but when ions enter this insulating film from the outside, interface units are generated and the characteristics deteriorate. produce. To prevent this, a structure is often used in which one of the base, emitter, and collector electrodes is formed on the insulating film by extending it over the end of the pn junction exposed on the surface of the semiconductor substrate. However, with this structure, it is impossible to completely cover the insulating film with the electrode, and in the case of high-voltage devices, there is still a limit to the withstand voltage of the insulating film, so the base electrode is placed on the collector region or the collector electrode is placed on the hearth. It cannot extend beyond the area.
従って上記従来方式では外部イオンの絶縁膜中への侵入
を完全に防止することは不可能であった。Therefore, in the conventional method described above, it is impossible to completely prevent external ions from entering the insulating film.
（Ｃ） 発明の目的
本発明の目的は半導体素子表面に形成された絶縁膜中へ
の外部イオンの侵入を防止し得る改良された半導体装置
を提供することにある。(C) Object of the Invention An object of the present invention is to provide an improved semiconductor device that can prevent external ions from entering into an insulating film formed on the surface of a semiconductor element.
（ｄ） 発明の構成
本発明の特徴は、半導体基体と、前記半導体基体内に形
成され当該半導体基体の表面において終端する少なくと
も一つのｐ−ｎ接合と、前記ｐ−ｎ接合の表出部上に配
置された絶縁膜と、前記絶縁股上に配置された多結晶あ
るいは非晶質の半導体層と、前記ｐ−ｎ接合を形成する
半導体領域に前記多結晶あるいは非晶質の半導体層を挟
んで対向して配設され且つ前記多結晶あるいは非晶質の
半導体層に接触する電極とを有することにある。(d) Structure of the Invention The present invention is characterized by a semiconductor substrate, at least one p-n junction formed within the semiconductor substrate and terminated at the surface of the semiconductor substrate, and an exposed portion of the p-n junction. an insulating film disposed on the insulating layer, a polycrystalline or amorphous semiconductor layer disposed on the insulating layer, and the polycrystalline or amorphous semiconductor layer sandwiched between the semiconductor region forming the p-n junction. and electrodes disposed opposite to each other and in contact with the polycrystalline or amorphous semiconductor layer.
（ｅ＋ 発明の実施例 以下本発明の一実施例を図面を参照しながら説明する。(e+ Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.
第１図及び第２図は本発明の一実施例としてのｎｐｎ型
トランジスタの構成を示す要部断面図及び平面図である
。第１図は第２図のＡ−Ａ”断面を示す。同図において
、■はｎ＋型サブストレート、２はｎ型のエピタキシア
ル成長層、３はｐ型の拡散層でベース領域、４はｎ４’
型の拡散層でエミッタ領域、５はｎ◆型の拡散層でチャ
ネル阻止層、６は絶縁膜で加熱酸化法により形成した二
酸化シリコン（５ｉＯ２）膜、７は多結晶シリコン層、
８はベース電極、９はエミッタ電極である。1 and 2 are a sectional view and a plan view of essential parts showing the structure of an npn type transistor as an embodiment of the present invention. Figure 1 shows a cross section taken along the line A-A'' in Figure 2. In the figure, ■ is an n+ type substrate, 2 is an n-type epitaxial growth layer, 3 is a p-type diffusion layer and base region, and 4 is a base region. n4'
5 is an n◆ type diffusion layer and is an emitter region, 6 is an insulating film and is a silicon dioxide (5iO2) film formed by a thermal oxidation method, 7 is a polycrystalline silicon layer,
8 is a base electrode, and 9 is an emitter electrode.
同図に示す半導体素子を製作するには、通常の製造工程
に従ってサブストレート１上にエピタキシアル成長層２
を形成し、該エピタキシアル成長Ｎ２表面に選択的に形
成した５ｉ０２膜等の絶縁膜をマスクとして、ｐ型不純
物を選択的に拡散してベース領域３を、次いでｎ型不純
物を選択的に拡散してエミッタ領域４及びチャネル阻止
層５を形成する。この段階では半導体素子表面は全面に
わた９て５ｉ０２膜６で被覆しておく。ここまでの工程
は通常の半導体装置の製造方法となんら変わるところは
ない。To manufacture the semiconductor device shown in the figure, an epitaxially grown layer 2 is deposited on a substrate 1 according to a normal manufacturing process.
Using an insulating film such as a 5i02 film selectively formed on the epitaxially grown N2 surface as a mask, p-type impurities are selectively diffused into the base region 3, and then n-type impurities are selectively diffused. Then, emitter region 4 and channel blocking layer 5 are formed. At this stage, the entire surface of the semiconductor element 9 is covered with the 5i02 film 6. The steps up to this point are no different from normal semiconductor device manufacturing methods.
次いで上記５ｉ０２膜６上に、モノシラン（ＳｉＨ４）
等のシランガスを反応ガスに用いた化学気相成長法（Ｃ
ＶＤ法）により、厚さ凡そ５０００ （人〕の多結晶シ
リコン層７を形成する。ここで留意すべきことは、上記
多結晶シリコン層７の抵抗率を高くすることであり、本
実施例ではシート抵抗を凡そ１００（ｋΩ／口〕とした
。次いでこの多結晶シリコン層７をフォトエツチング法
により選択的に除去して所望のパターンに、しかし少な
くともシリコン基板表面に露呈するエミッターベース接
合の端面上を５ｉ０２膜６を介して被覆するように形成
する。第２図に見られる如くシリコン基板表面に露呈す
る上記エミッターベース接合の端部は環状を呈するので
、この上部を被覆する多結晶シリコン層７も略環状に形
成する。Next, monosilane (SiH4) is applied on the 5i02 film 6.
Chemical vapor deposition method (C
A polycrystalline silicon layer 7 with a thickness of approximately 5000 mm is formed by VD method (VD method).What should be noted here is to increase the resistivity of the polycrystalline silicon layer 7, and in this example, The sheet resistance was set to approximately 100 (kΩ/hole). Next, this polycrystalline silicon layer 7 was selectively removed by photoetching to form a desired pattern, but at least on the end face of the emitter base junction exposed on the silicon substrate surface. 5i02 film 6. As shown in FIG. 2, the end of the emitter base junction exposed on the surface of the silicon substrate has an annular shape, so the polycrystalline silicon layer 7 covering the top thereof is It is also formed into a substantially annular shape.
次いでアルミニウム（ＡＱ）を上記多結晶シリコン層７
上を含むシリコン基板上全面に、凡そ２〔μｍ〕の厚さ
に被着せしめ、これをパターニングした後、凡そ４００
（’ｃ）の温度で約３０〔分〕加熱処理を施して、ベー
ス電極８及びエミッタ電極９を形成する。本工程におい
てベース電極８及びエミッタ電極９の端部が前記多結晶
シリコン層７の端部上に残留するようにすることが重要
である。Next, aluminum (AQ) is applied to the polycrystalline silicon layer 7.
After coating the entire surface of the silicon substrate including the top to a thickness of about 2 [μm] and patterning it,
A heat treatment is performed at a temperature of ('c) for about 30 minutes to form a base electrode 8 and an emitter electrode 9. In this step, it is important that the ends of the base electrode 8 and emitter electrode 9 remain on the ends of the polycrystalline silicon layer 7.
このように形成したベース電極８及びエミッタ電極９は
、多結晶シリコン層７とショットキ接触を形成する。こ
のショットキ接触のブレークダウン電圧は約５０（Ｖ〕
で、エミッターベース間のブレークダウン電圧（約１０
（Ｖ））に比較して遥かに高い。従ってベース電極８と
エミッタ電極９間は導電層である多結晶シリコン層９を
介して接続されているが、多結晶シリコン層９の抵抗率
が高いこと及び上述のようにショットキ接触のブレーク
ダウン電圧がエミッターベース間のブレークダウン電圧
より高いことから、エミッターベース間電流を増大させ
ることはなく、半導体装置の電気的特性には何ら問題は
ない。The base electrode 8 and emitter electrode 9 thus formed form a Schottky contact with the polycrystalline silicon layer 7. The breakdown voltage of this Schottky contact is approximately 50 (V)
The breakdown voltage between emitter and base (approximately 10
(V)) is much higher than that of (V)). Therefore, the base electrode 8 and the emitter electrode 9 are connected through the polycrystalline silicon layer 9, which is a conductive layer, but the breakdown voltage of the Schottky contact as described above is due to the high resistivity of the polycrystalline silicon layer 9 Since this is higher than the breakdown voltage between the emitter and base, the current between the emitter and base is not increased, and there is no problem with the electrical characteristics of the semiconductor device.
上述のようにして得られた本実施例の半導体装置の完成
体においては、シリコン基板表面に露呈せるｐ−ｎ接合
の端部上は総て、５ｉ０２膜６を介して電気的に接続せ
るアルミニウム（ＡＱ）層（ベース電極８．エミツタ電
極９）と多結晶シリコン層７により覆うことが出来、従
来構造の半導体装置のように絶縁膜上に導電層が欠如す
る部分は存在しない。従って本実施例では外部イオンは
これら導電層に遮られ、外部イオンの絶縁膜中への侵入
は防止される。In the completed semiconductor device of this example obtained as described above, all the ends of the p-n junction exposed on the silicon substrate surface are covered with aluminum, which is electrically connected via the 5i02 film 6. It can be covered by the (AQ) layer (base electrode 8, emitter electrode 9) and polycrystalline silicon layer 7, and there is no part where the conductive layer is missing on the insulating film unlike in a semiconductor device with a conventional structure. Therefore, in this embodiment, external ions are blocked by these conductive layers and are prevented from entering the insulating film.
かかる効果により本実施例の半導体装置は、たとえモー
ルド樹脂封止を行なっても、モールド樹脂中に含まれる
イオンが半導体素子表面の絶縁欣中に侵入することは防
止され、該絶縁膜の素子表面安定化の効果が劣化するこ
とがない。従って半導体装置の信頼度がより向上する。Due to this effect, even if the semiconductor device of this embodiment is sealed with mold resin, ions contained in the mold resin are prevented from penetrating into the insulating layer on the surface of the semiconductor element. The stabilizing effect does not deteriorate. Therefore, the reliability of the semiconductor device is further improved.
なお前記実施例にあっては、ｐ−ｎ接合上に絶縁膜を介
して配置される半導体層として多結晶シリコンを適用し
たが、本発明はこれに限定されるものではなく、非晶質
（アモルファス）半導体を適用してもよい。In the above embodiment, polycrystalline silicon was used as the semiconductor layer disposed on the pn junction with an insulating film interposed therebetween, but the present invention is not limited to this, and polycrystalline silicon ( Amorphous) semiconductors may also be used.
また上記一実施例ではｎｐｎ型半導体装置の例を掲げて
説明したが、本発明を用いてｐｎｐ型半導体装置を作成
することも勿論可能である。Furthermore, although the above embodiment has been explained using an example of an npn type semiconductor device, it is of course possible to create a pnp type semiconductor device using the present invention.
また本発明を実施するに際し、絶縁膜６を上記一実施例
に示したＳｉＯ□膜６に変えて、窒化シリコン（Ｓｉ３
Ｎａ ）成環通常使用する他の絶縁膜を用いても良い
。Furthermore, when carrying out the present invention, the insulating film 6 is replaced with the SiO□ film 6 shown in the above embodiment, and silicon nitride (Si3
(Na) Other insulating films commonly used for ring formation may also be used.
ｆｆｌ 発明の詳細
な説明した如く本発明によれば、半導体素子表面の絶縁
膜中へのイオンの侵入を防ぐことが出来るので、半導体
装置の特性特に電流増幅率ｈＦεの変動を防止すること
が出来、半導体装置の信頼度が向上する。ffl As described in detail, according to the present invention, it is possible to prevent ions from penetrating into the insulating film on the surface of the semiconductor element, and therefore it is possible to prevent variations in the characteristics of the semiconductor device, particularly the current amplification factor hFε. , the reliability of semiconductor devices is improved.
第１図及び第２図は本発明の一実施例を示す要部断面図
及び平面図である。
同図において、１はサブストレート、２はエピタキシア
ル成長層、３はベース領域、４はエミッタ領域、６は絶
縁膜、７は多結晶シリコン層、８はベース電極、９はエ
ミッタ電極を示す。FIGS. 1 and 2 are a sectional view and a plan view of essential parts showing an embodiment of the present invention. In the figure, 1 is a substrate, 2 is an epitaxial growth layer, 3 is a base region, 4 is an emitter region, 6 is an insulating film, 7 is a polycrystalline silicon layer, 8 is a base electrode, and 9 is an emitter electrode.
Claims (1)
基体の表面において終端する少なくとも一つのｐ−ｎ接
合と、前記ｐ−ｎ接合の表出部上に配置された絶縁膜と
、前記絶縁膜上に配置された多結晶あるいは非晶質の半
導体層と、前記ｐ−ｎ接合を形成する半導体領域に前記
多結晶あるいは非晶質の半導体層を挟んで対向して配設
され且つ前記多結晶あるいは非晶質の半導体層に接触す
る電極とを有することを特徴とする半導体装置。a semiconductor substrate, at least one pn junction formed within the semiconductor substrate and terminated at the surface of the semiconductor substrate, an insulating film disposed on an exposed portion of the pn junction, and an insulating film disposed on the insulating film. a polycrystalline or amorphous semiconductor layer disposed in the semiconductor region forming the p-n junction, and a polycrystalline or amorphous semiconductor layer disposed facing the semiconductor region forming the p-n junction with the polycrystalline or amorphous semiconductor layer interposed therebetween; 1. A semiconductor device comprising: an electrode in contact with an amorphous semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3627783A JPS59161864A (en) | 1983-03-04 | 1983-03-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3627783A JPS59161864A (en) | 1983-03-04 | 1983-03-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161864A true JPS59161864A (en) | 1984-09-12 |
Family
ID=12465275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3627783A Pending JPS59161864A (en) | 1983-03-04 | 1983-03-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161864A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979782A (en) * | 1972-12-08 | 1974-08-01 | ||
| JPS51130171A (en) * | 1975-05-07 | 1976-11-12 | Sony Corp | Semiconductor device |
| JPS5279661A (en) * | 1975-12-19 | 1977-07-04 | Philips Nv | Semiconductor device |
| JPS5681930A (en) * | 1979-11-07 | 1981-07-04 | Siemens Ag | Semiconductor device |
-
1983
- 1983-03-04 JP JP3627783A patent/JPS59161864A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979782A (en) * | 1972-12-08 | 1974-08-01 | ||
| JPS51130171A (en) * | 1975-05-07 | 1976-11-12 | Sony Corp | Semiconductor device |
| JPS5279661A (en) * | 1975-12-19 | 1977-07-04 | Philips Nv | Semiconductor device |
| JPS5681930A (en) * | 1979-11-07 | 1981-07-04 | Siemens Ag | Semiconductor device |
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