JPH0399439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the electronic structure of an emitter region into an ideal structure and to contrive superhigh speed operation of a semiconductor device and the improvement of the amplification factor of the device by a method wherein an intrinsic semiconductor layer is formed between a base region and the emitter region. CONSTITUTION:Patterning of a resist is performed and thereafter, an emitter region part is formed by performing an etching on an insulating layer 5 using a photomask 12 and an intrinsic semiconductor layer 3 consisting of carbon C or the like is formed on an exposed base region 2. Moreover, an N-type SiC layer 4 is provided on the layers 3 and 5 and after a patterning of a resist is performed using a photomask 13, the SiC layer 4 other than the SiC layer 4 located on the emitter region part is removed by etching and a doped N-type SiC layer 4 is formed on the emitter region. Subsequently contact holes are respectively formed in the base region and a collector region, which are located on the layer 5, and Al electrodes 6 are respectively formed on the respective regions of a base B, an emitter E and a collector C using a photomask 14.

Description

[Detailed Description of the Invention] (Summary) Regarding a method of manufacturing a semiconductor device with an a-speed operation speed, the purpose of this method is to provide an ultra-high operation speed and improve the amplification factor, by forming a collector region on a substrate. forming the base region through r
and an I culm forming an intrinsic half-layer with a predetermined thickness on the base region, and a semiconductor having an energy gap equal to or larger than that of the semiconductor material of the base region, on the intrinsic 'I'39 body layer. forming an emitter region made of a material.

(Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor HM with high operating speed.

In recent years, the operating speed of semiconductor devices has increased, but higher-speed and highly integrated semiconductor devices are required for various information processing systems with larger capacity and higher functionality.

(Conventional technology) Conventional high speed '1! The body protection will be briefly explained using a pibora transistor as an example, as shown in FIG. FIG. 4(A) is a cross-sectional view of the structure of a bipolar transistor before multilayer wiring, and FIG. 4(B) is a cross-sectional view of the structure of a bipolar transistor (HB T ). Figure 4 (A)
In the middle, E is the emitter, C is the rector, and B is the base (
The same applies to FIG. 4(B), and 20 is an n-type silicon (Si) layer grown epitaxially on a substrate (not shown).

In this Si[20], a P+ type base region 21 is diffused. The base region 21 includes a base contact portion as an external base region 21a, and an emitter contact portion and an internal base region 21b. Furthermore, an n-type emitter region 22 is diffused in the internal base region 21b. This is the so-called SST method (super self
-aligned technology), the internal base region 21b and emitter region 22 are formed as a self-line with one mask, and the electrode extraction portion and the spacing thereof are This method reduces the thickness of the polycrystalline S to the thickness of the oxide film. That is, by reducing the area of the emitter and making the internal base region 21b thinner, use in a high-speed region is addressed.

In addition, the HBF in FIG. 4(B) has n on the collector electrode C.
A type Si layer (collector region) 23 is formed, and this Si 1
A P-type 3i base region 24 is formed in 123 by diffusion. This base territory 1ii! An n-type silica carbon (Si C) IF) 25 is formed on the SiO layer 24 and bonded to the SiO layer 24, and an emitter electrode E is formed on the Si0 layer 25. That is, the base resistance is reduced by increasing the base concentration using the heterointerface, and the speed is increased by raising the peak of the frequency band ft.

[Problem to be solved by the invention]

However, since the so-called SST method relies on photolithography technology, the internal base region 2
There is a limit to reducing the thickness of 1b. Furthermore, making the internal base region 21b thinner leads to a decrease in base resistance and base-emitter breakdown voltage (between base and emitter, between base and collector, and between emitter and collector), making it impossible to increase the amplification factor of the transistor. There is a problem.

Furthermore, when forming a hetero interface as shown in FIG. 4 ([3), when growing the emitter region 25, the base region 24
There is a problem in that impurities are diffused from the surface, making it impossible to form an ideal heterointerface.

Therefore, the present invention has been made in view of the above-mentioned problems, and has an ultra-high operating speed and an improved amplification factor '1! The purpose of the present invention is to provide a method for manufacturing a body fat device.

[F stage for solving problems]

The above-mentioned problems include a step of forming a base region on a substrate via a collector region, a step of forming an intrinsic semiconductor layer of a predetermined thickness on the base region, and a step of forming a semiconductor layer of the base region on the intrinsic semiconductor layer. This is achieved by a method of manufacturing a semiconductor device including a step of forming an emitter region made of a semiconductor material having an energy gap equal to or larger than that of the semiconductor material.

[Effect]

In the present invention, an intrinsic saturated conductor layer is formed between the base region and the emitter region. As a result, when forming the emitter region, impurities are not mixed into the emitter region more than in the base region, the base concentration increases, and the base resistance can be lowered. .

Further, the semiconductor material constituting the emitter region is formed with an energy gap equal to or larger than that of the semiconductor material of the base region. As a result, the electron injection effect 5-1
That is, the amplification factor is improved.

〔Example〕

FIG. 1 shows an embodiment of the present invention. FIG. 1 is a structural sectional view illustrating a heterojunction bipolar transistor (HBr) manufactured by the method of the present invention. In FIG. 1, n-type silicon (Si) 1M1 constitutes a collector region on a collector electrode C made of aluminum (AL), etc.
is formed.

On this n5i1i1, a P type 3i is formed by diffusion and constitutes a base ffI region 2. On the base region 2, an intrinsic semiconductor layer 3 such as carbon (C) is selectively (
or the entire surface) with a predetermined thickness.

Further, n-type silica carbon (Si
C) A layer is formed and constitutes the emitter region 4. This 5iC14 is made into a petrojunction with a wI electric type opposite to that of the semiconductor material constituting the base region 2, and has an equal or large energy gap (for example, polySt, 7mol7s(a) Si , beta (β) S
! @). Then, a base electrode B formed of an aluminum (Ax) electrode 6 is formed on the base region 2 exposed from between the insulators 115, and an emitter electrode E formed of the AL electrode 6 is formed on the I emitter region 4. It is.

Next, the steps of the method of the present invention will be explained in detail with reference to FIG. First, a buried II(n'') 11 is formed on the P-type 3i substrate 10, and an n-type 3411I in the collector region is grown one bit laterally (FIG. 2(A)).
This is done in order to obtain a low saturation resistance and saturation voltage by lowering the series resistance of the collector.

Then, the n-type Si WJl is oxidized to form an insulating layer 5 of a silicon oxide film (Si 02 ), and a P-type base region 2 is formed by diffusion through photolithography (FIG. 2(B)). Subsequently, after resist patterning, the insulating ff15 is etched using the photomask 12 to form an emitter region, and an intrinsic semiconductor layer 3 of carbon (C) or the like is formed on the exposed base region 2. This intrinsic semiconductor layer 3 is formed by CVD (chemical vapor deposition)
The number of individuals is grown from several dozen to several hundred by the method (Figure 2 (C)).

Here, with the CVD method, growth stops after a certain amount of growth! It has IIJWJ properties and is used when growing with controlled thickness.

Then, n-type Si is formed on the intrinsic semiconductor Tl 33 and the insulating layer 5.
After forming a C layer (4) and patterning the resist using a photomask 13, the SiC other than the emitter region is removed by etching, and the doped n
A type Si0 layer 4 is formed (FIG. 2(D)).

Subsequently, contact holes are formed in the base and collector regions on the insulating WJ 5, and aluminum (Ai) ffi poles 6 are formed in the respective regions of the base B, emitter E, and collector C using a photomask 14 ( Figure 2 (E)).

Next, FIG. 3 shows a structural sectional view when the method of the present invention is applied to the method of SS (2) described above. In Figure 3, PL
! A buried layer 11 is embedded in the Sii plate 10, and an n-type collector region 5i11 is formed thereon. ,
In the n-type Si 11111, a P-type base region 2 is formed by diffusion. The external base region 2a of this base region 2 is connected to the base electrode via the P1-doped 3i layer 15. The internal base region 2b is made of two layers of Si oxide.
The skins 16a and 16b are selectively removed by etching or the like, and an intrinsic semiconductor layer 3 made of carbon or the like is formed on these parts by CVD. Then, an I-mitter W is placed on the negative semiconductor layer 3.
A 4-area n-type Si0 layer 4 is formed, and aluminum (Ai
) By forming the electrode 6, a T-mitter E is formed.

In this way, the intrinsic semiconductor layer 3 serves as a barrier layer, and impurities from the base region 2 are not mixed in when forming the T-mitter i region (n-type Si0 layer 4). Therefore, since the base concentration can be increased, the base resistance can be lowered, and the operating speed can be made extremely high. Furthermore, the semiconductor material (Si) of the emitter region 4 is
Since C) has a larger energy gap than the semiconductor material (Si 2 ) of the base region 2, it is possible to improve the amplification factor.

Furthermore, when compared with, for example, the conventional 88, the influence of the interface state generated at the F10 junction interface is reduced, and the cut-off frequency and current gain are increased. Conductor devices can be manufactured.

(Effects of the Invention) As described above, according to the present invention, by forming a predetermined intrinsic upper conductor layer between the base region and the emitter region,
Since the electronic structure of the emitter region can be easily imagined, the operating speed can be made extremely high, and the amplification factor can be improved.

[Brief explanation of drawings]

Figure 1 is a structural cross-sectional view of an embodiment of the method of the present invention, Figure 2 is a cross-sectional process diagram of the method of the present invention, Figure 3 is a cross-sectional view of the structure when the method of the present invention is applied to SST, Figure 4 is a structural cross-sectional view of a conventional transmissive type semiconductor device. In the figure, 1 is an n-type 3i layer (rector region), 2 is a base region, 3 is a benign semiconductor layer, 4 is an n-type Si CXi (emitter region), and 6 is an Ai electrode. Figure P-type Si □10 Motoyaku Rikatamoto tSST t': Reputation W4u 對 wo kaichi noodle cutting distribution Figure 3 ← ← 13 Figure 2 (A) Figure 4

Claims (1)

[Claims] A step of forming a base region on a substrate via a collector region, a step of forming an intrinsic semiconductor layer of a predetermined thickness on the base region, and a step of forming the base region on the intrinsic semiconductor layer. forming an emitter region made of a semiconductor material having an energy gap equal to or larger than that of a semiconductor material;