JPH0222826A - Bipolar type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent an N<--> type region or a P<--> type local region from being formed inside an epitaxial layer when an N<-> type epitaxial layer is grown by a method wherein an N<+> type buried region whose concentration is double or higher a surface concentration of a P-type semiconductor substrate and a P-type buried layer is piled up locally on an N-type buried layer. CONSTITUTION:An N-type buried region 2 and P-type buried regions 3 are formed on a P-type semiconductor substrate 1; after that, an N<+> type buried region 4 is formed locally in one part of the N-type buried region 2. During this process, a concentration of the N<+> type buried region 4 is made double or higher a surface concentration of the P-type semiconductor substrate 1 and the P-type buried regions 3. When this N<+> type buried region 4 is provided, a compensation of an impurity is relaxed when an N<-> epitaxial layer 5 is formed; it is possible to prevent that its one part becomes an N<--> type region or a P<--> type region locally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a high voltage semiconductor bipolar integrated circuit device.

[Conventional technology]

Conventionally, this type of high-voltage bipolar semiconductor integrated circuit device has an N-type buried layer on a P-type semiconductor substrate and a P-wall buried layer for insulating between elements, and an N-type epitaxial layer is formed on the entire surface of this layer. Afterwards, a P-type insulating region is completed, and bipolar transistors, resistors, etc. are formed in this region.

[Problem to be solved by the invention]

However, in the conventional bipolar semiconductor integrated circuit device having such a structure as described above, when an N-type epitaxial layer is formed on the N-type buried layer on the P-type semiconductor substrate and the P-wall buried layer, Since the P-type impurity diffuses out from the wall buried layer into the N'' type epitaxial layer, the impurity in the epitaxial layer is compensated, and a part of the N-type epitaxial layer becomes P-type.
- type or may become N- type. For this reason, the saturation resistance of NPN transistors etc. formed later increases, causing a problem that normal operation as an integrated circuit cannot be achieved.

In view of the above problems, an object of the present invention is to provide a unique bipolar semiconductor integrated circuit device that causes local P-type inversion or N-type change in an N-type epitaxial layer on a P-type semiconductor substrate. That's true.

[Means to solve the problem]

According to the present invention, the bipolar semiconductor integrated circuit device includes:
A P-type semiconductor substrate and an N semiconductor substrate selectively formed on the substrate.
2 for the P+ type buried layer of the type buried region and the insulating region, and the P+ type buried region of the P type semiconductor substrate and the insulating region, which is selectively formed in a part of the N type buried region.
and an N+ type buried layer having a concentration more than twice as high.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a partial sectional view of a high voltage bipolar semiconductor integrated circuit device showing an embodiment of the present invention. This integrated circuit device is manufactured as follows. That is, first, a P-type semiconductor substrate 1 (concentration 1×1015 to 5×1016/cn
i) N-type buried region 2 (surface concentration 5 x 101
After forming the P-wall buried region 3 (surface concentration 5×1016 to 2×1018/cut) and the N+ type buried region 4 (surface concentration I×1017) in a part of the N-type buried region 2. ~1×1019/C:rd) is formed locally. At this time, it is necessary to make the concentration of the N+ type buried region 4 twice or more than the surface concentration of the P type semiconductor substrate 1 and the P wall buried region 3 as in this embodiment. By providing this N1 buried region 4, impurity compensation when the N-epitaxial layer 5 is formed is relaxed, and a part of it is locally formed into an N-type region or a P-type region.
- Avoiding mold areas.

Therefore, after that, the N-type epitaxial layer 5 (concentration 8
10'4/co? >, forming a P+ type insulating region 7,
By sequentially forming a P-type base region 8, an N+-type collector region 9, and an N1-type emitter region 10 using a conventional technique, and providing base, collector, and emitter electrodes 11, 12, and 13, a high breakdown voltage bipolar type integrated circuit can be obtained. The circuit device is completed.

FIG. 2 is a partial sectional view of a high voltage bipolar semiconductor integrated circuit device showing another embodiment of the present invention. According to this embodiment, two N+ type buried regions 4a, 4b are provided on the N type buried region 2.

At this time, one of the buried regions 4a may be formed so as to partially protrude from the N-type buried region 2.

〔Effect of the invention〕

As described in detail above, according to the present invention, the N4 type buried region is locally superimposed on the N type buried layer and has a higher concentration of 2@ or more than the surface concentration of the P type semiconductor substrate and the P wall buried layer. This prevents the formation of N-type regions and P-type local regions in the epitaxial layer when growing an N'"-type epitaxial layer. It can have a significant effect on improving performance.

FIG. 3 is a cross-sectional view of a high voltage bipolar semiconductor integrated circuit device showing another embodiment of the invention.

DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type buried layer, 3...
... P wall buried layer, 4.4a, 4b... N+ type buried layer, 5... N- type epitaxial layer, 6... Insulating film, 7... P+ type insulating region, 8... P-type base region,
9... N'' type collector region, 10... N+ type emitter region, 11... Base electrode, 12... Collector electrode, 13... Emitter electrode.

Claims (1)

[Claims] A P-type semiconductor substrate and an N semiconductor substrate selectively formed on the substrate.
a P^+ type buried region in a type buried region and an insulating region;
The P is selectively formed in a part of the N-type buried region.
1. A bipolar semiconductor integrated circuit device comprising: a semiconductor substrate; and an N^+ type buried layer having a concentration twice or more higher than that of a P^+ type buried region of an insulating region.