JPS58135671A - Insulation and isolation type bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce the base resistance and the parasitic capacity by a method wherein the side surface of an emitter is coated with an insulator, and an external base is formed by isolation from the emitter so as to reach from under the insulator to immediately under the emitter end part. CONSTITUTION:The side surface of an emitter region 111 is coated with insulation and isolation regions 108 and 114, and the capacity between the emitter and the base is very small and greatly contributed to the high speed property. The graft base region 107 is positioned immediately under the insulation and isolation region 108, and arranged at the position very close to the emitter region 111 from a planar view and slightly away therefrom in a vertical direction. Thereby, it has a structure wherein the base resistance is sufficiently low, thus the generation of leak currents, burst noises and the deterioration of withstand voltages generated by the contact of the emitter and the graft base is prevented, and the element areas are small.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an isolation type bipolar transistor, and more particularly to an isolation type bipolar transistor having high density and high frequency characteristics.

Conventional configurations and their problems Although isolation type bipolar transistors are superior in high speed compared to MO8 type semiconductor devices, they have drawbacks in terms of integration and low power consumption, and it is important to overcome these drawbacks. It was a proposition.

In the early days of MO3-type semiconductor devices, MO8 devices utilized the inversion layer, or channel, of the substrate, so there was no need for isolation between devices, and as is evident in devices with silicon gate or molybdenum gate structures. Secondly, since the source and drain can be formed using the gate as a mask, there is a great advantage that the drain, source and channel can be formed in a self-aligned manner.

However, as the degree of integration of MO8 type semiconductor devices increases, it becomes necessary to separate the elements, that is, to separate the drain and source of one element from the drain and source of another element. Densification has become a major problem.

On the other hand, in the early days of bipolar semiconductor devices, the epitaxial layer for forming elements was extremely thick, about 10 μm, and the area of the isolation region required for isolation was also extremely large.

However, in recent years, insulation isolation technology has advanced, and epitaxial layers have become thinner, around 2 μm.
Since it is no longer necessary to take as much space during isolation and the base region, collector region, etc. can be formed so as to be in contact with the isolation region, the isolation is significantly improved compared to MO8 type semiconductor devices. The difference is starting to disappear. However, bipolar semiconductor devices have a base and an emitter like MO8 type semiconductor devices.

The lack of a sophisticated means to fabricate collectors in a self-aligned manner has slowed downscaling.

In addition, in bipolar semiconductor devices, it is necessary to form a graft base (high concentration base) region in order to lower the base resistance, and there is a difference in impurity concentration between the craft base region and the base region. Contacting them causes disadvantages such as poor withstand voltage, noise, and leakage current.

In this way, in bipolar semiconductor devices, MO8
Compared to the three regions (drain, channel, and source) of the device, having four regions (emitter, collector, base, and craft base) increases the area.

These will be explained below with reference to the drawings.

Figure 1 shows OXIM (Oxide l5olated M
This is an isolated bipolar semiconductor device called onolithic. In the figure, 11 is a p-type semiconductor substrate, 12 is an n+ buried region, 13 is an n+ region and is a collector contact region, 14 is an n collector region, and 1
6 is a p+ graft base region, 16 is a p active base region, 17 is an n+ emitter region, and 18a.

18b, 18c insulation isolation region, 19M, 19b.

19c are base, emitter, and collector electrodes, respectively. In this example, isolation region 18b is formed at the same time as isolation regions 18a and 18c for isolation between elements. Therefore, although the isolation region 18b isolates the collector region 14 and the emitter region 17 by a small distance, there is a drawback that the insulation isolation region 18b becomes deeper and becomes wider during isolation.
1 □ Also, in this structure, the graft base region 16 is provided to lower the base resistance, and the characteristics are improved, but the graft base region 16 is a p+ region and the emitter region 17 is an n+ region. Since they are in contact with each other, basic defects such as leakage current generation, noise generation, and deterioration of withstand voltage occur.

To prevent this, it is necessary to separate the graft base region 16 and emitter region 17. For this purpose, an additional photolithography process is required, and errors in mask alignment must be taken into consideration, making enlargement of the element unavoidable.

FIG. 2 shows a bipolar semiconductor device with this improvement.

In this figure, the same numbers as in FIG. 1 indicate the same parts, 20 is polycrystalline silicon, and 21 is an oxide film. This element has a structure in which the graft base region 16 and the emitter region 17 are separated, and the defects of the structure shown in FIG. 1 have been removed. In addition, in heavy equipment 1, when a metal electrode is attached directly on the graft base region jJ]tt15,
In order to prevent the dimensions from increasing due to the margin of the mask when forming the contact hole, when forming the graft base region 15, diffusion is performed using polycrystalline silicon 20, and this polycrystalline silicon 20 is stretched as it is as an electrode. , the base metal electrode 19a is connected on the insulation isolation region 18a.

Does this device have many improvements over the device shown in Figure 1?
There are three drawbacks: That is, the first drawback is that the active base region 16 is located between the graft base region 16 and the emitter region 17, which increases the base resistance, and the second drawback is that the polycrystalline silicon 720 is extracted as an electrode. , the resistance is higher than that in which a metal electrode is placed on the graft base region 16. That is, the resistance of polycrystalline silicon is several orders of magnitude higher than that of a metal film resistor, and an increase in base resistance becomes a problem, especially when higher integration rates progress and the capacitance and resistance of elements become smaller. The third drawback is that the isolation region 18b is deep, which is the same as the drawback of the OXIM structure in FIG.

As another example of higher density, an example of a triple diffusion type bipolar type semiconductor device is shown in Fig. M3. In this figure, the same numbers as in FIGS. 1 and 2 indicate the same parts.

FIG. 3 shows an active base region 16, an emitter region 17,
The positional relationship of the graft base region 16 is the same as in FIG. 2, and has the advantages mentioned above.

Furthermore, this structure has the advantage that the base metal electrode 19δ is disposed directly above the polycrystalline silicon 20 on the graft paste 16, so that the base resistance of the electrode extraction basin is small.

However, this element also has the following three drawbacks. Points 1 and 2 are the same drawbacks as those mentioned in FIG. The second reason is that the insulation isolation region 18b has the same depth as the isolation regions 18a and 18c for isolation between elements, so the insulation isolation region 18b inevitably becomes wider, and an increase in the element area is unavoidable. That's true. The third problem is that a buried layer as an n+ (high concentration n-type) region necessary for lowering the collector resistance is not included, which is a common drawback of triple diffusion type elements.

As described above, all of the currently published bipolar semiconductor devices have a few drawbacks.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide an isolated bipolar transistor with higher density and improved high frequency characteristics.

Structure of the Invention The present invention realizes reduction in paste resistance and parasitic capacitance by coating the side surface of the emitter with an insulating material and forming an external base separated from the emitter so as to extend from under the insulating material to just below the end of the emitter. It is an isolation type bipolar transistor.

Description of examples The present invention will be explained below with reference to the drawings.

FIG. 4 shows a structural cross-sectional view of an embodiment of an isolation type bipolar transistor according to the present invention. In the figure, 101 is a p-type substrate with an n+ type buried region 1 on the top surface.
02 is formed by diffusion and serves to lower the collector resistance. 103 is an insulator isolation region for isolation between elements;
04 is a p+ type channel stopper for preventing inversion.

106 is an n-type epitaxial layer, usually 0.5 to 6Ω
A layer with a resistance value of 2 to 5 μm is formed and serves as a collector.

106 is the base region and the p-type impurity concentration is 1×1017/
The value is around c111. 107 is the graft base area necessary to lower pace resistance.

It is formed directly under the inter-emitter isolation region 108.

109 is a graft base region under the base contact. 11Q is an n+ diffusion layer for lowering the contact resistance of the collector region 105, and is formed and diffused simultaneously with the formation and diffusion of the emitter region 111. 112a, 112b, 1
12c serves to prevent alloy bits of the polycrystalline silicon layer te, base, emitter, collector (7) Alt poles 113a, 113b, and also serves to prevent alloy bits of the polycrystalline silicon layer 112b, 11
2G serve as diffusion sources for the emitter region 111 and collector contact region 110, respectively. 114 is an insulating isolation region between the emitter region 111 and the collector region 106.

In this device, the side surfaces of the emitter region 111 are covered with insulating isolation regions 108 and 114, and the emitter and
The capacitance between bases is extremely small, which greatly contributes to high speed. Furthermore, the graft base region 107 is located directly under the insulation isolation region 108, and the emitter region 1
It is located very close to 11 in plan view and slightly away from it in the vertical direction of the paper. Therefore, the pace resistance is sufficiently low, and leakage current and burst noise caused by contact between the emitter and the graft base are reduced.
The structure prevents breakdown voltage deterioration and has a small element area. Regarding burst noise, in the example shown in FIG. 1 where the graft base and emitter are in contact, burst noise occurs more than 10Q times in one minute of measurement, but in the bipolar semiconductor device according to the present invention, the graft base and emitter are in contact with each other. Since they are formed apart in the vertical direction of the paper, the
- It can be set to a small distance of about 2 to 0.3 μm. Therefore, at this distance, the number of times is about 0 to 1 per 3 minutes, which is a very noticeable difference from the conventional example shown in FIG. Also, an emitter region 111 and a collector region 105
The insulation isolation region 114 that separates the element isolation region 1
Compared to 03, the depth of the insulator is shallower, so the width of the insulation isolation region 114 can be made very narrow, which is an ideal structure for high density.

Furthermore, since the electrode extraction positions of the emitter, collector, and base are predetermined using the polycrystalline silicon 112, the positions can be determined without the need for a new hole-opening process for contact, and the emitter region 111
．． The entire periphery of the collector region 106° and the base region 109 is covered with an oxide film, and only the polycrystalline silicon region necessary for taking out the electrode is exposed on the surface as a conductor.
The structure is such that a certain amount of mask alignment error can be tolerated without considering mask alignment error.

Next, a method for manufacturing an isolation type bipolar transistor according to the present invention will be described.

FIG. 6 shows a cross-sectional view of the process, and the process will be explained below in order.

^ On a p-type semiconductor substrate 121, an island region 122 for forming an isolated transistor, an isolation region 123, and an n+
A buried layer 124 is formed. The island region 122 has a specific resistance of 0.6
This is an n-type single crystal layer of ~2Ω even, and Si3N4124' for selective oxidation is formed on this island region 122. This structure can be easily constructed using conventional selective oxidation techniques.

(I3) Region 126 separating collector and base
After removing the 5t3N4124 above, the remaining Si3N
Selective oxidation is performed using 4124 as a mask to form an oxide film that separates the base and collector (hereinafter referred to as BC isolation film) 1
Form 26. This B.

The depth of the C isolation film 126 is formed to be shallower than the isolation oxide film 123, thereby reducing the spread of the oxide film in the lateral direction. Also, before selective oxidation, island region 1 of BC isolation region 125 is
22 may be etched.

(A resist film 128 is formed as an ion implantation blocking film on the collector region 127 formed by the qBC separation film 126 and the separation film region 123 using a normal photoetching technique. This resist film 128, the BC separation film 126, and the isolation Boron is implanted into the island region 122 by ion implantation using the region 123 as a mask.The active base layer 129 is formed by this ion implantation.The implantation conditions at this time are
KeV, 0.5~3X 10103ato/(1
4, the impurity distribution is 0.4 from the surface of the island region 122.
Located between 2 and 0.3 μm. In this way, the implantation dose is
By reducing the amount, defects induced in St by ion implantation can be reduced, which is effective in reducing collector-emitter leakage current and increasing transistor yield.

q After removing the resist film 128, polycrystalline Si is deposited on the entire surface.
A film 130 and a Si3N4 film 131 are deposited. A resist film 134 is used to form windows in a region 132 separating the base and emitter and a region 133 separating the base and collector.

(Resist film 13 with slope opening windows 132 and 133
4 as a mask, 513N4131, polycrystalline 81 layer 1
22 is preferably etched until at least the side surface of the region that will become the emitter is exposed. In other words, it is preferable to perform etching so as to reach the active base layer 129. After that, the resist film 134 is removed.

CF) Selective oxidation is performed using the Si3N4 film 131 as a mask. As a result, an oxide film 137 (hereinafter referred to as an EB isolation film) is formed that separates the region 136 where the emitter is to be formed and the region 136 where the base contact is to be formed. This E
Due to the B isolation film, the side surfaces of the region 136 forming the emitter are covered with an insulator.

0 After that, after removing the Si3N4 film 131, a resist film 138 is formed over the region 136 where the base contact is to be formed.
Using this as a mask, approximately Polysi layer 13 is coated with
By ion-implanting As into the vicinity of the 00 surface and subjecting it to heat treatment, a Siemi contact 139 and a collector contact 140 are formed.

At this time, the side surfaces of the emitter 139 are the BC separation film 126 and the EB
It is surrounded by a separation membrane 137.

(b) After removing the resist film 138, the collector contact region 140 is covered with at least a resist film 141, and high concentration boron ions are implanted using this as a mask. As a result, a highly concentrated graft base 142 is formed and has a self-line structure with respect to the emitter 139. At this time, since the polycrystalline layer 130 exists on the emitter 139, the influence on the active base 129 directly under the emitter 139 can be reduced by selecting an appropriate value for the ion implantation energy.

Although boron is implanted into the emitter 139, there is no problem since the emitter 139 has a high concentration. Since the graft base 142 formed in this manner is formed up to the periphery of the emitter 139, it is possible to lower the base resistance. Further, since high concentration boron ions are implanted after oxidizing the peripheral portion that will become the emitter 139, boron is not implanted directly under the BC isolation film 126 in contact with the emitter 139. For example, EB in contact with emitter 139
When the separation film 137 is formed to have a thickness of 0.2 to 0.4 μm, the emitter 139 and the high concentration graft base 142 can be separated from each other without coming into contact with each other during implantation.

Furthermore, since this high-concentration boron ion implantation is performed after the emitter 139 and the active base 129 are formed, there is no need for a high-temperature heat treatment step after this step, and the impurity profile can proceed to the final step with almost no change from that after implantation. be able to. In particular, it is possible to prevent the highly concentrated layer from entering directly under the emitter 139. Therefore, burst noise, leakage between the collector and emitter, etc. can be sufficiently reduced without lowering the breakdown voltage between the emitter 139 and the active base 129.

(I) Al wiring is applied to each contact region, and a base electrode 143. An emitter electrode 144 and a collector electrode 145 are formed. Since each electrode structure has an Al wiring-polycrystalline Si layer-monocrystalline Si layer structure, even if sintering is performed, breakdown of the bond due to penetration of Al can be prevented.

In the above-described method of manufacturing a transistor, the active base layer may be formed by performing active base ion implantation immediately before graft base implantation on the process table in FIG. It goes without saying that this process can also produce the same effect.

Effects of the Invention As described above, in the present invention, the emitter and the external base are separated in the vertical direction without being in contact with each other, and the external base extends from under the insulator to just below the end of the emitter, so that the emitter and the external base are not in contact with each other. Therefore, the withstand voltage between the emitter and base is high, and the external base and emitter are vertically separated and close to each other, so the base resistance is low, and the emitter and external base overlap planarly, reducing the area. Furthermore, since the emitter side surface is covered with an insulating material and the emitter is in contact with only the low concentration active base at its bottom surface, the base-emitter capacitance is reduced. Therefore, according to the present invention, it is possible to realize a high-performance bipolar semiconductor integrated circuit having extremely good high frequency characteristics, excellent voltage resistance, and a high density of bipolar transistors.

[Brief explanation of drawings]

FIG. 103.123... Inter-element isolation insulating film, 1 Akira. 129 """Active base area, 107,142-Fist・
...Shima graft base area, 1o8+ 137・■
...Emitter-base isolation insulating film, 111゜139 """ Emitter region, 141, 126----
...Collector-base isolation insulating film. Name of agent: Patent attorney Toshio Nakao and one other person
l Figure w42 Figure 13 Figure 4 sat

Claims (1)

[Claims] an emitter region whose side surfaces are covered with an insulator; an active base region formed directly below the emitter region; and an emitter region connected to the active base region and extending from below the insulator to immediately below an end of the emitter region. 1. An isolated bipolar transistor characterized in that it has a separate external base region and a separate external base region.