JPS59175766A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59175766A JPS59175766A JP5122683A JP5122683A JPS59175766A JP S59175766 A JPS59175766 A JP S59175766A JP 5122683 A JP5122683 A JP 5122683A JP 5122683 A JP5122683 A JP 5122683A JP S59175766 A JPS59175766 A JP S59175766A
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- base region
- base
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 abstract 9
- 239000002344 surface layer Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 74
- 239000013078 crystal Substances 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 244000061508 Eriobotrya japonica Species 0.000 description 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置とその製造方法に関し、特許バイポ
ーラ・トランジスタを含む半導体装置とその製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a patented bipolar transistor and a method of manufacturing the same.
一般に、高速、高周波バイポーラ・トランジスタではエ
ミツタ窓の大きさとエミッタ・ベース電極間を小さくす
ると同時に拡散層深さも浅くする必要がある。Generally, in high-speed, high-frequency bipolar transistors, it is necessary to reduce the size of the emitter window and the distance between the emitter and base electrodes, as well as to reduce the depth of the diffusion layer.
第１図は従来のバイポーラ・トランジスタの一例の断面
図である。FIG. 1 is a cross-sectional view of an example of a conventional bipolar transistor.
第１図において、１１は半導体基板上に形成されたＮコ
レクタ領域、１２は分離用の酸化膜、１３はＰ＋のグラ
フトベース領域、１４はＰ活性ベース領域、１５はＮ“
エミッタ領域、１６は多結晶シリ＝＋ｙのベース電極、
１７は多結晶シリコンのエミッタ電極、１８はベース・
エミッタ電極絶縁分離用の酸化膜である。In FIG. 1, 11 is an N collector region formed on a semiconductor substrate, 12 is an oxide film for isolation, 13 is a P+ graft base region, 14 is a P active base region, and 15 is an N"
Emitter region, 16 is polycrystalline silicon = +y base electrode,
17 is a polycrystalline silicon emitter electrode, 18 is a base electrode.
This is an oxide film for insulating and separating emitter electrodes.
このトランジスタでは、グラフトベース領域１３を形成
することによってベース抵抗の低減がなされており、ベ
ース電極１６、エミッタ電極１７に多結晶シリコンを使
用することにょシ、浅い拡散層の形成が実現はれている
。又、エミッタ電極に第２の多結晶シリコンを使用し、
ベース電極との絶縁分離に多結晶ンリコン膜１６の酸化
膜１８で絶縁分離している為にエミッタ・ベース電極間
が小さくなっている。In this transistor, the base resistance is reduced by forming the graft base region 13, and by using polycrystalline silicon for the base electrode 16 and emitter electrode 17, a shallow diffusion layer can be formed. There is. In addition, a second polycrystalline silicon is used for the emitter electrode,
Since the base electrode is insulated and separated by the oxide film 18 of the polycrystalline silicon film 16, the distance between the emitter and the base electrode is small.
しかしながら、酸化膜１８が単結晶と接する箇所１９で
は、単結晶を酸化することで形成しており、ベース領域
１４の不純物濃度の低下や結晶欠陥の発生原因となって
いる。又、グラフトベース領域１３と炉のエミッタ領域
１５の接触による耐圧低下を防止する為に、グラフトベ
ース・エミッタ間の寸法ρ忙余裕を持たなければならな
い。又、グラフ、トベース領域１３とエミッタ領域１５
は目合せによる余裕も持たなければならないのでベース
抵抗の増加の原因となっているという欠点がある。However, the portion 19 where the oxide film 18 contacts the single crystal is formed by oxidizing the single crystal, which causes a decrease in the impurity concentration of the base region 14 and the occurrence of crystal defects. Further, in order to prevent a drop in breakdown voltage due to contact between the graft base region 13 and the emitter region 15 of the furnace, a dimensional margin ρ must be provided between the graft base and the emitter. In addition, the graph shows the base region 13 and emitter region 15.
This has the disadvantage of causing an increase in base resistance since it is necessary to have a margin for alignment.
本発明は上記欠点を除去し、エミッタ領域とグラフトベ
ース領域とを自己整合で形成することによシベース抵掟
ｐ低下と素子寸法の縮小を計り、高密度で高周波特性の
優れた半導体装置とその製造方法を提供するものである
。The present invention eliminates the above drawbacks, lowers the base resistance p and reduces element dimensions by forming the emitter region and the graft base region in self-alignment, and provides a semiconductor device with high density and excellent high frequency characteristics. A manufacturing method is provided.
本発明の半導体装置は、半導体基板に設けられたコレク
タ領域と、核コレクタ領域に設けられたベース領域と、
該ベース領域に接して設けられたグラフトベース領域と
、該クラフトベース領域に設けられたベース電極と、前
記ベース領域及びあるいはグラフトベース領域上の半導
体基板表面に接しかつ前記ベース電極の表面の一部を櫃
うように設けられた第１の絶縁膜と、該第１の絶縁膜の
直上にかつ前記ベース電極の表面の一部を覆うように設
けられた第２の絶縁膜と、該第２の絶縁膜により前記グ
ラフトベース領域と自己整合されて前記ベース領域内に
設けられたエミッタ領域と、前記第１及び第２の絶縁膜
により前記ベース電極と絶縁されて形成されたエミッタ
電極とを含んで構成される。The semiconductor device of the present invention includes a collector region provided in a semiconductor substrate, a base region provided in the core collector region,
a graft base region provided in contact with the base region; a base electrode provided in the craft base region; and a part of the surface of the base electrode in contact with the semiconductor substrate surface on the base region and/or the graft base region. a first insulating film provided so as to cover the base electrode; a second insulating film provided directly above the first insulating film and covering a part of the surface of the base electrode; an emitter region provided in the base region and self-aligned with the graft base region by an insulating film; and an emitter electrode formed insulated from the base electrode by the first and second insulating films. Consists of.
本発明の半導体装置の製造方法は、半導体基板に絶縁分
離された半導体島状領域を形成する工程と、該島状領域
内にベース領域を形成する工程と、該ベース領域のエミ
ッタ領域を形成すべき領域の表面に第１の絶縁膜を設け
る工程と、該第１の絶縁膜上に多結晶シリコン膜を設け
る工程と、該多結晶シリコン膜の側面を第２の絶縁膜で
覆う工程と、該多結晶シリコン膜をマスクにしてグラフ
トベース領域を形成する工程と、前記多結晶シリコン膜
よシネ細物を導入してエミッタ領域を形成する工程とを
含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the steps of forming an isolated semiconductor island region on a semiconductor substrate, forming a base region within the island region, and forming an emitter region of the base region. a step of providing a first insulating film on the surface of the target region, a step of providing a polycrystalline silicon film on the first insulating film, a step of covering the side surface of the polycrystalline silicon film with a second insulating film, The method includes a step of forming a graft base region using the polycrystalline silicon film as a mask, and a step of introducing a thin film into the polycrystalline silicon film to form an emitter region.
ここで前記第１の絶縁膜はシリコン窒化膜、第２の絶縁
膜はシリコン酸化膜を使用する。Here, the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.
次に、本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described using the drawings.
第２図は本発明の半導体装置の一実施例の断面図である
。FIG. 2 is a sectional view of one embodiment of the semiconductor device of the present invention.
Ｐ型半導体基板２１の上にＮ＋型の埋込領域２２が形成
されコレクタ抵抗を下げる役目をしている。An N+ type buried region 22 is formed on the P type semiconductor substrate 21 and serves to lower the collector resistance.
２５は素子分離の絶縁物分離領域であり、２４はＰのチ
ャネルストッパである。２３はＮ型のエピタキシャル層
で、コレクタ領域となる。３４はコレクタ領域２３のコ
ンタクト抵抗を下げるためのＮ＋領領域ある。３３ｂは
コレクタ電極で、多結晶シリコン膜で作られる。２７は
活性ベース領域でアシ、ベース抵抗を下げる為にＰ＋型
のグラフトベ−ス領域３５が形成されている。３３ａは
ベース電極で多結晶シリコンで作られ、グラフトベース
領域３５の拡散源にもなっている。３９は′炉型のエミ
ッタ領域である。エミッタ電極４０は多結晶シリコンで
作られ、シリコン窒化膜２６及びシリコン酸化膜３０で
ベース電極３３ａと、絶縁分離でれている。25 is an insulator isolation region for element isolation, and 24 is a P channel stopper. Reference numeral 23 denotes an N-type epitaxial layer, which serves as a collector region. Reference numeral 34 denotes an N+ region for lowering the contact resistance of the collector region 23. 33b is a collector electrode made of a polycrystalline silicon film. 27 is an active base region, and a P+ type graft base region 35 is formed in order to lower the base resistance. A base electrode 33a is made of polycrystalline silicon and also serves as a diffusion source for the graft base region 35. 39 is a 'furnace type emitter region. The emitter electrode 40 is made of polycrystalline silicon, and is insulated and separated from the base electrode 33a by a silicon nitride film 26 and a silicon oxide film 30.
この実施例に示すように、本発明では、ベース抵抗の低
減のためのグラフトベース領域３５とエミッタ領域３９
は第１の絶縁膜２６によシ自己整合的に形成式れておυ
、従来のようにグラフトベース領域とエミッタ領域間に
目合せの余裕をとる必要がなく、素子寸法を小きくでき
、ベース抵抗も更に低くなっている。又、ベース電極３
３ａとエミッタ電極４０との絶縁分離は絶縁膜２６．３
０の２層構造となっており、特に絶縁膜２６は耐酸化性
のシリコン窒化膜であり、絶縁膜３ｏの形成時に単結晶
層が酸化６れ−ないゃで、ベース領域２７の不純物濃度
の低下や単結晶層への酸化時の歪や結晶欠陥の発生を防
止することができ特性の向上や歩留９の向上に効果があ
る。As shown in this embodiment, the present invention includes a graft base region 35 and an emitter region 39 for reducing base resistance.
is formed in a self-aligned manner by the first insulating film 26.
Unlike the conventional method, there is no need to provide alignment margin between the graft base region and the emitter region, allowing the device dimensions to be reduced and the base resistance to be further reduced. Also, the base electrode 3
3a and the emitter electrode 40 are separated by an insulating film 26.3.
In particular, the insulating film 26 is an oxidation-resistant silicon nitride film, and the impurity concentration of the base region 27 must be reduced to avoid oxidation of the single crystal layer during the formation of the insulating film 3o. It is possible to prevent the occurrence of distortion and crystal defects during oxidation of the single crystal layer, which is effective in improving characteristics and yield.
次に本発明の半導体装置の製造方法について説明する。Next, a method for manufacturing a semiconductor device according to the present invention will be explained.
第３図（ａｌ〜（ｉ＋は本発明の半導体装置の製造方法
の一実施例を説明するための工程順に示した断面図で必
る。FIG. 3 (al to (i+) are cross-sectional views shown in the order of steps for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention.
甘ず、第３図ｉａｌに示すように、Ｐ型半導体基板２１
の上にＮ＋埋込層２２、絶縁分離されたトランジスタ形
成の為の島領域２３、絶縁分離領域２４、絶縁膜２５ａ
を形成する。島領域２３はＮ型単結晶層であり、その上
面にはコレクタとベース分離の為の絶縁膜２５ｂ及び第
１の絶縁膜として選択酸化用シリコン窒化膜２６が形成
烙れている。この構造は通常の選択酸化技術を用いて容
易に構成することができる。As shown in FIG. 3, the P-type semiconductor substrate 21
On top, there is an N+ buried layer 22, an island region 23 for forming an isolated transistor, an insulation isolation region 24, and an insulation film 25a.
form. The island region 23 is an N-type single crystal layer, and an insulating film 25b for separating the collector and base and a silicon nitride film 26 for selective oxidation as a first insulating film are formed on its upper surface. This structure can be easily constructed using conventional selective oxidation techniques.
次に、第３図ｔｂ＋に示すように、フォトレジストをマ
スクにしてイオン注入法により島領域２３内にＰ型不純
物を導入してベース領域２７を形成する。続いて、全面
に多結晶シリコン膜２８及びシリコン側ヒ膜２９を形成
する。続いて通常のフォトエツチング法により、エミッ
タ電極を形成すべき場所に、多結晶シリコン膜２８．シ
リコン窒化膜２９を選択的に除去して、上面よりシリコ
ン窒化膜２９．多結゛晶シリ・コン膜２８の多層構造パ
ターンを形成する。Next, as shown in FIG. 3tb+, a P-type impurity is introduced into the island region 23 by ion implantation using a photoresist as a mask to form a base region 27. Subsequently, a polycrystalline silicon film 28 and a silicon side filler film 29 are formed on the entire surface. Subsequently, a polycrystalline silicon film 28. The silicon nitride film 29 is selectively removed, and the silicon nitride film 29. A multilayer structure pattern of polycrystalline silicon film 28 is formed.
次に、第３図（Ｃ１に示すように、熱酸化方法により、
多結晶シリコン膜２８の側面に第２の絶縁膜としてシリ
−コン窒化膜３０を形成する。この場合単結晶シリコン
層２３の上面はシリコン窒化膜２６で覆われ、又、多結
晶シリコン膜２８の上面もシリコン窒化膜２９で覆われ
ているので、多結晶シリコン膜２８の側面のみにシリコ
ン酸化膜３０が形成される。Next, as shown in FIG. 3 (C1), by thermal oxidation method,
A silicon nitride film 30 is formed as a second insulating film on the side surface of the polycrystalline silicon film 28. In this case, the upper surface of the single crystal silicon layer 23 is covered with a silicon nitride film 26, and the upper surface of the polycrystalline silicon film 28 is also covered with a silicon nitride film 29, so that only the side surfaces of the polycrystalline silicon film 28 are covered with silicon oxide. A membrane 30 is formed.
次に、第３図（ｄｌに示すように、周囲をシリコン酸化
膜３０及びシリ−コン窒化膜２８で覆われた多結晶シリ
コン膜２７をマスクとしてシリコン窒化膜２６を除去す
ることによりコレクタ電極用窓３１及びベース電極用窓
３２全開孔する。続いて、多結晶シリコン膜３３を被着
する。Next, as shown in FIG. 3 (dl), the silicon nitride film 26 is removed using the polycrystalline silicon film 27 whose periphery is covered with a silicon oxide film 30 and a silicon nitride film 28 as a mask, thereby forming a collector electrode. The window 31 and the base electrode window 32 are completely opened. Then, a polycrystalline silicon film 33 is deposited.
次に、第３図（ｅｌに示すように、フォトエツチング法
により、多結晶シリコン膜３３を選択的に除去してベー
ス電極３３ａ及びコレクタ電極３３ｂ ′ｆｃ形成する
。この時、シリコン窒化膜２９の表面全露出させる。Next, as shown in FIG. 3 (el), the polycrystalline silicon film 33 is selectively removed by photoetching to form a base electrode 33a and a collector electrode 33b'fc.At this time, the silicon nitride film 29 is Expose the entire surface.
次に、第３図（ｆ）に示すように、熱拡散法、又は、イ
オン注入法によりコレクタ電極部の多結晶シリコン膜３
３ｂよｐ単結晶層２３へＮ型不純物を導入してコレクタ
コンタクト領域３４を形成し、ベース電極部の多結晶ン
リコン膜３３ａよりＰ型不細物金導入してグラフトベー
ス領域３５全形成する。Next, as shown in FIG. 3(f), the polycrystalline silicon film 3 of the collector electrode portion is heated by thermal diffusion or ion implantation.
3b, an N-type impurity is introduced into the P single crystal layer 23 to form a collector contact region 34, and a P-type impurity gold is introduced into the polycrystalline silicon film 33a of the base electrode portion to form the entire graft base region 35.
そ乞てベース電極３３ａ コレクタ電極３３ｂの表面
にシリコン酸化膜３６ａ、３６ｂ’ｊ＝形成する。Silicon oxide films 36a and 36b'j are then formed on the surface of the base electrode 33a and collector electrode 33b.
次に、第３図ｆｇｌに示すように、シリコン窒化膜２８
、多結晶ンリコン膜２７全等方向性プラズマエッチ又は
溶液で除去する。続いて、イオンエッチ等の異方向性の
プラズマエッチでシリコン窒化膜２６をシリコン酸化膜
３０の底面には残るように選択的に除去し、エミツタ窓
３７を開孔子る。Next, as shown in FIG. 3fgl, the silicon nitride film 28
Then, the entire polycrystalline silicon film 27 is removed by isodirectional plasma etching or solution. Subsequently, the silicon nitride film 26 is selectively removed by anisotropic plasma etching such as ion etching so as to remain on the bottom surface of the silicon oxide film 30, and an emitter window 37 is opened.
次に、第３図（ｈｌに示すように、多結晶シリコン３８
を全面に形成しフォトエツチング法により多結晶シリコ
ン３８を選択的に除去してエミツタ窓を覆うようにエミ
ッタ電極４０を形成する。続いてエミッタ電極４０ｔ−
通してベース領域２７へＮ型不純・物を導入することに
よってエミッタ領域３９を形成する。このように形成さ
れたエミッタ領域３９はグラフトベース領域３５に対し
て自己整合で、互に接触することなくその間隔を非常に
小さくすることができるのでベース抵抗を小石くするこ
とができる。Next, as shown in FIG. 3 (hl), the polycrystalline silicon 38
is formed over the entire surface, and the polycrystalline silicon 38 is selectively removed by photoetching to form an emitter electrode 40 covering the emitter window. Next, the emitter electrode 40t-
An emitter region 39 is formed by introducing N-type impurities into the base region 27 through the step. The emitter regions 39 formed in this way are self-aligned with the graft base region 35 and can be spaced very small without touching each other, thereby making it possible to reduce the base resistance.
次に、第３図＋ｉ＋に示すように、通常のフォトエツチ
ング法によりシリコン酸化１１３６ａ、３６ｂｉ選択的
に除去して、それぞれベース電極３３ａ、コレクタ電極
３３ｂの表面を露出させる。Next, as shown in FIG. 3+i+, the silicon oxides 1136a and 36bi are selectively removed by a normal photoetching method to expose the surfaces of the base electrode 33a and collector electrode 33b, respectively.
次いで図示しないが通常行なわれる配線形成工程、保護
絶縁膜形成工程を経て半導体装置が作られる。Next, although not shown, a semiconductor device is manufactured through a normally performed wiring formation process and protective insulating film formation process.
以上説明したように１本発明によれば、エミッタ領域に
対してグラフトベース領域が自己整合的に形成されるの
で、従来のようにエミッタ領域に対してマスク合せを行
なってクラフトベース領域を形成するのと異なり、エミ
ッタ領域とグラフトベース領域の間に位置合せの余裕を
考慮する必要がないので、素子面積を縮小することがで
き、高密度化が実現できる。更に、ベース抵抗を下げる
ことができエミッタ領域とクラフトベース間は一定に保
たれるのでベース抵抗がばらつくこともない。又、ベー
ス電極、エミッタ電極間の分離に多層の絶縁膜を使用し
てお９、単結晶層と接する部分には耐酸化性の絶縁膜を
使用しているために、従来のようにエミッタ・ベース電
極間の絶縁膜を形成する際に単結晶層が酸化されるのと
異なり、不純物濃度の低下、結晶欠陥の発生を防ぐこと
ができる。従って、高速、高周波特性の向上、高密度化
、高歩留ｐを実現したバイポーラ型半導体装置及びその
製造方法が得られ、その効果は大きい。As explained above, according to the present invention, the graft base region is formed in a self-aligned manner with respect to the emitter region, so the graft base region is formed by performing mask alignment with the emitter region as in the conventional method. Unlike the above, there is no need to consider alignment margin between the emitter region and the graft base region, so the device area can be reduced and high density can be achieved. Furthermore, since the base resistance can be lowered and the distance between the emitter region and the craft base is kept constant, the base resistance does not vary. In addition, a multilayer insulating film is used to separate the base electrode and emitter electrode9, and an oxidation-resistant insulating film is used in the part in contact with the single crystal layer, so the emitter Unlike the case where a single crystal layer is oxidized when forming an insulating film between base electrodes, a decrease in impurity concentration and generation of crystal defects can be prevented. Therefore, it is possible to obtain a bipolar semiconductor device and a method for manufacturing the same that realize high speed, improved high frequency characteristics, high density, and high yield p, and the effects thereof are significant.
第１図は従来のバイポーラ・トランジスタの一例の断面
図、第２図は本発明の半導体装置の一実施例の断面図、
第３図（ａｌ〜＋ｉ＋は本発明の半導体装置の製造方法
の一実施例を説明するための工程順に示した断面図であ
る。１１・・・・・・半導体基板、１２・・・・・・酸
化膜、１３・・・・・・グラフトベース領域、１４・・
・・・・ペース領域、１５・・・・・・エミッタ領域、
１６・・・、・・ベース電極、１７・・・・・・エミッ
タ電極、１８・・・・・・酸化膜、２１・・・・・・半
導体基板、２２・・・・・・埋込層、２３・・・・・・
島領域、２４・・・・・・絶縁分離領域、２５゜２５ａ
、２５ｂ・・・・・・絶縁膜、２６・・・・・・第１の
絶縁膜（シリコンｆｆ１（［）、２７・・・・・・ベー
ス領１２８・・・・・・多結晶シリコン膜、２９・・・
・・・シリコン窒化膜、３０・・・・・・第２の絶縁膜
（シリコン酸化膜）、３１・・・・・・コレクタ電極用
窓、３２・・・・・・ベース電極用窓、３３・・・・・
・多結晶シリコン膜、３３ａ・・・・・・ペース電極、
３３ｂ・・・・・・コレクタ電極、３４・・・・・・コ
レクタコンタクト領域、３５・・・・・・グラフトベー
ス領ＭＳ ａｃｔ＆。
３６ｂ・・・・・シリコン酸化膜、３７・・・・・・エ
ミツタ窓、３８・・・・・・多結晶シリコン、３９・・
・・・・エミッタ領域、４０・・・・・・エミッタ電極
。
代理人 弁理士 内 原 晋、、′、’、）４．
％ａ、Ｎ。
享１ゾ
卒２Ｖ
療３拐
２ｊ １ｔ
Ｙ７３杷
（１））FIG. 1 is a cross-sectional view of an example of a conventional bipolar transistor, and FIG. 2 is a cross-sectional view of an example of a semiconductor device of the present invention.
FIG. 3 (al to +i+ are cross-sectional views shown in the order of steps for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention. 11... Semiconductor substrate, 12...・Oxide film, 13... Graft base region, 14...
...Pace area, 15...Emitter area,
16... Base electrode, 17... Emitter electrode, 18... Oxide film, 21... Semiconductor substrate, 22... Buried layer , 23...
Island region, 24... Insulation isolation region, 25° 25a
, 25b...Insulating film, 26...First insulating film (silicon ff1([), 27...Base region 128...Polycrystalline silicon film , 29...
... Silicon nitride film, 30 ... Second insulating film (silicon oxide film), 31 ... Collector electrode window, 32 ... Base electrode window, 33・・・・・・
・Polycrystalline silicon film, 33a...Pace electrode,
33b... Collector electrode, 34... Collector contact region, 35... Graft base region MS act&. 36b... Silicon oxide film, 37... Emitter window, 38... Polycrystalline silicon, 39...
...Emitter region, 40...Emitter electrode. Agent: Susumu Uchihara, patent attorney, 4.
%a,N. Kyo 1 Zo Graduation 2V Treatment 3 Kyo 2j 1t Y73 Loquat (1))
Claims (1)
クタ領域に設けられたベース領域と、該ベース領域に接
して設けられたグラフトベース領域と、該クラフトベー
ス領域に設けられたベース電極と、前記ベース領域及び
あるいはグラフトベース領域上の半導体基板表面に接し
かつ前記ベース電極の表面の一部を覆うように設けられ
た第１の絶縁膜と、該第１の絶縁膜の直上にかつ前記ベ
ース電極の表面の一部を覆うように設けられた第２の絶
縁膜と、該第２の絶縁膜により前記グラフトベース領域
と自己整合されて前記ベース領域内に設けられたエミッ
タ領域と、 ：前記第１及び第２の絶縁膜により前記
ベース電極と絶縁されて形成されたエミッタ電極とを含
むことを特徴とする半導体装置。 （２）半導体基板に絶縁分離され九半導体島状領域を形
成する工程と、該島状領域内にベース領域を形成する：
工程と、該ベース領域のエミ’）夕領域を形成すべき領
域の表面に第１の絶縁膜を設ける工程と、該第１の絶縁
膜上に多結晶シリコン膜を設ける工程と、該多結晶シリ
コン膜の側面を第２の絶縁膜で覆う工程と、該多結晶シ
リコン膜をマスクにしてグラフトベース領域全形成する
工程と、前記多結晶シリコン膜より不純物を導入してエ
ミッタ領域全形成する工程とを含むことを特徴とする半
導体装置の製造方法。 （３）前記第１の絶縁膜がシリコン窒化膜であり、第２
の絶縁膜がシリコン酸化膜でおる特許請求の範囲第（１
）項及び第（２）項記載の半導体装置とその製造方法。[Claims] (Li) A collector region provided on a semiconductor substrate, a base region provided in the collector region, a graft base region provided in contact with the base region, and a graft base region provided in the craft base region. a first insulating film provided in contact with the semiconductor substrate surface on the base region and/or the graft base region and covering a part of the surface of the base electrode; a second insulating film provided directly above and covering a part of the surface of the base electrode; and an emitter provided in the base region and self-aligned with the graft base region by the second insulating film. and: an emitter electrode formed insulated from the base electrode by the first and second insulating films. Forming a region and forming a base region within the island region:
a step of providing a first insulating film on the surface of a region where an emitter region of the base region is to be formed; a step of providing a polycrystalline silicon film on the first insulating film; A step of covering the side surface of the silicon film with a second insulating film, a step of forming the entire graft base region using the polycrystalline silicon film as a mask, and a step of introducing impurities from the polycrystalline silicon film to form the entire emitter region. A method for manufacturing a semiconductor device, comprising: (3) The first insulating film is a silicon nitride film, and the second insulating film is a silicon nitride film.
Claim 1 (1) in which the insulating film is a silicon oxide film
) and (2), and the semiconductor device and its manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5122683A JPS59175766A (en) | 1983-03-26 | 1983-03-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5122683A JPS59175766A (en) | 1983-03-26 | 1983-03-26 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59175766A true JPS59175766A (en) | 1984-10-04 |
Family
ID=12881026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5122683A Pending JPS59175766A (en) | 1983-03-26 | 1983-03-26 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59175766A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61290762A (en) * | 1985-06-19 | 1986-12-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1983
- 1983-03-26 JP JP5122683A patent/JPS59175766A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61290762A (en) * | 1985-06-19 | 1986-12-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0511417B2 (en) * | 1985-06-19 | 1993-02-15 | Matsushita Electric Ind Co Ltd |
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