JPH0464458B2 - - Google Patents
Info
- Publication number
- JPH0464458B2 JPH0464458B2 JP59252319A JP25231984A JPH0464458B2 JP H0464458 B2 JPH0464458 B2 JP H0464458B2 JP 59252319 A JP59252319 A JP 59252319A JP 25231984 A JP25231984 A JP 25231984A JP H0464458 B2 JPH0464458 B2 JP H0464458B2
- Authority
- JP
- Japan
- Prior art keywords
- field plate
- region
- plate electrode
- semiconductor layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 53
- 230000000694 effects Effects 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 8
- 230000007257 malfunction Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はプレーナ型の半導体装置に関し、就
中、その接合耐圧を向上するために用いられるフ
イールドプレート構造の改良に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a planar semiconductor device, and more particularly to an improvement in a field plate structure used to improve the junction breakdown voltage thereof.
プレーナ型の半導体装置は一導電型の半導体層
表面から該半導体層に対して逆導電型の不純物領
域を形成した構造を有し、これにより形成される
接合（プレーナ接合）は必然的に湾曲され且つそ
の接合端部は半導体層の表面に露出されることに
なる。
A planar semiconductor device has a structure in which an impurity region of an opposite conductivity type is formed from the surface of a semiconductor layer of one conductivity type to the semiconductor layer, and the junction (planar junction) formed thereby is inevitably curved. Moreover, the bonding end portion is exposed to the surface of the semiconductor layer.
第２図Ａは上記プレーナ接合の一例を示す断面
図である。同図において、１はＮ型シリコン層で
ある。該Ｎ型シリコン層１の表面からは高濃度の
P+型不純物領域２が形成されると共に、全表面
を覆うシリコン酸化膜３が形成されている。この
プレーナ接合に逆バイアスが印加されると、接合
近傍には図中破線で示す状態で空乏層が広がる。
空乏層はP+型領域２内にも形成されるが、不純
物濃度の高いP+型領域内部での空乏層の幅は極
めて狭いから、図では省略してある。 FIG. 2A is a sectional view showing an example of the planar joint. In the figure, 1 is an N-type silicon layer. From the surface of the N-type silicon layer 1, a high concentration of
A P + type impurity region 2 is formed, and a silicon oxide film 3 covering the entire surface is formed. When a reverse bias is applied to this planar junction, a depletion layer spreads near the junction as shown by the broken line in the figure.
A depletion layer is also formed within the P + type region 2, but the width of the depletion layer inside the P + type region with high impurity concentration is extremely narrow, so it is omitted in the figure.
一般にプレーナ接合にはブレークダウン耐圧が
低いという問題があり、これは主に接合面の湾曲
部に電界が集中することによるものであるが、図
示のように接合表面近傍における空乏層の幅が狭
くなつていることも耐圧低下の原因になつてい
る。即ち、表面近傍でのみ空乏層が狭くなるため
空乏層の湾曲部は更に湾曲が大きくなり、電界集
中が激しくなる。そこで、プレーナ接合における
耐圧向上を図るために、従来からフイールドプレ
ート構造が採用されている。 In general, planar junctions have a problem of low breakdown voltage, which is mainly due to the concentration of the electric field at the curved part of the junction surface, but as shown in the figure, the width of the depletion layer near the junction surface is narrow. The aging also causes a drop in pressure resistance. That is, since the depletion layer becomes narrower only near the surface, the curved portion of the depletion layer becomes even more curved, and the electric field becomes more concentrated. Therefore, in order to improve the withstand voltage in planar bonding, a field plate structure has conventionally been adopted.
第２図Ｂは最も一般的に行なわれているフイー
ルドプレート構造を示しており、図示のように接
合近傍のＮ型シリコン層領域２上に、酸化膜３を
介してアルミニウム等の導電性金属からなるフイ
ールドプレート電極４が形成されている。該フイ
ールドプレート電極４には負の電圧が印加され、
これにより電極下のＮ型シリコン層領域表層から
電子が排斥される結果、図示のように空乏層が形
成される。こうしてフイールドプレート効果によ
り表面の空乏層の形状が補正されるため、プレー
ナ接合の耐圧の向上を図ることが可能となる。 FIG. 2B shows the most commonly used field plate structure. As shown in the figure, a conductive metal such as aluminum is deposited on the N-type silicon layer region 2 near the junction via an oxide film 3. A field plate electrode 4 is formed. A negative voltage is applied to the field plate electrode 4,
As a result, electrons are excluded from the surface layer of the N-type silicon layer region under the electrode, and a depletion layer is formed as shown in the figure. In this way, the shape of the depletion layer on the surface is corrected by the field plate effect, making it possible to improve the withstand voltage of the planar junction.
第３図Ａは従来行なわれている他のフイールド
プレート構造を示す断面図である。この構造で
は、例えば酸素添加された多結晶シリコン層等の
高抵抗導体からなるフイールドプレート電極４′
を用い、且つ該電極４′のＹ端からＸ端に向けて
図示ように微少電流ｉを流すようになつている。
微少電流ｉが流れることによつて電圧降下が生じ
るから、フイールドプレート電極４′にはＹ端か
らＸ端にかけて第３図Ｂに示すような電位勾配が
形成される。このような勾配をもつた電圧が印加
される結果、この場合にフイールドプレート効果
により形成される空乏層は、図中破線で示すよう
に周辺部に向つて滑かに傾斜した形状になる。 FIG. 3A is a sectional view showing another conventional field plate structure. In this structure, a field plate electrode 4' made of a high resistance conductor such as an oxygenated polycrystalline silicon layer is used.
, and a minute current i is caused to flow from the Y end to the X end of the electrode 4' as shown in the figure.
Since a voltage drop occurs due to the flow of the minute current i, a potential gradient as shown in FIG. 3B is formed in the field plate electrode 4' from the Y end to the X end. As a result of applying a voltage with such a gradient, the depletion layer formed by the field plate effect in this case has a shape that slopes smoothly toward the periphery, as shown by the broken line in the figure.
第２図Ｂの構造では空乏層の形状補正はなされ
るものの、フイールドプレート電極４に印加され
る電圧は一定であるため、延長して形成された空
乏層の端部には曲率の大きい湾曲部が発生する。
このため、この新たな湾曲部分に電界集中を生
じ、充分な耐圧向上効果が得られないという問題
があつた。
Although the shape of the depletion layer is corrected in the structure shown in FIG. Occur.
Therefore, there was a problem that electric field concentration occurred in this new curved portion, and a sufficient effect of improving the breakdown voltage could not be obtained.
これに対し、第３図Ａの構造ではフイールドプ
レート効果による空乏層の延びは極めて滑らかで
あるため第２図Ｂの場合のような問題はなく、充
分な耐圧向上効果が得られる。しかし、この場合
にはフイールドプレート電極４′に微少電流ｉを
流さなければならないから、電力損失を生じると
いう問題があつた。また、このような構造をトラ
ンジスタ等の素子に採用した場合、小電流領域で
の動作が困難で、誤動作を生じ易いという問題が
あつた。 On the other hand, in the structure of FIG. 3A, the extension of the depletion layer due to the field plate effect is extremely smooth, so there is no problem as in the case of FIG. 2B, and a sufficient effect of improving breakdown voltage can be obtained. However, in this case, a small current i must be passed through the field plate electrode 4', resulting in a problem of power loss. Further, when such a structure is adopted for an element such as a transistor, there is a problem that operation in a small current region is difficult and malfunction is likely to occur.
本発明は上記事情に鑑みてなされたもので、逆
バイアスされたプレーナ接合の空乏層の形状を滑
らかな理想的な形状に補正して充分な耐圧向上効
果を得ることができ、且つ電流損失や誤動作の発
生をも防止できるフイールドプレート構造を具備
した半導体装置を提供するものである。
The present invention has been made in view of the above circumstances, and it is possible to correct the shape of the depletion layer of a reverse biased planar junction to a smooth ideal shape, thereby obtaining a sufficient effect of improving breakdown voltage, and reducing current loss and The present invention provides a semiconductor device equipped with a field plate structure that can also prevent malfunctions.
本発明による半導体装置は、第一導電型半導体
層と、該第一導電型半導体層の表面から所定の拡
散深さで選択的に形成されて第一導電型半導体層
との間にプレーナ接合を形成している第二導電型
不純物領域と、該第二導電型不純物領域および前
記第一導電型半導体層の表面を覆う絶縁膜と、該
絶縁膜を介して前記第二導電型不純物領域の周縁
からその外側の第一導電型領域に亙る領域上に形
成された半導体層からなるフイールドプレート電
極と、該フイールドプレート電極を構成する半導
体層において前記第二導電型不純物領域の周縁か
らプレーナ接合の外側方向に向けて交互に形成さ
れた複数の第一導電型領域および複数の第二導電
型領域と、該第一導電型領域およびこれよりも内
側の第二導電型領域により前記フイールドプレー
ト電極の全膜厚に亙つて形成される少なくとも二
つ以上の接合とを具備し、前記プレーナ接合に逆
バアスを印加して動作させる際、前記フイールド
プレート電極の両端部間にも前記少なくとも二つ
以上の接合が逆バイアスとなる電圧を印加するよ
うにしたことを特徴とするものである。
A semiconductor device according to the present invention provides a planar junction between a first conductive type semiconductor layer and a first conductive type semiconductor layer that is selectively formed at a predetermined diffusion depth from the surface of the first conductive type semiconductor layer. A formed second conductivity type impurity region, an insulating film covering the surface of the second conductivity type impurity region and the first conductivity type semiconductor layer, and a peripheral edge of the second conductivity type impurity region via the insulating film. A field plate electrode consisting of a semiconductor layer formed on a region extending from the region to the first conductivity type region outside the field plate electrode, and the outside of the planar junction from the periphery of the second conductivity type impurity region in the semiconductor layer constituting the field plate electrode. A plurality of first conductivity type regions and a plurality of second conductivity type regions are formed alternately in the direction, and the entire field plate electrode is and at least two or more junctions formed over the film thickness, and when operating by applying a reverse bias to the planar junction, the at least two or more junctions are also formed between both ends of the field plate electrode. This is characterized in that a voltage is applied that provides a reverse bias.
上記本発明におけるフイールドプレート電極に
は、少なくとも三つのPN接合が存在することに
なりる。しかも、プレーナ接合に逆バイアスが印
加されて半導体装置が動作される際、フイールド
プレート電極における少なくとも二つの接合は逆
バイアスとなり、その近傍には空乏層が形成され
る。この空乏層が形成されている状態のフイール
ドプレート電極は直列に接続された複数のコンデ
ンサと等価であり、空乏層領域にはその幅方向に
電位勾配が形成される。従つてフイールドプレー
ト電極の両端間には、何等電流が流れなくても傾
斜した電位勾配部分が複数形成され、何等電力損
失を伴うことなく第３図Ａの場合に近似したフイ
ールドプレード効果を得ることができる。 The field plate electrode according to the present invention has at least three PN junctions. Furthermore, when a semiconductor device is operated with a reverse bias applied to the planar junction, at least two junctions in the field plate electrode are reverse biased, and a depletion layer is formed in the vicinity thereof. The field plate electrode in which this depletion layer is formed is equivalent to a plurality of capacitors connected in series, and a potential gradient is formed in the depletion layer region in its width direction. Therefore, a plurality of inclined potential gradient parts are formed between both ends of the field plate electrode even if no current flows, and a field plate effect similar to that in the case of FIG. 3A can be obtained without any power loss. I can do it.
以下に本発明を高耐圧バイポーラトランジスタ
に適用した一実施例を説明する。
An embodiment in which the present invention is applied to a high voltage bipolar transistor will be described below.
第１図は本発明の一実施例になる高耐圧バイポ
ーラ型半導体装置を示す断面図である。同図にお
いて、１１はＰ型シリコン基板である。該Ｐ型シ
リコン基板上にはＮ型エピタキシヤルシリコン層
が成長され、両者の間にはN+型埋込層１２が形
成されている。Ｎ型エピタキシヤルシリコン層の
表面からは前記Ｐ型基板に達するP+型分離領域
１３が選択的に形成され、これによつてＮ型コレ
クタ領域１４が周囲から電気的に分離されてい
る。コレクタ領域１４の表層にはＰ型ベース領域
１５が形成され、該ベース領域内にはN+型エミ
ツタ領域１６が形成されている。また、ベース領
域１５にはP+型ベースコンタクト領域１７が形
成され、コレクタ領域にもN+型コレクタコンタ
クト領域１８が形成されている。エピタキシヤル
シリコン層の表面はシリコン酸化膜１９で覆わ
れ、該酸化膜上には多結晶シリコン層からなるフ
イールドプレート電極２０がパターンニングされ
ている。該フイールドプレート電極２０はＰ型ベ
ース領域１５の周縁部上からその外側のＮ型コレ
クタ領域１４上に亙つて形成され、その表面は酸
化膜２１で覆われている。 FIG. 1 is a sectional view showing a high voltage bipolar semiconductor device according to an embodiment of the present invention. In the figure, 11 is a P-type silicon substrate. An N type epitaxial silicon layer is grown on the P type silicon substrate, and an N + type buried layer 12 is formed between the two. A P + -type isolation region 13 is selectively formed from the surface of the N-type epitaxial silicon layer to reach the P- type substrate, thereby electrically separating the N-type collector region 14 from the surroundings. A P type base region 15 is formed in the surface layer of the collector region 14, and an N + type emitter region 16 is formed within the base region. Further, a P + type base contact region 17 is formed in the base region 15, and an N + type collector contact region 18 is also formed in the collector region. The surface of the epitaxial silicon layer is covered with a silicon oxide film 19, and a field plate electrode 20 made of a polycrystalline silicon layer is patterned on the oxide film. The field plate electrode 20 is formed from the peripheral edge of the P-type base region 15 to the N-type collector region 14 outside thereof, and its surface is covered with an oxide film 21.
また、このフイールドプレート電極２０にはそ
の内側端部、即ちＰ型ベース領域側の端部から外
側端部方向に向けて複数のＰ型領域２２…、複数
のＮ型領域２３…が交互に形成されている。これ
らＰ型多結晶シリコン領域２２…およびＮ型多結
晶シリコン領域２３の両者はフイールドプレート
電極２０の全膜厚に亙るPN接合を形成してい
る。シリコン酸化膜１９上にはアルミニウムパタ
ーンからなるエミツタ電極２４、ベース電極２
５、コレクタ電極２６が形成されており、これら
の電極はコンタクトホールを介して夫々エミツタ
領域１６、ベースコンタクト領域１７、コレクタ
コンタクト領域１８に接続されている。更に、エ
ミツタ電極２４はフイールドプレート電極２０に
おける内側端部のＰ型領域２２に接続され、また
コレクタ電極２６はフイールドプレート電極２０
における外側端部のＮ型領域２３に接続されてい
る。 Further, in this field plate electrode 20, a plurality of P-type regions 22, a plurality of N-type regions 23, etc. are formed alternately from the inner end, that is, the end on the P-type base region side, toward the outer end. has been done. Both the P-type polycrystalline silicon regions 22 . . . and the N-type polycrystalline silicon regions 23 form a PN junction that extends over the entire thickness of the field plate electrode 20. On the silicon oxide film 19 are an emitter electrode 24 and a base electrode 2 made of an aluminum pattern.
5. A collector electrode 26 is formed, and these electrodes are connected to the emitter region 16, base contact region 17, and collector contact region 18, respectively, via contact holes. Furthermore, the emitter electrode 24 is connected to the P-type region 22 at the inner end of the field plate electrode 20, and the collector electrode 26 is connected to the P-type region 22 at the inner end of the field plate electrode 20.
It is connected to the N-type region 23 at the outer end of.
上記実施例における作用を説明すれば次の通り
である。 The operation of the above embodiment will be explained as follows.
第１図のバイポーラ型半導体装置を動作させる
際、エミツタ領域１６とベース領域１５の間には
順バイアスが印加され、ベース領域１５とコレク
タ領域１４との間には逆バイアスが印加される。
その結果、第４図Ａに示すようにフイールドプレ
ート電極２０には内側端部ＸのＰ型領域２２が
負、外側端部ＹのＮ型領域２３が正になる電圧が
印加される。従つて、ベース／コレクタ間のPN
接合近傍に空乏層が広がると共に、フイールドプ
レート電極２０のPN接合にも逆バイアスが印加
されて空乏層が広がる。第４図Ａはフイールドプ
レート電極２０に空乏層が広がつた状態を示して
おり、図中交差斜線を付した部分が空乏層を示し
ている。なお、フイールドプレート電極２０の
PN接合のうち、逆バイアスが加わるのは内側の
Ｐ型領域と外側のＮ型領域とで形成される接合Ａ
であつて、内側Ｎ領域と外側Ｐ領域とで形成され
る接合Ｂは順バイアスとなる。従つて、図示のよ
うに接合の一つおきに空乏層が形成される。もち
ろん、順バイアスの接合にも空乏層は存在する
が、そこにおける電位の変化は微少であるため、
ここでは省略する。 When operating the bipolar semiconductor device shown in FIG. 1, a forward bias is applied between the emitter region 16 and the base region 15, and a reverse bias is applied between the base region 15 and the collector region 14.
As a result, as shown in FIG. 4A, a voltage is applied to the field plate electrode 20 such that the P-type region 22 at the inner end X is negative and the N-type region 23 at the outer end Y is positive. Therefore, the PN between base and collector
The depletion layer spreads near the junction, and a reverse bias is also applied to the PN junction of the field plate electrode 20, causing the depletion layer to spread. FIG. 4A shows a state in which a depletion layer has spread in the field plate electrode 20, and the cross-hatched area in the figure shows the depletion layer. Note that the field plate electrode 20
Of the PN junctions, reverse bias is applied to junction A formed between the inner P-type region and the outer N-type region.
The junction B formed by the inner N region and the outer P region is forward biased. Therefore, a depletion layer is formed at every other junction as shown. Of course, a depletion layer exists in a forward-biased junction, but the change in potential there is minute, so
It is omitted here.
このような状態おけるフイールドプレート電極
２０は、空乏層を誘電体層としたコンデンサを直
列に結合したものと等価である。従つて全く電流
が流れない状態でも空乏層領域には電位勾配が形
成され、フイールドプレート電極２０全体では第
４図Ｂに示すよな電位分布が形成される。このよ
うな電位分布をもつた電極２０によるフイールド
プレート効果が加わる結果、コレクタ領域のベー
ス領域１５との接合近傍表面には第５図中に破線
で示す形状の空乏層が形成され、第２図の通常の
フイールドプレート構造に比較して接合耐圧の向
上を図ることができる。また、既述のようにフイ
ールドプレート電極２０に電流を流す必要がない
から、第３図の従来例のように電力損失や微少電
流動作領域での誤動作を生じることがない。この
場合、第３図の改良された従来例に比較すると空
乏層の形状補正効果は若干劣ると思われるが、こ
れは接合の数を増加することでかなりの程度改良
され、それよりも電力損失がないこと及び誤動作
を防止できる効果の方が大きい。しかも、多結晶
シリコン層に形成された接合は単結晶シリコン層
に形成された接合に比較して耐圧が低くならざる
を得ないが、フイールドプレート電極の両端に印
加される電圧を複数の接合部分に分割することで
その欠点を備える利点がある。 The field plate electrode 20 in this state is equivalent to a series connection of capacitors in which the depletion layer is a dielectric layer. Therefore, even in a state where no current flows, a potential gradient is formed in the depletion layer region, and a potential distribution as shown in FIG. 4B is formed across the field plate electrode 20. As a result of the addition of the field plate effect due to the electrode 20 having such a potential distribution, a depletion layer in the shape shown by the broken line in FIG. 5 is formed on the surface of the collector region near the junction with the base region 15, and as shown in FIG. The junction breakdown voltage can be improved compared to the normal field plate structure. Furthermore, since there is no need to flow a current through the field plate electrode 20 as described above, there is no power loss or malfunction in the micro current operation region as in the conventional example shown in FIG. In this case, the shape correction effect of the depletion layer seems to be slightly inferior compared to the improved conventional example shown in Figure 3, but this can be improved to a considerable degree by increasing the number of junctions, and the power loss is This has a greater effect of preventing errors and malfunctions. Furthermore, although a junction formed in a polycrystalline silicon layer inevitably has a lower breakdown voltage than a junction formed in a single-crystal silicon layer, the voltage applied to both ends of the field plate electrode can be applied to multiple junctions. There is an advantage in overcoming this drawback by dividing the data into two parts.
次に、第１図の実施例におけるフイールドプレ
ート電極２０を形成する方法の一例につき、第６
図Ａ〜Ｄを参照して説明する。 Next, regarding an example of the method of forming the field plate electrode 20 in the embodiment of FIG.
This will be explained with reference to Figures A to D.
まず、Ｐ型シリコン基板１１を用いた従来のバ
イポーラプロセスにおける定法に従つて、Ｎ型エ
ピタキシヤル層１４N+型埋込層１２、P+型分離
領域１３を形成した後、エピタキシヤル層表面を
1100℃の上記雰囲気中で60分酸化し、膜厚6000〓
のフイールド酸化膜１９を形成する。続いて
CVD法により膜厚5000〓のＮ型多結晶シリンコ
ン層を堆積し、これをパターンニングしてフイー
ルドプレート電極となるＮ型多結晶シリコンパタ
ーン20′を形成する（第６図Ａ図示）。 First, an N-type epitaxial layer 14, a N + -type buried layer 12, and a P + -type isolation region 13 are formed according to a standard method in a conventional bipolar process using a P-type silicon substrate 11, and then the surface of the epitaxial layer is
Oxidized for 60 minutes in the above atmosphere at 1100℃, resulting in a film thickness of 6000mm.
A field oxide film 19 is formed. continue
A 5000 mm thick N-type polycrystalline silicon layer is deposited by CVD and patterned to form an N-type polycrystalline silicon pattern 20' which will become a field plate electrode (as shown in FIG. 6A).
次に、フオツトエツチングによりベース領域と
なる部分のフイールド酸化膜を選択的にエツチン
グして開孔した後、1100℃でドライ酸化を行なう
ことにより、ベース開孔部および多結晶シリコン
パターン20の表面に膜厚1000〓の薄い酸化膜２１
を形成する（第６図Ｂ図示）。 Next, the field oxide film in the portion that will become the base region is selectively etched by photo etching to form holes, and then dry oxidation is performed at 1100°C to form the base hole and the surface of the polycrystalline silicon pattern 20. A thin oxide film 21 with a film thickness of 1000 mm
(as shown in FIG. 6B).
次に、ベース領域開孔部上およびフイールドプ
レート電極のＰ型領域２２…となる部分上に開孔
部を有するレジストパターン３１を形成し、該レ
ジストパターン３１をマスクとしてボロンのイオ
ン注入を行なことにより、ベース領域予定部およ
びＰ型領域２２…の予定部にホロンをドープする
（第６図Ｃ図示）。 Next, a resist pattern 31 having openings is formed over the openings in the base region and over the portions that will become the P-type regions 22 of the field plate electrode, and using the resist pattern 31 as a mask, boron ions are implanted. As a result, the planned portions of the base region and the planned portions of the P-type regions 22 are doped with holons (as shown in FIG. 6C).
次に、レジストパターン３１を除去し、熱処理
をを行なつて先にイオン注入したボロンの活性化
を行ない、Ｐ型ベース領域２５を形成すると同時
に、フイールドプレート電極２０のＰ型領域２２
…を形成する（第６図Ｄ図示）。 Next, the resist pattern 31 is removed, and heat treatment is performed to activate the previously implanted boron ions to form the P-type base region 25. At the same time, the P-type region 22 of the field plate electrode 20 is
... is formed (as shown in FIG. 6D).
その後は定法に従つてエミツタ拡散およびコレ
クタコンタクト領域１８の形成、ベースコンタク
ト領域１７の形成、更にアルミニウム配線２４，
２５，２６の形成を行なえば第１図の構造を具備
したバイポーラ型半導体装置を得ることができ
る。 After that, according to the conventional method, emitter diffusion and collector contact region 18 are formed, base contact region 17 is formed, aluminum wiring 24,
By forming 25 and 26, a bipolar semiconductor device having the structure shown in FIG. 1 can be obtained.
以上詳述したように、本発明によれば半導体装
置のフイールドプレート電極構造を改良すること
により、逆バイアスされたプレーナ接合の空乏層
の形状を滑らかな理想的な形状に補正して充分な
耐圧向上効果を得ると同時に、電流損失や誤動作
の発生をも防止できる等、顕著な効果が得られる
ものである。
As described in detail above, according to the present invention, by improving the field plate electrode structure of a semiconductor device, the shape of the depletion layer of a reverse biased planar junction is corrected to a smooth ideal shape, and a sufficient breakdown voltage can be achieved. In addition to obtaining improvement effects, remarkable effects such as being able to prevent current loss and malfunctions can be obtained.
第１図は本発明をバイポーラ型半導体装置に適
用した一実施例を示す断面図、第２図Ａはプレー
ナ接合とその耐圧低下の問題を説明する断面図で
あり、同図Ｂは従来の半導体装置におけるフイー
ルドプレート構造を示す断面図、第３図Ａ，Ｂは
従来の改良されたフイールドプレート構造を示す
説明図、第４図Ａ，Ｂは第１図の実施例における
作用を示す説明図、第５図は第１図の実施例にお
いてベース領域１５とコレクタ領域１４の接合近
傍に広がる空乏層の形状を示す断面図、第６図
Ａ，Ｄは第１図の実施例になる半導体装置の要部
製造工程を順を追つて示す断面図である。
１１……Ｐ型シリコン基板、１２……N+型埋
込領域、１３……P+型分離領域、１４……Ｎ型
コレクタ領域、１５……Ｐ型ベース領域、１６…
…N+型エミツタ領域、１７……P+型ベースコン
タクト領域、１８……N+型コレクタコンタクト
領域、１９……フイールド酸化膜、２０……フイ
ールドプレート電極、２０′……Ｎ型多結晶シリ
コンパターン、２１……薄い酸化膜、２２……Ｐ
型領域、２３……Ｎ型領域、３１……レジストパ
ターン。
FIG. 1 is a cross-sectional view showing an embodiment in which the present invention is applied to a bipolar semiconductor device, FIG. 3A and 3B are explanatory diagrams showing a conventional improved field plate structure; FIGS. 4A and B are explanatory diagrams showing the operation of the embodiment of FIG. 1; 5 is a cross-sectional view showing the shape of the depletion layer extending near the junction between the base region 15 and collector region 14 in the embodiment of FIG. 1, and FIGS. 6A and 6D are of the semiconductor device according to the embodiment of FIG. FIG. 3 is a cross-sectional view showing the main manufacturing process in order. DESCRIPTION OF SYMBOLS 11... P type silicon substrate, 12... N + type buried region, 13... P + type isolation region, 14... N type collector region, 15... P type base region, 16...
...N + type emitter region, 17...P + type base contact region, 18...N + type collector contact region, 19...field oxide film, 20...field plate electrode, 20'...N type polycrystalline silicon Pattern, 21...thin oxide film, 22...P
Type area, 23...N type area, 31...Resist pattern.
Claims (1)
層の表面から所定の拡散深さで選択的に形成され
て前記第一導電型半導体層との間にプレーナ接合
を形成している第二導電型不純物領域と、該第二
導電型不純物領域および前記第一導電型半導体層
の表面を覆う絶縁膜と、該絶縁膜を介して前記第
二導電型不純物領域の周縁からその外側の第一導
電型領域に亙る領域上に形成された半導体層から
なるフイールドプレート電極と、該フイールドプ
レート電極を構成する半導体層において前記第二
導電型不純物領域の周縁からプレーナ接合の外側
方向に向けて交互に形成された複数の第一導電型
領域および複数の第二導電型領域と、該第一導電
型領域および第二導電型領域により前記フイール
ドプレート電極の全膜厚に亙つて形成される三つ
以上の接合と、前記プレーナ接合に逆バイアスを
印加して動作させる際、前記フイールドプレート
電極の両端部間にも前記三つ以上の接合のうち少
なくとも二つ以上の接合が逆バイアスとなる電圧
が印加されるコンタクトとを具備したことを特徴
とする半導体装置。 ２ 前記第一導電型半導体層がバイポーラトラン
ジスタのコレクタ領域を構成し、前記第二導電型
不純物領域がバイポーラトランジスタのベース領
域を構成していることを特徴とする特許請求の範
囲第１項記載の半導体装置。 ３ 前記フイールドプレート電極を構成する半導
体層が多結晶シリコン層であることを特徴とする
特許請求の範囲第１項または第２項記載の半導体
装置。[Claims] 1. A planar junction between a first conductive type semiconductor layer and the first conductive type semiconductor layer, which is selectively formed at a predetermined diffusion depth from the surface of the first conductive type semiconductor layer. an insulating film that covers the second conductive type impurity region and the surface of the first conductive type semiconductor layer; A field plate electrode consisting of a semiconductor layer formed on a region extending from the periphery to the first conductivity type region outside the field plate electrode, and a planar junction from the periphery of the second conductivity type impurity region in the semiconductor layer constituting the field plate electrode. A plurality of first conductivity type regions and a plurality of second conductivity type regions are formed alternately toward the outside, and the first conductivity type regions and the second conductivity type regions cover the entire film thickness of the field plate electrode. When operating by applying a reverse bias to the planar junction, at least two of the three or more junctions are formed between both ends of the field plate electrode. 1. A semiconductor device comprising a contact to which a reverse bias voltage is applied. 2. The semiconductor layer according to claim 1, wherein the first conductivity type semiconductor layer constitutes a collector region of a bipolar transistor, and the second conductivity type impurity region constitutes a base region of the bipolar transistor. Semiconductor equipment. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor layer constituting the field plate electrode is a polycrystalline silicon layer.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252319A JPS61129867A (en) | 1984-11-29 | 1984-11-29 | Semiconductor device |
| KR1019850008747A KR890004495B1 (en) | 1984-11-29 | 1985-11-22 | Semiconductor device |
| US06/802,372 US4707720A (en) | 1984-11-29 | 1985-11-27 | Semiconductor memory device |
| DE8585115145T DE3585225D1 (en) | 1984-11-29 | 1985-11-29 | PLANAR SEMICONDUCTOR DEVICE WITH A FIELD PLATE. |
| EP85115145A EP0190423B1 (en) | 1984-11-29 | 1985-11-29 | Planar semiconductor device having a field plate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252319A JPS61129867A (en) | 1984-11-29 | 1984-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61129867A JPS61129867A (en) | 1986-06-17 |
| JPH0464458B2 true JPH0464458B2 (en) | 1992-10-15 |
Family
ID=17235598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59252319A Granted JPS61129867A (en) | 1984-11-29 | 1984-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61129867A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2956434B2 (en) * | 1992-10-30 | 1999-10-04 | 株式会社デンソー | Insulated semiconductor device |
| JP2803565B2 (en) * | 1994-04-15 | 1998-09-24 | 株式会社デンソー | Method for manufacturing semiconductor device |
| CN103681808A (en) * | 2012-09-09 | 2014-03-26 | 苏州英能电子科技有限公司 | LBJT (Lateral Bipolar Junction Transistor) containing field plate structure |
-
1984
- 1984-11-29 JP JP59252319A patent/JPS61129867A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61129867A (en) | 1986-06-17 |
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