JPH07115173A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the variation in the layer resistance of a polycrystalline silicon resistance element by a method wherein the polycrystalline resistance element is formed simultaneously with an active base layer or with an emitter layer. CONSTITUTION:An N-type buried layer 2, an N-type epitaxial layer 3, an insulating diffused layer 4 and a first insulating layer 5 are formed on a P-type silicon substrate 1. After that, the first insulating layer 5 is selectively removed by photoetching to open an active base diffusion window. Then an active base layer 7 containing, for instance, P-type impurities and a first polycrystalline silicon layer 8 are formed simultaneously by an MBE method. With this constitution, the variation in the thickness of the polycrystalline silicon layer and the variation in the impurity concentration can be reduced to about a half of the variation of a conventional constitution and the variation in a polycrystalline silicon resistance can be halved, so that the quality and the yield can be substantially improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a high frequency semiconductor integrated circuit having a shallow junction and a polysilicon resistance.

[0002]

2. Description of the Related Art As semiconductor integrated circuits have higher performance and higher functionality, a polysilicon layer, which is advantageous in improving the degree of integration, is used as a circuit resistance element, and a shallow junction technique for the emitter and active base layers. Has become a problem.

As a conventional technique of this type, for example, in JP-A-4-37143, an active base layer is formed by the MBE method.

3A to 3F are cross-sectional views of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a high frequency semiconductor integrated circuit in which an active base layer is formed by using the MBE method. is there.

First, as shown in FIG. 3A, after the N type buried layer 2 and the N type epitaxial layer 3 are formed on the P type silicon substrate 1, the second insulating layer 17 (1500Å) and the third insulating layer 17 are formed. The insulating layer 18 (1500 Å) is sequentially deposited. Then, the second insulating layer 17 and the third insulating layer 18 are formed by photolithography.
Are selectively and sequentially etched away to open an insulating diffusion window, and P-type impurities are diffused to a high concentration to form a P-type diffusion layer 4 having a depth of 1.2 μm. Next, as shown in FIG. 3B, after thermally oxidizing the third insulating layer 18 as a mask to form the first insulating layer 5 (1.5 μm), the third insulating layer 1 is formed.
8 is entirely removed by etching. Next, the second insulating layer 17
After selectively ion-implanting a large amount of N-type impurities through the vias, a high temperature heat treatment is performed to form the collector diffusion layer 6. Next, as shown in FIG. 3C, after depositing a third polysilicon layer 19 (1000 Å), a large amount of impurities are ion-implanted from the upper surface. Next, heat treatment is performed to activate the ion-implanted impurities, and then the third polysilicon layer 19 is removed by etching by photoetching to form a resistance pattern. Next, after depositing a fourth insulating layer (3000Å) 20, the fourth insulating layer 20 is selectively removed by etching by photoetching. next,
As shown in FIG. 3D, the second insulating layer 17 is selectively etched away by a photo-etching method to open a base diffusion window, and then an active base containing a large amount of P-type impurities is formed by an MBE method. A layer 7 (1000Å) and a first polysilicon layer 8 (1000Å) are formed. Next, a high-concentration base layer 9 is formed by selectively ion-implanting a large amount of P-type impurities by photolithography. Next, as shown in FIG. 3E, after the first polysilicon layer 8 is entirely removed by etching, a fifth insulating layer 21 (2000 Å) is deposited. Next, the fifth insulating layer 21 is selectively etched away by the photoetching method, the emitter diffusion window and the collector diffusion window are opened, and then the second polysilicon layer 11 is deposited. Next, a large amount of N-type impurities are ion-implanted into the second polysilicon layer 11 from the upper surface, and then a high temperature heat treatment is performed to form the emitter layer 12. Next, the second polysilicon layer 11 is selectively removed by etching by photolithography. Next, as shown in FIG. 3F, the fourth insulating layer and the fifth insulating layers 20 and 21 are selectively and sequentially removed by photolithography to open the base contact window and the resistance contact window. After forming the holes, an electrode metal is vapor-deposited to form an emitter electrode 13, a base electrode 14, a collector electrode 15 and a resistance electrode 16.

[0006]

In this conventional method of manufacturing a semiconductor integrated circuit for high frequency, since the active base layer and the polysilicon resistance element are separately formed, the polysilicon layer is formed by a normal vapor phase growth method. After that, a large amount of impurities are ion-implanted from the upper surface to control the layer resistance, but as a result, there is a drawback that the layer resistance greatly varies due to variations in the film thickness and impurity concentration of the polysilicon layer.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit, which reduces variations in layer resistance of polysilicon resistance elements.

[0008]

A method of manufacturing a semiconductor integrated circuit according to the present invention is characterized in that a polysilicon resistance element is formed simultaneously with an active base layer or an emitter layer.

[0009]

According to the present invention, the polysilicon resistance element is formed simultaneously with the active base layer or the emitter layer and the polysili resistance element by using the MBE method which can control the film thickness and the concentration uniformly and with high precision. As a result, the layer resistance variation of the polysilicon resistance element can be reduced and the chip manufacturing process can be shortened.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG.
In the same process as the conventional example described by (a) and (b), P
After forming the N-type buried layer 2, the N-type epitaxial layer 3, the insulating diffusion layer 4, and the first insulating layer 5 on the type silicon substrate 1, the first insulating layer 5 is selectively formed by photolithography. Etch away and open active base diffusion window. Then MB
By the E method, for example, P type impurities of 1.0 × 10 ¹⁹ / cm
^The active base layer 7 (1000 Å) containing about ² and the first polysilicon layer 8 (1000 Å) are simultaneously formed. Next, as shown in FIG. 1 (b), the first polysilicon layer 8 is selectively removed by etching by a photo-etching method to form a resistance pattern, and then the photo-etching method is used as in the conventional example. Then, a large amount of P-type impurities are ion-implanted to form the base high-concentration layer 9. Next, the second insulating layer 10 (30
After depositing 00 Å), the second insulating layer 10 is selectively etched and removed by a photo-etching method to open an emitter diffusion window and a collector contact window. Next, as shown in FIG. 1C, after depositing the second polysilicon layer 11 in the same manner as in the conventional example, a large amount of impurities are ion-implanted from the upper surface. Next, after heat treatment at a high temperature to form the emitter layer 12, the second polysilicon layer 11 is selectively etched by a photo-etching method. Next, the second insulating layer 10 is selectively removed by photoetching to open the base contact window and the resistance contact window, and then an electrode metal is vapor-deposited to form the emitter electrode 13, the base electrode 14, and the collector electrode. 15 and the resistance electrode 16 are formed.

2 (a) to 2 (d) are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

First, as shown in FIG.
In the same manner as the conventional example described in (a) and (b), P
After the N-type buried layer 2, the N-type epitaxial layer 3, the insulating diffusion layer 4, and the first insulating layer 5 are formed on the silicon substrate 1, the P-type impurities are selectively and sequentially formed on the upper surface by photolithography. Ion implantation (20 KeV, 1 × 10 ¹⁴ / cm ² , 1
5 KeV, 1 × 10 ¹⁵ / cm ² ) and the active base layer 2
2. Base high concentration layer 9 is formed. Next, the first insulating layer 5 is selectively removed by etching by photolithography to open the emitter diffusion window and the collector contact window. Next, as shown in FIG. 2B, for example, N
An emitter layer containing a type impurity of about 5.0 × 10 ²⁰ / cm ² and a collector layer 23 (1500Å) and a fourth polysilicon layer 24 (1500Å) are simultaneously formed. Next, as shown in FIG. 2 (c), a fourth photo-etching method is selectively performed.
After removing the polysilicon layer 24 by etching to form a resistance pattern, a fourth insulating layer 20 (3000 Å) is deposited. Next, after heat treatment (900 ° C., 20 minutes) to stabilize the fourth polysilicon layer 19, the fourth insulating layer 20 is selectively removed by photolithography. Next, as shown in FIG. 2D, after opening the base contact window and the resistance contact window as in the conventional example,
Emitter electrode 13, base electrode 14, collector electrode 15
And the resistance electrode 16 is formed.

[0015]

As described above, according to the present invention, the polysilicon resistance element is formed at the same time as the active base layer or the emitter layer by using the MBE method having excellent controllability. It is possible to reduce the variation of the impurity concentration to about half that of the conventional one, and as a result, the variation of the polysilicon resistance is halved, and the P / W non-defective rate,
Since the W yield can be significantly improved, and in the present invention, the impurity concentration of the polysilicon layer can be formed uniformly, the etching sidewall cross-sectional shape of the polysilicon layer has an ideal tapered shape (angle 70 °). ) Is effective.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit according to the second embodiment of the present invention.

FIG. 3 is a process sectional view showing a conventional method for manufacturing a semiconductor integrated circuit.

[Explanation of symbols]

 1 P-type silicon substrate 2 N-type buried layer 3 N-type epitaxial layer 4 Insulation diffusion layer 5 First insulation layer 6 Collector diffusion layer 7 Active base layer 8 First polysilicon layer 9 Base high-concentration layer 10 Second Insulating layer 11 Second polysilicon layer 12 Emitter layer 13 Emitter electrode 14 Base electrode 15 Collector electrode 16 Polysilicon resistance electrode 17 Second insulating layer 18 Third insulating layer 19 Third polysilicon layer 20 Fourth insulating layer Layer 21 Fifth Insulating Layer 22 Active Base Layer 23 Emitter Single Crystal Silicon Layer 24 Fourth Polysilicon Layer

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[Procedure amendment]

[Submission date] May 17, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73 // H01L 21/203 M 8122-4M

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit in which a polysilicon resistance element is provided on an insulating layer formed on one main surface of a one conductivity type semiconductor substrate, wherein the polysilicon resistance element is an active base layer or an emitter. A method for manufacturing a semiconductor integrated circuit, which is formed simultaneously with the layers.