KR100203906B1 - Method for forming an element isolation region in a semiconductor device - Google Patents
Method for forming an element isolation region in a semiconductor device Download PDFInfo
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- KR100203906B1 KR100203906B1 KR1019960025717A KR19960025717A KR100203906B1 KR 100203906 B1 KR100203906 B1 KR 100203906B1 KR 1019960025717 A KR1019960025717 A KR 1019960025717A KR 19960025717 A KR19960025717 A KR 19960025717A KR 100203906 B1 KR100203906 B1 KR 100203906B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Abstract
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 트랜치 소자분리 공정에서 나타나는 소자분리 산화막의 측벽부분에서 게이트 산화막의 열화를 방지하기 위한 것으로, 소자분리 영역으로 정의된 지역의 질화막과 패드 산화막을 제거한 뒤, 전체구조 상부에 비정질 실리콘을 증착하고 전멱식각으로 트랜치를 형성함과 아울러, 트랜치의 양측벽에 상기 비정질 실리콘 스페이서를 형성한 다음 식각된 트랜치 표면을 얇게 산화시킴으로써, 트랜치가 형성된 실리콘 표면의 얇은 열산화막의 균일한 두께가 형성되도록 하여 게이트 산화막의 열화를 방지하고 이로써 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있다.The present invention relates to a method of manufacturing a device isolation film of a semiconductor device, and to prevent deterioration of the gate oxide film in the sidewall portion of the device isolation oxide film formed in the trench device isolation process, the nitride film and the pad oxide film in the region defined as the device isolation region. After the removal, the amorphous silicon is deposited on the entire structure, the trench is formed by electroetching, the amorphous silicon spacer is formed on both sidewalls of the trench, and the etched trench surface is thinly oxidized. A uniform thickness of the thin thermal oxide film may be formed to prevent deterioration of the gate oxide film, thereby improving production yield and reliability of the semiconductor device.
Description
제1a도 내지 제1c도는 종래의 기술에 따른 반도체 소자의 소자분리막 제조공정도.1A to 1C are diagrams illustrating a device isolation film manufacturing process of a semiconductor device according to the related art.
제2a도 내지 제2g도는 본 발명의 기술에 따른 반도체 소자의 소자분리막 제조공정도.2a to 2g is a manufacturing process of the device isolation film of a semiconductor device according to the technology of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 20 : 실리콘 기판 11, 21 : 패드 산화막11, 20: silicon substrate 11, 21: pad oxide film
12, 22 : 질화막 14, 26 : 트랜치(Trench)12, 22: nitride film 14, 26: trench
15 : 열산화막 16, 28 : 소자분리막15: thermal oxide film 16, 28: device isolation film
25 : 비정질 실리콘막 27 : 측벽 산화막25 amorphous silicon film 27 sidewall oxide film
30 : 실리콘 스페이서30: silicon spacer
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 특히 트랜치가 형성된 실리콘표면의 데미지(Demage)제거를 위해 형성하는 얇은 열산화막의 두께를 균일한 두께로 형성함으로써, 게이트 산화막의 열화를 방지하여 반도체소자의 제조수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리막 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and in particular, by forming a uniform thickness of the thin thermal oxide film formed to remove the damage on the trench-formed silicon surface, to prevent deterioration of the gate oxide film The present invention relates to a device isolation film manufacturing method of a semiconductor device capable of improving the manufacturing yield and reliability of the semiconductor device.
종래의 기술에 따른 반도체 소자의 소자분리막 제조공정에 대해 첨부도면을 참조하여 살펴보기로 한다.A device isolation film manufacturing process of a semiconductor device according to the related art will be described with reference to the accompanying drawings.
제1a도 내지 제1c도는 종래의 기술에 따른 반도체 소자의 소자분리막 제조공정도이다.1A to 1C are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the related art.
먼저, 실리콘 기판(10) 위에 얇은 패트 산화막(11)과 두꺼운 질화막(12)을 차례로 형성한 후, 소자분리 영역의 질화막(12)과 산화막(11)을 제거한다.First, the thin pat oxide film 11 and the thick nitride film 12 are sequentially formed on the silicon substrate 10, and then the nitride film 12 and the oxide film 11 in the device isolation region are removed.
다음 계속하여 노출된 실리콘 기판(10)을 일정깊이로 건식식각하여 트랜치(14)를 형성한다(제1a도 참조).Next, the exposed silicon substrate 10 is dry-etched to a predetermined depth to form the trench 14 (see FIG. 1A).
다음, 상기 트랜치(14) 형성을 위해 실리콘 기판(10)을 건식식각할 때 발생한 데미지를 없애기 위해 실리콘 기판(10)의 표면을 얇게 산화시켜 열산화막(15)을 형성한 뒤 상기 열산화막(15)을 습식식각으로 제거한다(제1b도 참조).Next, the thermal oxide film 15 is formed by thinly oxidizing the surface of the silicon substrate 10 in order to eliminate damage generated when the silicon substrate 10 is dry-etched to form the trench 14. ) Is removed by wet etching (see also part 1b).
다음 전체구조 상부에서 화학기상증착(Chemical Vapor Deposition; 이하 CVD라 칭함.)법으로 산화막(이하 CVD 산화막이라 칭함.)으로 상기 식각된 실리콘 기판(10)의 표면을 매립한다.Next, the surface of the etched silicon substrate 10 is buried in an oxide film (hereinafter referred to as a CVD oxide film) by chemical vapor deposition (CVD).
그후 화학-기계적 연마(Chemical Mechanica Polishing; 이하 CMP라 칭함.) 공정이나 건식식각으로 평탄화하고 상부의 질화막(12)과 패드 산화막(11)을 제거한다.After that, it is planarized by chemical mechanical polishing (hereinafter referred to as CMP) process or dry etching, and the upper nitride film 12 and the pad oxide film 11 are removed.
이때 상기의 종래의 기술에 있어서, 트랜치(14) 형성후 실시하는 얇은 열산화막(15) 형성시 식각된 실리콘의 코너부위에서 산화가 제대로 이루어지지 않게 되고, 또한 소자분리막 상부 측벽부분의 전기적 집중현상으로 인해 게이트 산화막의 열화가 발생될 수 있어 결국 반도체 소자의 신뢰성을 저하시키게 되는 문제점이 있다.At this time, in the conventional technique, the oxidation is not properly performed at the corners of the etched silicon when the thin thermal oxide film 15 formed after the trench 14 is formed, and the electric concentration of the upper sidewall of the device isolation film As a result, deterioration of the gate oxide film may occur, resulting in a decrease in reliability of the semiconductor device.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 소자분리 영역으로 정의된 지역의 질화막과 패드 산화막을 제거한 뒤, 전체 구조 상부에 비정질 실리콘을 증착하고 전면식각으로 트랜치를 형성함과 아울러, 트랜치의 양측벽에 상기 비정질 실리콘 스페이서를 형성한 다음 식각된 트랜치 표면을 얇게 산화시킴으로써 트랜치가 형성된 실리콘 표면의 얇은 열산화막의 균일한 두께가 형성되도록 하여 게이트 산화막의 열화를 방지하고 이에 의해 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자 분리 막 제조방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention removes the nitride film and the pad oxide film in the region defined as the device isolation region, deposits amorphous silicon on the entire structure, and forms trenches by etching the entire surface. By forming the amorphous silicon spacer on the wall and thinly oxidizing the etched trench surface, a uniform thickness of a thin thermal oxide film on the trenched silicon surface is formed to prevent deterioration of the gate oxide film, thereby producing a semiconductor device It is an object of the present invention to provide a method for manufacturing a device isolation film of a semiconductor device capable of improving reliability.
상기 목적을 달성하기 위한 본 발명의 방법에 의하면, 실리콘 기판 상부에 패드 산화막과 질화막을 차례로 형성하는 단계와 마스크 공정으로 소자분리 영역을 정의하는 단계와, 상기 소자분리영역으로 정의된 지역의 질화막과 패드 산화막을 차례로 건식식각하여 제거하는 단계와, 전체구조 상부에 비정질실리콘을 소정 두께 형성하는 단계와, 상기 비정질실리콘을 전면 건식식각으로 식각하여 상기 소자분리 영역 양측벽에 비정질 실리콘 스페이서를 형성하는 단계와, 소자분리영역의 노출된 실리콘 기판을 일정깊이로 식각하여 트랜치를 형성하는 단계와, 상기 트랜치의 양측벽을 열산화시켜 열산화막을 형성하는 단계와, 상기 형성된 열산화막을 습식식각하여 제거하는 단계와, 전체구조 상부에 소자분리 산화막을 소정두께로 형성하는 단계와, 상기 소자영역의 소자분리 산화막을 건식식각하여 제거하는 단계와, 노출된 상기 질화막을 습식식각으로 제거하고 패드산화막을 습식식각으로 제거하는 단계로 구성됨을 특징으로 한다.According to the method of the present invention for achieving the above object, the step of forming a pad oxide film and a nitride film on the silicon substrate in order and defining a device isolation region by a mask process, a nitride film of the region defined as the device isolation region and Dry etching the pad oxide layer in order, forming a predetermined thickness of amorphous silicon on the entire structure, and etching the amorphous silicon by dry etching on the entire surface to form amorphous silicon spacers on both sidewalls of the device isolation region. And forming a trench by etching the exposed silicon substrate of the device isolation region to a predetermined depth, thermally oxidizing both side walls of the trench to form a thermal oxide layer, and wet etching the formed thermal oxide layer to remove the trench. Forming a device isolation oxide film in a predetermined thickness on the entire structure; And an element isolation oxide film of the element region, characterized by consisting of a method comprising the step of removing by dry etching, removing the exposed nitride film by wet etching, and removing the pad oxide film by wet etching.
이하 본 발명에 따른 반도체 소자의 소자분리막 제조방법에 대해 첨부도면을 참조하여 보다 상세히 설명하기로 한다.Hereinafter, a device isolation film manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2e도는 본 발명의 방법에 따른 반도체 소자의 소자분리막 제조공정도이다.2A through 2E are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the method of the present invention.
제2a도를 참조하면, 실리콘 기판(20)에 패드 산화막(11)을 소정 두께 예컨대, 약 50-300Å로 형성한 후, 상기 패드산화막(11) 위에 질화막(22)을 700-5000Å 형성한다.Referring to FIG. 2A, after the pad oxide film 11 is formed on the silicon substrate 20 to have a predetermined thickness, for example, about 50-300 GPa, the nitride film 22 is formed on the pad oxide film 11.
다음 마스크 공정으로 소자분리영역(50)을 정의한 후 상기 정의된 영역의 질화막(22)과 패드산화막(21)을 제거한 다음, 상기 마스크 공정시 사용하였던 감광막(미도시)을 제거한다.(제2a도 참조)After the device isolation region 50 is defined by the next mask process, the nitride layer 22 and the pad oxide layer 21 of the defined region are removed, and then the photoresist layer (not shown) used in the mask process is removed. See also)
전체 표면에 비정질실리콘(25)을 70-5000Å 두께로 증착한다.Amorphous silicon 25 is deposited to 70-5000 mm thick on the entire surface.
이때 상기 비정질실리콘(25) 대신 폴리실리콘으로 사용할 수 있다.(제2b도 참조)In this case, polysilicon may be used instead of the amorphous silicon 25 (see also 2b).
상기 비정질실리콘(25)을 건식식각하여 소자분리영역(50)의 가장자리에 실리콘 스페이서(30)을 형성한다.(제2c도 참조)The amorphous silicon 25 is dry etched to form a silicon spacer 30 at the edge of the device isolation region 50 (see also FIG. 2C).
소자분리영역에 노출된 실리콘 기판(20)을 건식식각하여 2000-5000Å 깊이의 트랜치(26)를 형성한다.The silicon substrate 20 exposed to the device isolation region is dry etched to form a trench 26 having a depth of 2000-5000 Å.
이때, 상기 실리콘 스페이서(30)는 실리콘 기판(20)과 같이 식각되어 일부만 남고(30') 소자영역은 질화막(22)이 마스크 작용을 하여 식각되지 않는다.(제2c도 참조)At this time, the silicon spacer 30 is etched like the silicon substrate 20, and only a part thereof remains (30 '), and the device region is not etched by the nitride film 22 acting as a mask (see also 2c).
다음 상기 트랜치(26)형성을 위해 식각된 소자분리 영역의 실리콘(20) 표면을 얇게 열산화시켜 상기 트랜치 식각시에 생긴 데미지를 없애기 위한 측벽 열산화막(27)을 100-500Å 두께로 형성한다.Next, a thin thermal oxidation of the surface of the silicon 20 of the device isolation region etched to form the trench 26 is performed to form a sidewall thermal oxidation layer 27 having a thickness of 100-500 Å to eliminate damage caused during the trench etching.
이때 상기 실리콘 스페이서(30')도 함께 산화된다.(제2e도 참조)At this time, the silicon spacer 30 'is also oxidized (see also 2e).
다음 상기 열산화막(27)을 HF나 BOE(Buffered Oxide Etchent)용액을 사용하여 제거하고 전체구조 상부에 CVD산화막(28) 예컨대, O3-TEOS나 BPSG(Boro Phosphorus Siligate)를 사용하여 상기 식각된 소자분리 영역을 매립한다.Next, the thermal oxide layer 27 is removed using HF or BOE (Buffered Oxide Etchent) solution and etched using the CVD oxide layer 28, for example, O 3 -TEOS or BPSG (Boro Phosphorus Siligate) on the entire structure. Buried the device isolation region.
이때 상기 CVD 산화막(28)의 증착두께는 건식식각이나 CMP 공정으로 상기 산화막(28)을 제거할 때 상기 패드 산화막(21)보다 높은 위치에 있도록 충분한 두께인 약 2000-10000Å 두께로 증착한다.(제2f도 참조)At this time, the deposition thickness of the CVD oxide film 28 is deposited to a thickness of about 2000-10000 kPa, which is sufficient to be located at a position higher than the pad oxide film 21 when the oxide film 28 is removed by dry etching or a CMP process. See also 2f)
다음 인산용액으로 상기 질화막(22)과 패드산화막(21)을 제거하여 최종 소자분리막(28')을 형성한다.Next, the nitride layer 22 and the pad oxide layer 21 are removed with a phosphate solution to form a final device isolation layer 28 '.
이상 상기와 같이 본 발명은 트랜치 소자분리 공정에서 나타나는 소자분리 산화막의 측벽부분에서 게이트 산화막의 열화를 방지하기 위한 것으로, 소자분리 영역으로 정의된 지역의 질화막과 패드 산화막을 제거한 뒤, 전체구조 상부에 비정질 실리콘을 증착하고 전멱식각으로 트랜치를 형성함과 아울러, 트랜치의 양측벽에 상기 비정질 실리콘 스페이서를 형성한 다음 식각된 트랜치 표면을 얇게 산화시킴으로써, 트랜치가 형성된 실리콘 표면의 얇은 열산화막의 균일한 두께가 형성되도록 하여 게이트 산화막의 열화를 방지하고 이로써 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있다.As described above, the present invention is to prevent deterioration of the gate oxide film in the sidewall portion of the device isolation oxide film in the trench device isolation process, and after removing the nitride film and the pad oxide film in the region defined as the device isolation region, Uniform thickness of thin thermal oxide film on the trenched silicon surface by depositing amorphous silicon, forming trenches by electrode etching, forming the amorphous silicon spacers on both side walls of the trench, and then oxidizing the etched trench surface thinly. Can be formed to prevent deterioration of the gate oxide film, thereby improving the manufacturing yield and reliability of the semiconductor device.
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| KR1019960025717A KR100203906B1 (en) | 1996-06-29 | 1996-06-29 | Method for forming an element isolation region in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100671155B1 (en) * | 2001-06-26 | 2007-01-17 | 매그나칩 반도체 유한회사 | Method for manufacturing an isolation layer in a semiconductor device |
| KR100894791B1 (en) * | 2002-10-24 | 2009-04-24 | 매그나칩 반도체 유한회사 | Method of forming a isolation layer in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100671155B1 (en) * | 2001-06-26 | 2007-01-17 | 매그나칩 반도체 유한회사 | Method for manufacturing an isolation layer in a semiconductor device |
| KR100894791B1 (en) * | 2002-10-24 | 2009-04-24 | 매그나칩 반도체 유한회사 | Method of forming a isolation layer in a semiconductor device |
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| KR980006086A (en) | 1998-03-30 |
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